Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 19)
+++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 57)
@@ -32,7 +32,8 @@
 //#define IDEBUG // Update tab debug
 //#define DDEBUG // Directory debug
+//#define LOCK_DEBUG // Lock debug
 //#define DEBUG_VCI_MEM_CACHE 1
+#define DEBUG_START_CYCLE 8750000
 #define RANDOMIZE_SC
-#define NCYCLES -1
 namespace soclib { namespace caba {
 
@@ -134,4 +135,6 @@
     "XRAM_RSP_INVAL",
     "XRAM_RSP_WRITE_DIRTY",
+    "XRAM_RSP_HEAP_ERASE",
+    "XRAM_RSP_HEAP_LAST",
   };
   const char *ixr_cmd_fsm_str[] = {
@@ -581,5 +584,5 @@
 
 #if DEBUG_VCI_MEM_CACHE 
-if(m_cpt_cycles > NCYCLES){
+if(m_cpt_cycles > DEBUG_START_CYCLE){
     std::cout << "---------------------------------------------" << std::dec << std::endl;
     std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
@@ -758,7 +761,10 @@
             bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl;
 	m_update_tab.print();
+}
 #endif
+            while(!valid);
             assert ( valid 
                 && "VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" );
@@ -782,6 +788,8 @@
             m_update_tab.clear(r_init_rsp_upt_index.read());
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl;
 	m_update_tab.print();
+}
 #endif
           }
@@ -835,9 +843,10 @@
             DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	   std::cout << "In READ_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
 	   entry.print();
 	   std::cout << "done" << std::endl;
+}
 #endif
-
             r_read_is_cnt   = entry.is_cnt;
             r_read_dirty    = entry.dirty;
@@ -888,5 +897,5 @@
             entry.tag	  = r_read_tag.read();
             entry.lock	  = r_read_lock.read();
-            entry.ptr     = 0;
+            entry.ptr     = r_read_ptr.read();
             if(cached_read){  // Cached read, we update the copy
               if(!is_cnt){ // Not counter mode
@@ -905,7 +914,9 @@
             }
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	   std::cout << "In READ_DIR_HIT printing the entry of address is : " << std::endl;
 	   entry.print();
 	   std::cout << "done" << std::endl;
+}
 #endif
 
@@ -946,7 +957,9 @@
             }
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	   std::cout << "In READ_HEAP_LOCK printing the entry of address is : " << std::endl;
 	   entry.print();
 	   std::cout << "done" << std::endl;
+}
 #endif
 
@@ -1064,5 +1077,7 @@
           if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+}
 #endif
             size_t index = 0;
@@ -1095,7 +1110,9 @@
                 std::vector<data_t>(m_words,0));
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_SET transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -1336,8 +1353,10 @@
             }
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
 	std::cout << sc_time_stamp() << " " << name() << " WRITE_UPT_LOCK update table : " << std::endl;
 	m_update_tab.print();
             }
+}
 #endif
             r_write_upt_index = index;
@@ -1456,5 +1475,7 @@
           if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+}
 #endif
             size_t hit_index = 0;
@@ -1507,7 +1528,9 @@
                 data_vector);
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -1533,7 +1556,9 @@
             r_write_fsm = WRITE_RSP;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -1592,8 +1617,10 @@
                 index);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
 	std::cout << sc_time_stamp() << " " << name() << " WRITE_INVAL_LOCK update table : " << std::endl;
 	m_update_tab.print();
             }
+}
 #endif
             r_write_upt_index = index;
@@ -1624,7 +1651,9 @@
                 std::vector<data_t>(m_words,0));
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -1830,7 +1859,9 @@
             r_ixr_rsp_fsm = IXR_RSP_IDLE;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -1851,7 +1882,9 @@
             if ( eop ) {
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -1900,5 +1933,7 @@
               break;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl;
+}
 #endif
             }
@@ -1912,5 +1947,7 @@
             r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl;
+}
 #endif
           }
@@ -1948,7 +1985,9 @@
             r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl;
 	std::cout << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl;
 	victim.print();
+}
 #endif
           }
@@ -1960,5 +1999,7 @@
           if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) {
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state" << std::endl;
+}
 #endif
             size_t index;
@@ -1966,7 +2007,9 @@
               r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
     std::cout << "A invalidation is already registered at this address" << std::endl;
 	m_update_tab.print();
+}
 #endif
 
@@ -1975,7 +2018,9 @@
 	      r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
     std::cout << "The inval tab is full" << std::endl;
 	m_update_tab.print();
+}
 #endif
 	    }
@@ -1983,6 +2028,8 @@
               r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl;
 	m_update_tab.print();
+}
 #endif
             }
@@ -1996,5 +2043,7 @@
           break;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl;
+}
 #endif
         }
@@ -2042,13 +2091,17 @@
           m_cache_directory.write(set, way, entry);
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	   std::cout << "printing the entry : " << std::endl;
 	   entry.print();
 	   std::cout << "done" << std::endl;
+}
 #endif
 
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -2069,6 +2122,8 @@
 
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             std::cout << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl;
             m_update_tab.print();
+}
 #endif
             r_xram_rsp_upt_index = index;
@@ -2105,7 +2160,9 @@
                 std::vector<data_t>(m_words,0) );
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -2135,5 +2192,7 @@
 
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl;
+}
 #endif
           }
@@ -2164,5 +2223,7 @@
             else                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl;
+}
 #endif
           }
@@ -2185,5 +2246,7 @@
             else                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl;
+}
 #endif
           }
@@ -2286,7 +2349,9 @@
            DirectoryEntry entry = m_cache_directory.read(cleanup_address , way);
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	   std::cout << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl;
 	   entry.print();
 	   std::cout << "done" << std::endl;
+}
 #endif
             r_cleanup_is_cnt    = entry.is_cnt;
@@ -2513,5 +2578,5 @@
             if(!hit_inval) {
 #ifdef DEBUG_VCI_MEM_CACHE
-if(m_cpt_total_cycles > NCYCLES)
+if(m_cpt_cycles > DEBUG_START_CYCLE)
               std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl;
 #endif
@@ -2536,6 +2601,8 @@
             m_update_tab.clear(r_cleanup_index.read());
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl;
 	m_update_tab.print();
+}
 #endif
 
@@ -2605,7 +2672,9 @@
           if( m_cmd_llsc_addr_fifo.rok() ) {
 #ifdef LOCK_DEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             std::cout << "SC data : " << m_cmd_llsc_wdata_fifo.read() << std::endl;
             std::cout << "SC addr : " << std::hex << m_cmd_llsc_addr_fifo.read() << std::dec << std::endl;
             std::cout << "SC cpt  : " << r_llsc_cpt.read() << std::endl;
+}
 #endif
             if(m_cmd_llsc_eop_fifo.read()){
@@ -2613,5 +2682,7 @@
               r_llsc_fsm = SC_DIR_LOCK;
 #ifdef LOCK_DEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
               std::cout << "SC eop" << std::endl;
+}
 #endif
             } else { // we keep the last word
@@ -2681,4 +2752,5 @@
 
 #ifdef LOCK_DEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
           std::cout << "SC_DIR_HIT_READ ok ? " << ok << std::endl;
           if(!ok){
@@ -2693,4 +2765,5 @@
                   std::cout << "SC_DIR_HIT_READ wdata 1      : " << m_cmd_llsc_wdata_fifo.read() << std::endl;
           }
+}
 #endif
           if(ok){
@@ -2770,8 +2843,10 @@
             }
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
 	std::cout << sc_time_stamp() << " " << name() << " SC_UPT_LOCK update table : " << std::endl;
 	m_update_tab.print();
             }
+}
 #endif
             r_llsc_upt_index = index;
@@ -2822,5 +2897,7 @@
             if(r_llsc_count.read() == 1){
 #ifdef LOCK_DEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
               std::cout << "SC_UPT_REQ, only one owner : " << r_llsc_copy.read() << std::endl;
+}
 #endif
               r_llsc_fsm = LLSC_IDLE;
@@ -2916,8 +2993,10 @@
                 index);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
 	std::cout << sc_time_stamp() << " " << name() << " LLSC_INVAL_LOCK update table : " << std::endl;
 	m_update_tab.print();
             }
+}
 #endif
             r_llsc_upt_index = index;
@@ -2947,7 +3026,9 @@
                 std::vector<data_t>(m_words,0));
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " SC_DIR_INVAL transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
@@ -3083,7 +3164,9 @@
                   data_vector);
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
 	std::cout << sc_time_stamp() << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl;
 	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
 	  m_transaction_tab.print(i);
+}
 #endif
 
