Index: /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp
===================================================================
--- /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp	(revision 579)
+++ /trunk/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp	(revision 580)
@@ -32,4 +32,6 @@
 #include "vci_block_device_tsar.h"
 
+#define DEBUG_BDEV   0
+
 namespace soclib { namespace caba {
 
@@ -65,5 +67,4 @@
             r_trdid = p_vci_target.trdid.read();
             r_pktid = p_vci_target.pktid.read();
-	    r_tdata = p_vci_target.wdata.read();
             sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read();
 
@@ -96,4 +97,10 @@
             else if(  read && (cell == BLOCK_DEVICE_SIZE) )       r_target_fsm = T_READ_SIZE;
             else if(  read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK;
+
+            // get write data value for both 32 bits and 64 bits data width
+            if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) 
+                r_tdata = (uint32_t)(p_vci_target.wdata.read()>>32);
+            else
+                r_tdata = p_vci_target.wdata.read();
         }
         break;
@@ -102,14 +109,15 @@
     case T_WRITE_BUFFER:
     {
-	if (p_vci_target.rspack.read() ) {
-#ifdef SOCLIB_MODULE_DEBUG
-	    std::cout << "vci_bd WRITE_BUFFER " << r_tdata.read()
-		<< " status " << r_initiator_fsm.read() << std::endl;
+	    if (p_vci_target.rspack.read() ) 
+        {
+            if (r_initiator_fsm.read() == M_IDLE)
+            {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_BUFFER> value = " << r_tdata.read() << std::endl;
 #endif
-            if (r_initiator_fsm.read() == M_IDLE)
-            {
                 r_buf_address = (uint64_t)r_tdata.read();
                 r_target_fsm  = T_IDLE;
-	    }
+	        }
         }
         break;
@@ -118,15 +126,15 @@
     case T_WRITE_BUFFER_EXT:
     {
-	if (p_vci_target.rspack.read() ) {
-#ifdef SOCLIB_MODULE_DEBUG
-	    std::cout << "vci_bd WRITE_BUFFER_EXT " << r_tdata.read()
-		<< " status " << r_initiator_fsm.read() << std::endl;
+        if (p_vci_target.rspack.read() ) 
+        {
+            if (r_initiator_fsm.read() == M_IDLE)
+            {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_BUFFER_EXT> value = " << r_tdata.read() << std::endl;
 #endif
-            if (r_initiator_fsm.read() == M_IDLE)
-            {
-                r_buf_address = r_buf_address.read() + 
-                            (((uint64_t)r_tdata.read())<<32);
+                r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32);
                 r_target_fsm  = T_IDLE;
-	    }
+            }
         }
         break;
@@ -135,15 +143,16 @@
     case T_WRITE_COUNT:
     {
-	if (p_vci_target.rspack.read() ) {
-#ifdef SOCLIB_MODULE_DEBUG
-	    std::cout << "vci_bd WRITE_COUNT " << r_tdata.read() <<
-		" status " << r_initiator_fsm.read() << std::endl;
+        if (p_vci_target.rspack.read() ) 
+        {
+            if (r_initiator_fsm.read() == M_IDLE)
+            {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_COUNT> value = " << r_tdata.read() << std::endl;
 #endif
-            if (r_initiator_fsm.read() == M_IDLE)
-            {
                 r_nblocks    = (uint32_t)r_tdata.read();
                 r_target_fsm = T_IDLE;
             }
-	}
+        }
         break;
     }
@@ -151,14 +160,16 @@
     case T_WRITE_LBA:
     {
-	if (p_vci_target.rspack.read() ) {
-#ifdef SOCLIB_MODULE_DEBUG
-	    std::cout << "vci_bd WRITE_LBA " << r_tdata.read() <<
-		" status " << r_initiator_fsm.read() << std::endl;
+        if (p_vci_target.rspack.read() ) 
+        {
+            if (r_initiator_fsm.read() == M_IDLE) 
+            {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_LBA> value = " << r_tdata.read() << std::endl;
 #endif
-            if (r_initiator_fsm.read() == M_IDLE) {
                 r_lba        = (uint32_t)r_tdata.read();
                 r_target_fsm = T_IDLE;
             }
-	}
+        }
         break;
     }
@@ -168,34 +179,33 @@
         if ( p_vci_target.rspack.read() )  
         {
-#ifdef SOCLIB_MODULE_DEBUG
-	    std::cout << "vci_bd WRITE_OP " << r_tdata.read() <<
-		" status " << r_initiator_fsm.read();
-#endif
             if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_READ) and
                  (r_initiator_fsm.read() == M_IDLE) )
             {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_LBA> value = READ" << std::endl;
+#endif
                 r_read = true;
                 r_go   = true;
-#ifdef SOCLIB_MODULE_DEBUG
-		std::cout << " READ";
-#endif
             }
             else if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_WRITE) and
                       (r_initiator_fsm.read() == M_IDLE) )
             {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_LBA> value = WRITE" << std::endl;
+#endif
                 r_read = false;
                 r_go   = true;
-#ifdef SOCLIB_MODULE_DEBUG
-		std::cout << " WRITE";
+            }
+            else
+            {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_LBA> value = SOFT RESET" << std::endl;
 #endif
-            }
-            else
-            {
                 r_go   = false;
             }
             r_target_fsm = T_IDLE;
-#ifdef SOCLIB_MODULE_DEBUG
-	    std::cout << std::endl;
-#endif
         }
         break;
@@ -206,7 +216,7 @@
         if ( p_vci_target.rspack.read() ) 
         {
-#ifdef SOCLIB_MODULE_DEBUG
-	    std::cout << "vci_bd WRITE_IRQEN " << r_tdata.read()
-		<< " status " << r_initiator_fsm.read() << std::endl;
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_TGT WRITE_IRQEN> value = " << r_tdata.read() << std::endl;
 #endif
             r_target_fsm = T_IDLE;
@@ -289,12 +299,9 @@
             {
                 r_initiator_fsm = M_READ_ERROR;
-#ifdef SOCLIB_MODULE_DEBUG
-		std::cout << "vci_bd M_READ_ERROR" << std::endl;
-#endif
             }
             else   
             {
                 r_burst_count   = 0;
-                r_words_count    = 0;
+                r_words_count   = 0;
                 r_initiator_fsm = M_READ_BURST;
             }
@@ -389,7 +396,4 @@
             {
                 r_initiator_fsm = M_READ_ERROR;
-#ifdef SOCLIB_MODULE_DEBUG
-		std::cout << "vci_bd M_READ_ERROR" << std::endl;
-#endif
             }
             else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 
@@ -399,7 +403,4 @@
                 {
                     r_initiator_fsm = M_READ_SUCCESS;
-#ifdef SOCLIB_MODULE_DEBUG
-		    std::cout << "vci_bd M_READ_SUCCESS" << std::endl;
-#endif
                 }
                 else                                              // last burst not last block
@@ -480,7 +481,4 @@
                 {
                     r_initiator_fsm = M_WRITE_ERROR;
-#ifdef SOCLIB_MODULE_DEBUG
-		    std::cout << "vci_bd M_WRITE_ERROR" << std::endl;
-#endif
                 }
                 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 
@@ -512,14 +510,8 @@
             {
                 r_initiator_fsm = M_WRITE_ERROR; 
-#ifdef SOCLIB_MODULE_DEBUG
-		std::cout << "vci_bd M_WRITE_ERROR" << std::endl;
-#endif
             }
             else if ( r_block_count.read() == r_nblocks.read() - 1 ) 
             {
                 r_initiator_fsm = M_WRITE_SUCCESS; 
-#ifdef SOCLIB_MODULE_DEBUG
-		std::cout << "vci_bd M_WRITE_SUCCESS" << std::endl;
-#endif
             }
             else
@@ -693,10 +685,16 @@
           (r_initiator_fsm == M_READ_ERROR)    ||
           (r_initiator_fsm == M_WRITE_ERROR) ) &&  
-         r_irq_enable.read() ) {
-#ifdef SOCLIB_MODULE_DEBUG
-		std::cout << "vci_bd send IRQ" << std::endl;
+         r_irq_enable.read() ) 
+    {
+
+#if DEBUG_BDEV
+std::cout << "  <BDEV_INI send IRQ>" << std::endl;
 #endif
 		p_irq = true;
-    } else			           p_irq = false;
+    } 
+    else 
+    {
+        p_irq = false;
+    }
 } // end GenMoore()
 
@@ -817,4 +815,5 @@
 } // end constructor
 
+/////////////////////////////////
 tmpl(/**/)::~VciBlockDeviceTsar()
 {
@@ -828,47 +827,49 @@
 	const char* initiator_str[] = 
     {
-		"IDLE",
-
-		"READ_BLOCK",
-		"READ_BURST",
-		"READ_CMD",
-		"READ_RSP",
-		"READ_SUCCESS",
-		"READ_ERROR",
-
-		"WRITE_BURST",
-		"WRITE_CMD",
-		"WRITE_RSP",
-		"WRITE_BLOCK",
-		"WRITE_SUCCESS",
-		"WRITE_ERROR",
+		"INI_IDLE",
+
+		"INI_READ_BLOCK",
+		"INI_READ_BURST",
+		"INI_READ_CMD",
+		"INI_READ_RSP",
+		"INI_READ_SUCCESS",
+		"INI_READ_ERROR",
+
+		"INI_WRITE_BURST",
+		"INI_WRITE_CMD",
+		"INI_WRITE_RSP",
+		"INI_WRITE_BLOCK",
+		"INI_WRITE_SUCCESS",
+		"INI_WRITE_ERROR",
 	};
 	const char* target_str[] = 
     {
-		"IDLE",
-		"WRITE_BUFFER",
-		"READ_BUFFER",
-		"WRITE_BUFFER_EXT",
-		"READ_BUFFER_EXT",
-		"WRITE_COUNT",
-		"READ_COUNT",
-		"WRITE_LBA",
-		"READ_LBA",
-		"WRITE_OP",
-		"READ_STATUS",
-		"WRITE_IRQEN",
-		"READ_IRQEN",
-		"READ_SIZE",
-		"READ_BLOCK",
-		"READ_ERROR",
-		"WRITE_ERROR ",
+		"TGT_IDLE",
+		"TGT_WRITE_BUFFER",
+		"TGT_READ_BUFFER",
+		"TGT_WRITE_BUFFER_EXT",
+		"TGT_READ_BUFFER_EXT",
+		"TGT_WRITE_COUNT",
+		"TGT_READ_COUNT",
+		"TGT_WRITE_LBA",
+		"TGT_READ_LBA",
+		"TGT_WRITE_OP",
+		"TGT_READ_STATUS",
+		"TGT_WRITE_IRQEN",
+		"TGT_READ_IRQEN",
+		"TGT_READ_SIZE",
+		"TGT_READ_BLOCK",
+		"TGT_READ_ERROR",
+		"TGT_WRITE_ERROR ",
 	};
 
-	std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()] 
-		  << "  BDEV_INI : " << initiator_str[r_initiator_fsm.read()] 
-          << "  buf = " << std::hex << r_buf_address.read()
-		  << "  block = " << std::dec << r_block_count.read() 
-		  << "  burst = " << r_burst_count.read() 
-		  << "  word  = " << r_words_count.read() <<std::endl; 
+	std::cout << "BDEV " << name()
+              << " : " << target_str[r_target_fsm.read()] 
+		      << " / " << initiator_str[r_initiator_fsm.read()] 
+              << " / buf = " << std::hex << r_buf_address.read()
+              << " / lba = " << std::hex << r_lba.read()
+		      << " / block_count = " << std::dec << r_block_count.read() 
+		      << " / burst_count = " << r_burst_count.read() 
+		      << " / word_count = " << r_words_count.read() <<std::endl; 
 }