Index: trunk/modules/vci_spi/caba/source/include/vci_spi.h
===================================================================
--- trunk/modules/vci_spi/caba/source/include/vci_spi.h	(revision 592)
+++ trunk/modules/vci_spi/caba/source/include/vci_spi.h	(revision 594)
@@ -122,8 +122,9 @@
     M_READ_CMD          = 2,
     M_READ_RSP          = 3,
-    M_WRITE_WAIT        = 4,
-    M_WRITE_CMD         = 5,
-    M_WRITE_RSP         = 6,
-    M_WRITE_END         = 7
+    M_READ_END          = 4,
+    M_WRITE_WAIT        = 5,
+    M_WRITE_CMD         = 6,
+    M_WRITE_RSP         = 7,
+    M_WRITE_END         = 8
     };
 
Index: trunk/modules/vci_spi/caba/source/src/vci_spi.cpp
===================================================================
--- trunk/modules/vci_spi/caba/source/src/vci_spi.cpp	(revision 592)
+++ trunk/modules/vci_spi/caba/source/src/vci_spi.cpp	(revision 594)
@@ -417,5 +417,5 @@
 		r_dma_count = 0;
 		r_dma_error = true;
-	        r_initiator_fsm = M_IDLE;
+	        r_initiator_fsm = M_READ_END;
 #ifdef SOCLIB_MODULE_DEBUG
 		std::cout << "vci_bd M_READ_ERROR" << std::endl;
@@ -425,5 +425,5 @@
 	    {
 		r_dma_count = 0;
-		r_initiator_fsm = M_IDLE;
+		r_initiator_fsm = M_READ_END;
 		r_dma_error = false;
 #ifdef SOCLIB_MODULE_DEBUG
@@ -439,4 +439,10 @@
 	break;
     }
+    ///////////////////
+    case M_READ_END: 
+	// wait one cycle because VHDL can't update r_dma_count
+	// in the same cycle as going back IDLE
+	r_initiator_fsm = M_IDLE;
+	break;
     ///////////////////
     case M_WRITE_WAIT:  // wait for the FIFO to be empty
@@ -733,4 +739,5 @@
 		"M_READ_CMD",
 		"M_READ_RSP",
+		"M_READ_END",
 
 		"M_WRITE_WAIT",