Index: trunk/modules/vci_spi/caba/source/include/vci_spi.h
===================================================================
--- trunk/modules/vci_spi/caba/source/include/vci_spi.h	(revision 594)
+++ trunk/modules/vci_spi/caba/source/include/vci_spi.h	(revision 595)
@@ -122,5 +122,5 @@
     M_READ_CMD          = 2,
     M_READ_RSP          = 3,
-    M_READ_END          = 4,
+    M_INTR              = 4,
     M_WRITE_WAIT        = 5,
     M_WRITE_CMD         = 6,
Index: trunk/modules/vci_spi/caba/source/src/vci_spi.cpp
===================================================================
--- trunk/modules/vci_spi/caba/source/src/vci_spi.cpp	(revision 594)
+++ trunk/modules/vci_spi/caba/source/src/vci_spi.cpp	(revision 595)
@@ -59,4 +59,5 @@
 	r_spi_bsy         = false;
 	r_dma_count       = 0;
+	r_dma_error       = false;
 	r_spi_clk_counter = 0xffff;
 	r_spi_clk	  = 0;
@@ -178,5 +179,5 @@
 #endif
 		    } else {
-			r_irq = r_irq & r_spi_bsy;
+			r_irq = false;
 		    }
 		    r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ;
@@ -417,5 +418,5 @@
 		r_dma_count = 0;
 		r_dma_error = true;
-	        r_initiator_fsm = M_READ_END;
+	        r_initiator_fsm = M_INTR;
 #ifdef SOCLIB_MODULE_DEBUG
 		std::cout << "vci_bd M_READ_ERROR" << std::endl;
@@ -425,5 +426,5 @@
 	    {
 		r_dma_count = 0;
-		r_initiator_fsm = M_READ_END;
+		r_initiator_fsm = M_INTR;
 		r_dma_error = false;
 #ifdef SOCLIB_MODULE_DEBUG
@@ -440,8 +441,7 @@
     }
     ///////////////////
-    case M_READ_END: 
-	// wait one cycle because VHDL can't update r_dma_count
-	// in the same cycle as going back IDLE
+    case M_INTR: 
 	r_initiator_fsm = M_IDLE;
+	r_irq = true;
 	break;
     ///////////////////
@@ -502,5 +502,5 @@
     {
 	if (r_spi_fsm == S_IDLE) { // write complete
-	    r_initiator_fsm  = M_IDLE;
+	    r_initiator_fsm  = M_INTR;
 	}
 	break;
@@ -739,5 +739,5 @@
 		"M_READ_CMD",
 		"M_READ_RSP",
-		"M_READ_END",
+		"M_INTR",
 
 		"M_WRITE_WAIT",