Ignore:
Timestamp:
Dec 17, 2013, 11:11:20 AM (11 years ago)
Author:
cfuguet
Message:

Modifications in vci_mem_cache:

  • The out of segment read or write does not activate any more an assert on the memory cache. Instead, the request is sent to the XRAM and the error from the XRAM will be propagated to the processor doing the access.

The propagation of the error is done in two different ways:

  • When is a READ MISS: The error is propagated through the VCI rerror to the processor doing the read.
  • When is a WRITE MISS: The error is propagated through an IRQ which normally is connected to the local XICU.
Location:
trunk/modules/vci_mem_cache/caba/source/include
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

    r599 r601  
    466466      sc_in<bool>                                 p_clk;
    467467      sc_in<bool>                                 p_resetn;
     468      sc_out<bool>                                p_irq;
    468469      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
    469470      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
     
    904905      sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
    905906      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
     907      sc_signal<bool>     r_xram_rsp_rerror_irq;        // WRITE MISS rerror irq
     908      sc_signal<bool>     r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
     909      sc_signal<addr_t>   r_xram_rsp_rerror_address;    // WRITE MISS rerror address
     910      sc_signal<size_t>   r_xram_rsp_rerror_rsrcid;     // WRITE MISS rerror srcid
    906911
    907912      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
  • trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h

    r549 r601  
    401401    void write_rsp(const size_t      index,
    402402                   const size_t      word,
    403                    const wide_data_t data)
     403                   const wide_data_t data,
     404                   const bool        rerror)
    404405    {
    405406        data_t  value;
     
    417418        assert( (tab[index].xram_read ) and
    418419        "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()");
     420
     421        if ( rerror )
     422        {
     423            tab[index].rerror = true;
     424            return;
     425        }
    419426
    420427        // first 32 bits word
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