Changeset 601 for trunk/modules/vci_mem_cache/caba/source/include

Timestamp:

Dec 17, 2013, 11:11:20 AM (11 years ago)

Author:

cfuguet

Message:

Modifications in vci_mem_cache:

• The out of segment read or write does not activate any more an assert on the memory cache. Instead, the request is sent to the XRAM and the error from the XRAM will be propagated to the processor doing the access.

The propagation of the error is done in two different ways:

• When is a READ MISS: The error is propagated through the VCI rerror to the processor doing the read.

• When is a WRITE MISS: The error is propagated through an IRQ which normally is connected to the local XICU.

Location:

trunk/modules/vci_mem_cache/caba/source/include

Files:

• vci_mem_cache.h (modified) (2 diffs)
• xram_transaction.h (modified) (2 diffs)

trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -466 +466 @@
       sc_in<bool>                                 p_clk;
       sc_in<bool>                                 p_resetn;
+      sc_out<bool>                                p_irq;
       soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
       soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
@@ -904 +905 @@
       sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
       sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
+      sc_signal<bool>     r_xram_rsp_rerror_irq;        // WRITE MISS rerror irq
+      sc_signal<bool>     r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
+      sc_signal<addr_t>   r_xram_rsp_rerror_address;    // WRITE MISS rerror address
+      sc_signal<size_t>   r_xram_rsp_rerror_rsrcid;     // WRITE MISS rerror srcid
 
       // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)

trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -401 +401 @@
     void write_rsp(const size_t      index,
                    const size_t      word,
-                   const wide_data_t data)
+                   const wide_data_t data,
+                   const bool        rerror)
     {
         data_t  value;
@@ -417 +418 @@
         assert( (tab[index].xram_read ) and
         "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()");
+
+        if ( rerror )
+        {
+            tab[index].rerror = true;
+            return;
+        }
 
         // first 32 bits word