Index: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 599) +++ trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 601) @@ -466,4 +466,5 @@ sc_in p_clk; sc_in p_resetn; + sc_out p_irq; soclib::caba::VciTarget p_vci_tgt; soclib::caba::VciInitiator p_vci_ixr; @@ -904,4 +905,8 @@ sc_signal r_xram_rsp_ivt_index; // IVT entry index sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap + sc_signal r_xram_rsp_rerror_irq; // WRITE MISS rerror irq + sc_signal r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable + sc_signal r_xram_rsp_rerror_address; // WRITE MISS rerror address + sc_signal r_xram_rsp_rerror_rsrcid; // WRITE MISS rerror srcid // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) Index: trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 599) +++ trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 601) @@ -401,5 +401,6 @@ void write_rsp(const size_t index, const size_t word, - const wide_data_t data) + const wide_data_t data, + const bool rerror) { data_t value; @@ -417,4 +418,10 @@ assert( (tab[index].xram_read ) and "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()"); + + if ( rerror ) + { + tab[index].rerror = true; + return; + } // first 32 bits word Index: trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 599) +++ trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 601) @@ -1054,4 +1054,6 @@ r_xram_rsp_to_ixr_cmd_req = false; r_xram_rsp_trt_index = 0; + r_xram_rsp_rerror_irq = false; + r_xram_rsp_rerror_irq_enable = false; m_xram_rsp_to_cc_send_inst_fifo.init(); @@ -1214,22 +1216,16 @@ addr_t address = p_vci_tgt.address.read(); uint32_t plen = p_vci_tgt.plen.read(); - bool found = false; bool config = false; - for (size_t seg_id = 0; (seg_id < m_nseg) && !found; seg_id++) + for (size_t seg_id = 0; (seg_id < m_nseg) ; seg_id++) { if (m_seg[seg_id]->contains(address) && m_seg[seg_id]->contains(address + plen - vci_param_int::B)) { - found = true; if (m_seg[seg_id]->special()) config = true; } } - if (!found) /////////// out of segment error - { - r_tgt_cmd_fsm = TGT_CMD_ERROR; - } - else if (config) /////////// configuration command + if (config) /////////// configuration command { if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR; @@ -1356,4 +1352,14 @@ // X : REGISTER INDEX // // // + // For WRITE MISS error signaling: FUNC = 0x010 // + // // + // REGS_IDX // + // ============================================ // + // RESERVED | X | // + // (4 bits) | (3 bits) | // + // ============================================ // + // // + // X : REGISTER INDEX // + // // /////////////////////////////////////////////////////////// @@ -1453,4 +1459,69 @@ { error = read_instrumentation(regr, rdata); + } + else + { + error = 1; + } + + break; + } + + // xram GET bus error registers + case MEMC_RERROR: + { + need_rsp = true; + error = 0; + + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + { + switch (regr) + { + case MEMC_RERROR_IRQ_ENABLE: + r_xram_rsp_rerror_irq_enable = + (p_vci_tgt.wdata.read() != 0); + + break; + + default: + error = 1; + break; + } + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + switch (regr) + { + case MEMC_RERROR_SRCID: + rdata = (uint32_t) + r_xram_rsp_rerror_rsrcid.read(); + + break; + + case MEMC_RERROR_ADDR_LO: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read()) & + ((1ULL<<32)-1); + + break; + + case MEMC_RERROR_ADDR_HI: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read() >> 32) & + ((1ULL<<32)-1); + + break; + + case MEMC_RERROR_IRQ_RESET: + if (not r_xram_rsp_rerror_irq.read()) break; + + r_xram_rsp_rerror_irq = false; + + break; + + default: + error = 1; + break; + } } else @@ -4217,8 +4288,6 @@ r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); - assert( ((p_vci_ixr.rerror.read() & 0x1) == 0) and - "MEMC ERROR in IXR_RSP state: XRAM response error !"); - - if (p_vci_ixr.reop.read()) // PUT + if (p_vci_ixr.reop.read() and not + p_vci_ixr.rerror.read()) // PUT { r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; @@ -4249,16 +4318,13 @@ if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) { - size_t index = r_ixr_rsp_trt_index.read(); + size_t index = r_ixr_rsp_trt_index.read(); + if (m_trt.is_config(index)) // it's a config transaction { config_rsp_lines_ixr_rsp_decr = true; - m_trt.erase(index); - r_ixr_rsp_fsm = IXR_RSP_IDLE; - } - else // not a config transaction - { - m_trt.erase(index); - r_ixr_rsp_fsm = IXR_RSP_IDLE; - } + } + + m_trt.erase(index); + r_ixr_rsp_fsm = IXR_RSP_IDLE; #if DEBUG_MEMC_IXR_RSP @@ -4279,10 +4345,10 @@ bool eop = p_vci_ixr.reop.read(); wide_data_t data = p_vci_ixr.rdata.read(); - bool error = ((p_vci_ixr.rerror.read() & 0x1) == 1); - - assert(((eop == (word == (m_words-2))) or error) and + bool rerror = ((p_vci_ixr.rerror.read() & 0x1) == 1); + + assert(((eop == (word == (m_words-2))) or rerror) and "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); - m_trt.write_rsp( index, word, data ); + m_trt.write_rsp( index, word, data, rerror ); r_ixr_rsp_cpt = word + 2; @@ -4819,6 +4885,40 @@ // Next state - if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; - else r_xram_rsp_fsm = XRAM_RSP_IDLE; + if (r_xram_rsp_trt_buf.proc_read) + { + r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; + } + else + { + // Trigger an interruption to signal a bus error from + // the XRAM because a processor WRITE MISS (XRAM GET + // transaction and not processor read). + // + // To avoid deadlocks we do not wait an error to be + // acknowledged before signaling another one. + // Therefore, when there is an active error, and other + // errors arrive, these are not considered + + if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read() + && r_xram_rsp_trt_buf.xram_read ) + { + r_xram_rsp_rerror_irq = true; + r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4; + r_xram_rsp_rerror_rsrcid = r_xram_rsp_trt_buf.srcid; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout + << " " + << " Triggering interrupt to signal WRITE MISS bus error" + << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read() + << " / nline = " << r_xram_rsp_trt_buf.nline + << " / rsrcid = " << r_xram_rsp_trt_buf.srcid + << std::endl; +#endif + } + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + } #if DEBUG_MEMC_XRAM_RSP @@ -8425,4 +8525,14 @@ //////////////////////////////////////////////////////////////////// + // p_irq port + // + // WRITE MISS response error signaling + //////////////////////////////////////////////////////////////////// + + p_irq = + r_xram_rsp_rerror_irq.read() && + r_xram_rsp_rerror_irq_enable.read(); + + //////////////////////////////////////////////////////////////////// // p_dspin_m2p port (CC_SEND FSM) ////////////////////////////////////////////////////////////////////