Changeset 604 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source

Timestamp:

Dec 17, 2013, 3:21:07 PM (11 years ago)

Author:

devigne

Message:

Merge with the latest trunk (concurrent access to a register CONFIG_FSM)
Modification processing software invalidations to memcache level.

When a software memcache invalidation, it does not write the dirty data in the
XRAM (and therefore does not reserve space in the TRT). This poses a problem
when processing CLEANUP_DATA on a line NCC because CLEANUP_FSM expects to find
a placeholder in the TRT.

To overcome this problem, the flit DSPIN a multi-inval now contains a bit to
indicate that the invalidation from a control configuration (software
invalidation level memcache).

At the reception of this message invalidation in the L1 cache, it retrieves the
value of the field DSPIN IS_CONFIG. When processing invalidation (
DCACHE_CC_INVAL ), the value of this field is checked. Two scenarios are
possible:

• 1st case : The INVAL concerns a line NCC but not from a software invalidation (IS_CONFIG = 0), the CLEANUP sent then follows the classical treatment of invalidation of a line NCC (sends a CLEANUP_NCC with or without data).

• 2nd case : The INVAL provides a line NCC from a software invalidation (IS_CONFIG = 1) : same treatment as was CLEANUP line CC.

Thus in the case of interest (software invalidation on a line NCC), the CLEANUP
received by the memcache will be treated as one line CC.

Location:

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source

Files:

• include/vci_cc_vcache_wrapper.h (modified) (1 diff)
• src/vci_cc_vcache_wrapper.cpp (modified) (4 diffs)

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -604 +604 @@
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
-    sc_signal<bool>         r_cc_receive_dcache_req;        // cc_receive to dcache request
-    sc_signal<int>          r_cc_receive_dcache_type;       // cc_receive type of request
-    sc_signal<size_t>       r_cc_receive_dcache_way;        // cc_receive to dcache way
-    sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
-    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_dcache_nline;      // cache line physical address
+    sc_signal<bool>         r_cc_receive_dcache_req;              // cc_receive to dcache request
+    sc_signal<int>          r_cc_receive_dcache_type;             // cc_receive type of request
+    sc_signal<size_t>       r_cc_receive_dcache_way;              // cc_receive to dcache way
+    sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
+    sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
+    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
+    sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
 
     ///////////////////////////////////

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -2297 +2297 @@
         {
 
+
             if ( r_mmu_mode.read() & DATA_TLB_MASK )  // DTLB activated
             {
@@ -5366 +5367 @@
 #endif
                 }
-
-                if (cache_state == CACHE_SLOT_STATE_VALID_CC) 
+                // If the line is coherente we send a classic CLEANUP
+                // If the type of inval request from Memcache is configuration
+                // (software), we send a classic CLEANUP
+                if (cache_state == CACHE_SLOT_STATE_VALID_CC or r_cc_receive_dcache_inval_is_config.read()) 
                 {
                     r_dcache.write_dir( way,
@@ -5388 +5391 @@
                 r_dcache_cc_send_type = CC_TYPE_CLEANUP;
                 // MODIFIER POUR DIRTY BIT //
-                if (cache_state == CACHE_SLOT_STATE_VALID_NCC)
+                if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
                 {
                     r_dcache_cc_cleanup_line_ncc = true; 
                     if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
-                    //if (true) //must send data
                     {
                         r_dcache_cc_cleanup_updt_data = true;
@@ -6309 +6311 @@
         case CC_RECEIVE_DATA_INVAL_HEADER:
         {
+            // initialize dspin received data
+            uint64_t receive_data = p_dspin_m2p.data.read();
             // sample updt tab index in the HEADER, then skip to second flit
             r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
+            r_cc_receive_dcache_inval_is_config = DspinDhccpParam::dspin_get(receive_data,
+                                                  DspinDhccpParam::MULTI_INVAL_IS_CONFIG);
             break;
         }