Changeset 605 for trunk/modules/vci_mem_cache/caba

Timestamp:

Dec 18, 2013, 11:33:50 AM (11 years ago)

Author:

cfuguet

Message:

Modification in vci_mem_cache:

• The rerror_irq_enable register is also readeable

Location:

trunk/modules/vci_mem_cache/caba/source

Files:

• include/vci_mem_cache.h (modified) (3 diffs)
• src/vci_mem_cache.cpp (modified) (4 diffs)

trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -83 +83 @@
         TGT_CMD_WRITE,
         TGT_CMD_CAS,
-        TGT_CMD_ERROR,
-        TGT_CMD_CONFIG
+        TGT_CMD_CONFIG,
+        TGT_CMD_ERROR
       };
 
@@ -96 +96 @@
         TGT_RSP_MULTI_ACK_IDLE,
         TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_CONFIG_IDLE,
-        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_READ,
         TGT_RSP_WRITE,
@@ -104 +104 @@
         TGT_RSP_MULTI_ACK,
         TGT_RSP_CLEANUP,
-        TGT_RSP_CONFIG,
-        TGT_RSP_TGT_CMD
+        TGT_RSP_TGT_CMD,
+        TGT_RSP_CONFIG
       };
 

trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -65 +65 @@
         "TGT_CMD_WRITE",
         "TGT_CMD_CAS",
-        "TGT_CMD_ERROR",
-        "TGT_CMD_CONFIG"
+        "TGT_CMD_CONFIG",
+        "TGT_CMD_ERROR"
     };
     const char *tgt_rsp_fsm_str[] =
@@ -76 +76 @@
         "TGT_RSP_MULTI_ACK_IDLE",
         "TGT_RSP_CLEANUP_IDLE",
+        "TGT_RSP_TGT_CMD_IDLE",
         "TGT_RSP_CONFIG_IDLE",
-        "TGT_RSP_TGT_CMD_IDLE",
         "TGT_RSP_READ",
         "TGT_RSP_WRITE",
@@ -84 +84 @@
         "TGT_RSP_MULTI_ACK",
         "TGT_RSP_CLEANUP",
-        "TGT_RSP_CONFIG",
-        "TGT_RSP_TGT_CMD"
+        "TGT_RSP_TGT_CMD",
+        "TGT_RSP_CONFIG"
     };
     const char *cc_receive_fsm_str[] =
@@ -1520 +1520 @@
                                         break;
 
+                                    case MEMC_RERROR_IRQ_ENABLE:
+                                        rdata = (uint32_t)
+                                            (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0;
+
+                                        break;
+
                                     default:
                                         error = 1;