Index: trunk/platforms/almos-tsar-mipsel/Makefile =================================================================== --- trunk/platforms/almos-tsar-mipsel/Makefile (revision 609) +++ trunk/platforms/almos-tsar-mipsel/Makefile (revision 609) @@ -0,0 +1,6 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x -j8 + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x term* Index: trunk/platforms/almos-tsar-mipsel/soclib.conf =================================================================== --- trunk/platforms/almos-tsar-mipsel/soclib.conf (revision 609) +++ trunk/platforms/almos-tsar-mipsel/soclib.conf (revision 609) @@ -0,0 +1,18 @@ + +config.lib_systemcass_openmp_mine = Library( + parent = config.systemc, + dir = "/users/outil/nbsdtsar/systemcass-optim", + libdir = "%(dir)s/lib-linux", + cflags = config.systemc.cflags+['-fopenmp']+['-O3']+['-DUSE_OPENMP=1'], + libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic', '-fopenmp'], +) + +config.systemcass_openmp_mine = BuildEnv( + parent = config.systemc_64, + libraries = [ config.lib_systemcass_openmp_mine ], + repos = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-optim", + cache_file = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-optim/soclib_cc.cache", + toolchain = config.toolchain_64, +) + +config.default = config.systemcass_openmp_mine Index: trunk/platforms/almos-tsar-mipsel/top.cpp =================================================================== --- trunk/platforms/almos-tsar-mipsel/top.cpp (revision 609) +++ trunk/platforms/almos-tsar-mipsel/top.cpp (revision 609) @@ -0,0 +1,946 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : may 2013 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture. +// The physical address space is 40 bits. +// +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 8. +// +// - It uses four dspin_local_crossbar per cluster as local interconnect +// - It uses two virtual_dspin routers per cluster as global interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains one vci_xicu per cluster. +// - It contains one vci_multi_dma per cluster. +// - It contains one vci_simple_ram per cluster to model the L3 cache. +// +// The communication between the MemCache and the Xram is 64 bits. +// +// All clusters are identical, but the cluster 0 (called io_cluster), +// contains 6 extra components: +// - the boot rom (BROM) +// - the disk controller (BDEV) +// - the multi-channel network controller (MNIC) +// - the multi-channel chained buffer dma controller (CDMA) +// - the multi-channel tty controller (MTTY) +// - the frame buffer controller (FBUF) +// +// It is build with one single component implementing a cluster, +// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) +// +// The IRQs are connected to XICUs as follow: +// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. +// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. +// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. +// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. +// +// Some hardware parameters are used when compiling the OS, and are used +// by this top.cpp file. They must be defined in the hard_config.h file : +// - CLUSTER_X : number of clusters in a row (power of 2) +// - CLUSTER_Y : number of clusters in a column (power of 2) +// - CLUSTER_SIZE : size of the segment allocated to a cluster +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) +// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) +// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) +// +// Some other hardware parameters are not used when compiling the OS, +// and can be directly defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_SECTOR_SIZE : block size for block drvice +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container +///////////////////////////////////////////////////////////////////////// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 24 | +///////////////////////////////////////////////////////////////////////// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// | X_ID | Y_ID |---| L_ID | +// |x_width|y_width|---| 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "tsar_xbar_cluster.h" +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#if USE_OPENMP +#include +#endif + +// cluster index (computed from x,y coordinates) +#define cluster(x,y) (y + ymax * x) + +#define min(x, y) (x < y ? x : y) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 +#define vci_address_width 32 +#define vci_plen_width 8 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////////////////////////////////////////// +#define CLUSTER_X 1 +#define CLUSTER_Y 1 +#define NB_CLUSTERS 1 +#define NB_PROCS_MAX 4 +#define NB_DMA_CHANNELS 1 +#define NB_TTY_CHANNELS 4 +#define NB_IOC_CHANNELS 1 +#define NB_NIC_CHANNELS 1 +#define NB_CMA_CHANNELS 0 +#define USE_XICU 1 +#define IOMMU_ACTIVE 0 + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters +//////////////////////////////////////////////////////////// +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define FBUF_X_SIZE 512 +#define FBUF_Y_SIZE 512 + +#define BDEV_SECTOR_SIZE 4096 +#define BDEV_IMAGE_NAME "hdd-img.bin" + +#define NIC_RX_NAME "rx_packets.txt" +#define NIC_TX_NAME "tx_packets.txt" +#define NIC_TIMEOUT 10000 + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM/RAM +//////////////////////////////////////////////////////////// +#define soft_name "bootloader.bin",\ + "kernel-soclib.bin@0xbfc10000:D",\ + "arch-info.bin@0xBFC08000:D" + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////////////////////////////////////////// +#define MAX_FROZEN_CYCLES 100000000 + +//////////////////////////////////////////////////////////////////// +// TGTID definition in direct space +// For all components: global TGTID = global SRCID = cluster_index +//////////////////////////////////////////////////////////////////// +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define MDMA_TGTID 2 +#define MTTY_TGTID 3 +#define FBUF_TGTID 4 +#define BDEV_TGTID 5 +#define MNIC_TGTID 6 +#define BROM_TGTID 7 +#define CDMA_TGTID 8 +#define SIMH_TGTID 9 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// +// There is 3 segments replicated in all clusters +// and 5 specific segments in the "IO" cluster +// (containing address 0xBF000000) +///////////////////////////////////////////////////////// +// Physical Address Decoding: 8 GID + 8 LID + 16 offset. +///////////////////////////////////////////////////////// +#define RAM_BASE 0x00000000 +#define RAM_SIZE 0x00C00000 + +#define BROM_BASE 0xBFC00000 +#define BROM_SIZE 0x00100000 + +#define FBUF_BASE 0xBFD00000 +#define FBUF_SIZE 0x00200000 + +#define XICU_BASE 0x00F00000 +#define XICU_SIZE 0x00002000 + +#define BDEV_BASE 0xBFF10000 +#define BDEV_SIZE 0x00000100 + +#define MTTY_BASE 0xBFF20000 +#define MTTY_SIZE 0x00000100 + +#define MDMA_BASE 0x00F30000 +#define MDMA_SIZE 0x00001000 * NB_DMA_CHANNELS // 4 Kbytes per channel + +#define MEMC_BASE 0x00F40000 +#define MEMC_SIZE 0x00001000 + +#define SIMH_BASE 0xBFF50000 +#define SIMH_SIZE 0x00001000 + +#define CDMA_BASE 0xBFF60000 +#define CDMA_SIZE 0x00000100 + +#define MNIC_BASE 0xB0F80000 +#define MNIC_SIZE 0x00080000 // 512 Kbytes (for 8 channels) + +bool stop_called = false; + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + uint64_t ncycles = 0xFFFFFFFFFFFFFFFF; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0; // index of memc to be traced + size_t debug_proc_id = 0; // index of proc to be traced + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t xmax = CLUSTER_X; // number of clusters in a row + size_t ymax = CLUSTER_Y; // number of clusters in a column + size_t nprocs = NB_PROCS_MAX; // number of processors per cluster + size_t xfb = FBUF_X_SIZE; // frameBuffer column number + size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number + size_t fb_mode = 420; + size_t memc_size = RAM_SIZE; + size_t blk_size = BDEV_SECTOR_SIZE; + size_t l1_i_ways = L1_IWAYS; + size_t l1_d_ways = L1_DWAYS; + size_t l1_i_sets = L1_ISETS; + size_t l1_d_sets = L1_DSETS; + size_t memc_sets = MEMC_SETS; + size_t memc_ways = MEMC_WAYS; + size_t xram_latency = XRAM_LATENCY; + size_t cluster_io_id; // index of cluster containing IOs + struct timeval t1,t2; + uint64_t ms1,ms2; + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) + { + ncycles = atoi(argv[n + 1]); + } + else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1 vci_param_int; + + typedef soclib::caba::VciParams vci_param_ext; + +#if USE_OPENMP + omp_set_dynamic(false); + omp_set_num_threads(threads_nr); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + + // Define parameters depending on mesh size + size_t x_width; + size_t y_width; + + if (xmax == 1) x_width = 0; + else if (xmax == 2) x_width = 1; + else if (xmax <= 4) x_width = 2; + else if (xmax <= 8) x_width = 3; + else x_width = 4; + + if (ymax == 1) y_width = 0; + else if (ymax == 2) y_width = 1; + else if (ymax <= 4) y_width = 2; + else if (ymax <= 8) y_width = 3; + else y_width = 4; + + cluster_io_id = 0xbfc00000 >> (vci_address_width - x_width - y_width); // index of cluster containing IOs + + ///////////////////// + // Mapping Tables + ///////////////////// + + // internal network + MappingTable maptabd(vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FFFF0000); + + for (size_t x = 0; x < xmax; x++) + { + for (size_t y = 0; y < ymax; y++) + { + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream si; + si << "seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE, + IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE, + IntTab(cluster(x,y),MDMA_TGTID), false)); + + std::ostringstream sh; + sh << "seg_ram_" << x << "_" << y; + maptabd.add(Segment(sh.str(), RAM_BASE + offset, memc_size, + IntTab(cluster(x,y),MEMC_TGTID), true)); + + std::ostringstream sconf; + sconf << "seg_memc_config_" << x << "_" << y; + maptabd.add(Segment(sconf.str(), MEMC_BASE + offset, MEMC_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), true, true)); + + if ( cluster(x,y) == cluster_io_id ) + { + maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, + IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, + IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, + IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, + IntTab(cluster(x,y),BROM_TGTID), true)); + maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, + IntTab(cluster(x,y),MNIC_TGTID), false)); + maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE, + IntTab(cluster(x,y),CDMA_TGTID), false)); + maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE, + IntTab(cluster(x,y),SIMH_TGTID), false)); + } + } + } + std::cout << maptabd << std::endl; + + // external network + MappingTable maptabx(vci_address_width, + IntTab(x_width+y_width), + IntTab(x_width+y_width), + 0x00FFFF0000ULL); + + for (size_t x = 0; x < xmax; x++) + { + for (size_t y = 0; y < ymax ; y++) + { + + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + + maptabx.add(Segment(sh.str(), RAM_BASE + offset, + memc_size, IntTab(cluster(x,y)), false)); + } + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + std::cout << "Clock .. "; + sc_clock signal_clk("clk"); + std::cout << ". [OK]" << std::endl; + sc_signal signal_resetn("resetn"); + + // Horizontal inter-clusters DSPIN signals + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", xmax-1, ymax, 3); + + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", xmax-1, ymax, 3); + + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); + + // Vertical inter-clusters DSPIN signals + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", xmax, ymax-1, 3); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", xmax, ymax-1, 3); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); + + // Mesh boundaries DSPIN signals + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in" , xmax, ymax, 4, 3); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", xmax, ymax, 4, 3); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in" , xmax, ymax, 4, 2); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", xmax, ymax, 4, 2); + + //////////////////////////// + // Loader + //////////////////////////// + + soclib::common::Loader loader(soft_name); + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////// + // Clusters construction + //////////////////////////// + + TsarXbarCluster* clusters[xmax][ymax]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for (size_t i = 0; i < (xmax * ymax); i++) + { + size_t x = i / ymax; + size_t y = i % ymax; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << x << "_" << y << std::endl; + std::cout << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarXbarCluster + ( + sc.str().c_str(), + nprocs, + NB_TTY_CHANNELS, + NB_DMA_CHANNELS, + x, + y, + cluster(x,y), + maptabd, + maptabx, + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + CDMA_TGTID, + BDEV_TGTID, + SIMH_TGTID, + memc_ways, + memc_sets, + l1_i_ways, + l1_i_sets, + l1_d_ways, + l1_d_sets, + xram_latency, + (cluster(x,y) == cluster_io_id), + xfb, + yfb, + disk_name, + blk_size, + NB_NIC_CHANNELS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + NB_CMA_CHANNELS, + loader, + frozen_cycles, + debug_from , + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id) + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // Clock & RESET + for (size_t x = 0; x < (xmax); x++){ + for (size_t y = 0; y < ymax; y++){ + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (xmax > 1){ + for (size_t x = 0; x < (xmax-1); x++){ + for (size_t y = 0; y < ymax; y++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); + clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); + } + } + } + } + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (ymax > 1) { + for (size_t y = 0; y < (ymax-1); y++){ + for (size_t x = 0; x < xmax; x++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < ymax; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); + clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); + clusters[xmax-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[xmax-1][y][EAST][k]); + clusters[xmax-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[xmax-1][y][EAST][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); + clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); + clusters[xmax-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[xmax-1][y][EAST][k]); + clusters[xmax-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[xmax-1][y][EAST][k]); + } + } + + // North & South boundary clusters connections + for (size_t x = 0; x < xmax; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); + clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); + clusters[x][ymax-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][ymax-1][NORTH][k]); + clusters[x][ymax-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][ymax-1][NORTH][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); + clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); + clusters[x][ymax-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][ymax-1][NORTH][k]); + clusters[x][ymax-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][ymax-1][NORTH][k]); + } + } + std::cout << "North, South, West, East connections established" << std::endl; + std::cout << std::endl; + + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for (size_t x = 0; x < xmax ; x++){ + for (size_t y = 0; y < ymax ; y++){ + for (size_t a = 0; a < 4; a++){ + for (size_t k = 0; k < 3; k++){ + signal_dspin_false_cmd_in [x][y][a][k].write = false; + signal_dspin_false_cmd_in [x][y][a][k].read = true; + signal_dspin_false_cmd_out[x][y][a][k].write = false; + signal_dspin_false_cmd_out[x][y][a][k].read = true; + } + + for (size_t k = 0; k < 2; k++){ + signal_dspin_false_rsp_in [x][y][a][k].write = false; + signal_dspin_false_rsp_in [x][y][a][k].read = true; + signal_dspin_false_rsp_out[x][y][a][k].write = false; + signal_dspin_false_rsp_out[x][y][a][k].read = true; + } + } + } + } + +#define STATS_CYCLES 10000000 + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + uint64_t n = 0; + + while (!stop_called) { + if (gettimeofday(&t1, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + sc_start(STATS_CYCLES); + n += STATS_CYCLES; + if (gettimeofday(&t2, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + ms1 = (uint64_t)t1.tv_sec * 1000ULL + (uint64_t)t1.tv_usec / 1000; + ms2 = (uint64_t)t2.tv_sec * 1000ULL + (uint64_t)t2.tv_usec / 1000; + std::cerr << "cycle " << n + << " platform clock frequency " + << (double)STATS_CYCLES / (double)(ms2 - ms1) + << "Khz" << std::endl; + } + + // Free memory + for (size_t i = 0; i < (xmax * ymax); i++) + { + size_t x = i / ymax; + size_t y = i % ymax; + delete clusters[x][y]; + } + + dealloc_elems >(signal_dspin_h_cmd_inc, xmax - 1, ymax, 3); + dealloc_elems >(signal_dspin_h_cmd_dec, xmax - 1, ymax, 3); + dealloc_elems >(signal_dspin_h_rsp_inc, xmax - 1, ymax, 2); + dealloc_elems >(signal_dspin_h_rsp_dec, xmax - 1, ymax, 2); + dealloc_elems >(signal_dspin_v_cmd_inc, xmax, ymax - 1, 3); + dealloc_elems >(signal_dspin_v_cmd_dec, xmax, ymax - 1, 3); + dealloc_elems >(signal_dspin_v_rsp_inc, xmax, ymax - 1, 2); + dealloc_elems >(signal_dspin_v_rsp_dec, xmax, ymax - 1, 2); + dealloc_elems >(signal_dspin_false_cmd_in, xmax, ymax, 4, 3); + dealloc_elems >(signal_dspin_false_cmd_out, xmax, ymax, 4, 3); + dealloc_elems >(signal_dspin_false_rsp_in, xmax, ymax, 4, 2); + dealloc_elems >(signal_dspin_false_rsp_out, xmax, ymax, 4, 2); + + return EXIT_SUCCESS; +} + + +void handler(int dummy = 0) { + stop_called = true; + sc_stop(); +} + +void voidhandler(int dummy = 0) {} + +int sc_main (int argc, char *argv[]) +{ + signal(SIGINT, handler); + signal(SIGPIPE, voidhandler); + + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 Index: trunk/platforms/almos-tsar-mipsel/top.desc =================================================================== --- trunk/platforms/almos-tsar-mipsel/top.desc (revision 609) +++ trunk/platforms/almos-tsar-mipsel/top.desc (revision 609) @@ -0,0 +1,46 @@ + +# -*- python -*- + +# internal VCI parameters values +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 32 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 + +todo = Platform('caba', 'top.cpp', + + uses = [ + Uses('caba:tsar_xbar_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, +) Index: trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 609) +++ trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 609) @@ -0,0 +1,107 @@ + +# -*- python -*- + +Module('caba:tsar_xbar_cluster', + classname = 'soclib::caba::TsarXbarCluster', + tmpl_parameters = [ + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + ], + + header_files = [ '../source/include/tsar_xbar_cluster.h', + ], + + implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_cmd_width'), + dspin_out_width = parameter.Reference('dspin_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + dspin_in_width = parameter.Reference('dspin_rsp_width'), + dspin_out_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:vci_simple_rom', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:vci_multi_tty', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_framebuffer', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_nic', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_chbuf_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_block_device_tsar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simhelper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('common:elf_file_loader'), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_cmd_out', [4, 3], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', [4, 3], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_output', 'p_rsp_out', [4, 2], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [4, 2], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + ], +) + + Index: trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h =================================================================== --- trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 609) +++ trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 609) @@ -0,0 +1,292 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_XBAR_CLUSTER_H +#define SOCLIB_CABA_TSAR_XBAR_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_simple_rom.h" +#include "vci_xicu.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "virtual_dspin_router.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_chbuf_dma.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_multi_dma.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_simhelper.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template class TsarXbarCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + public: + + // Used in destructor + size_t n_procs; + + // Ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::DspinOutput **p_cmd_out; + soclib::caba::DspinInput **p_cmd_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_irq_memc; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mtty[23]; + sc_signal signal_irq_mnic_rx[8]; // unused + sc_signal signal_irq_mnic_tx[8]; // unused + sc_signal signal_irq_chbuf[8]; // unused + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and local_crossbars + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_clack_l2g_c; + DspinSignals signal_dspin_clack_g2l_c; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + + // Direct VCI signals to VCI/DSPIN wrappers + VciSignals signal_vci_ini_proc[8]; + VciSignals signal_vci_ini_mdma; + VciSignals signal_vci_ini_bdev; + VciSignals signal_vci_ini_chbuf; + + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mdma; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_brom; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_tgt_mnic; + VciSignals signal_vci_tgt_chbuf; + VciSignals signal_vci_tgt_simh; + + // Direct DSPIN signals to local crossbars + DspinSignals signal_dspin_cmd_proc_i[8]; + DspinSignals signal_dspin_rsp_proc_i[8]; + DspinSignals signal_dspin_cmd_mdma_i; + DspinSignals signal_dspin_rsp_mdma_i; + DspinSignals signal_dspin_cmd_bdev_i; + DspinSignals signal_dspin_rsp_bdev_i; + DspinSignals signal_dspin_cmd_chbuf_i; + DspinSignals signal_dspin_rsp_chbuf_i; + + DspinSignals signal_dspin_cmd_memc_t; + DspinSignals signal_dspin_rsp_memc_t; + DspinSignals signal_dspin_cmd_xicu_t; + DspinSignals signal_dspin_rsp_xicu_t; + DspinSignals signal_dspin_cmd_mdma_t; + DspinSignals signal_dspin_rsp_mdma_t; + DspinSignals signal_dspin_cmd_mtty_t; + DspinSignals signal_dspin_rsp_mtty_t; + DspinSignals signal_dspin_cmd_bdev_t; + DspinSignals signal_dspin_rsp_bdev_t; + DspinSignals signal_dspin_cmd_brom_t; + DspinSignals signal_dspin_rsp_brom_t; + DspinSignals signal_dspin_cmd_fbuf_t; + DspinSignals signal_dspin_rsp_fbuf_t; + DspinSignals signal_dspin_cmd_mnic_t; + DspinSignals signal_dspin_rsp_mnic_t; + DspinSignals signal_dspin_cmd_chbuf_t; + DspinSignals signal_dspin_rsp_chbuf_t; + DspinSignals signal_dspin_cmd_simh_t; + DspinSignals signal_dspin_rsp_simh_t; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_clack_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[8]; + DspinSignals signal_dspin_clack_proc[8]; + DspinSignals signal_dspin_p2m_proc[8]; + + // external RAM to MEMC VCI signal + VciSignals signal_vci_xram; + + // Components + + VciCcVCacheWrapper >* proc[8]; + + VciDspinInitiatorWrapper* wi_proc[8]; + + VciMemCache* memc; + + VciDspinTargetWrapper* wt_memc; + + VciXicu* xicu; + + VciDspinTargetWrapper* wt_xicu; + + VciMultiDma* mdma; + + VciDspinInitiatorWrapper* wi_mdma; + + VciDspinTargetWrapper* wt_mdma; + + VciSimpleRam* xram; + + VciSimpleRom* brom; + + VciDspinTargetWrapper* wt_brom; + + VciMultiTty* mtty; + + VciDspinTargetWrapper* wt_mtty; + + VciSimhelper* simhelper; + + VciDspinTargetWrapper* wt_simhelper; + + + VciFrameBuffer* fbuf; + + VciDspinTargetWrapper* wt_fbuf; + + VciMultiNic* mnic; + + VciDspinTargetWrapper* wt_mnic; + + VciChbufDma* chbuf; + + VciDspinTargetWrapper* wt_chbuf; + + VciDspinInitiatorWrapper* wi_chbuf; + + VciBlockDeviceTsar* bdev; + + VciDspinInitiatorWrapper* wi_bdev; + + VciDspinTargetWrapper* wt_bdev; + + DspinLocalCrossbar* xbar_cmd_d; + DspinLocalCrossbar* xbar_rsp_d; + DspinLocalCrossbar* xbar_m2p_c; + DspinLocalCrossbar* xbar_p2m_c; + DspinLocalCrossbar* xbar_clack_c; + + VirtualDspinRouter* router_cmd; + VirtualDspinRouter* router_rsp; + + TsarXbarCluster( sc_module_name insname, + size_t nb_procs, // processors + size_t nb_ttys, // TTY terminals + size_t nb_dmas, // DMA channels + size_t x, // x coordinate + size_t y, // y coordinate + size_t cluster, // y + ymax*x + const soclib::common::MappingTable &mtd, // internal + const soclib::common::MappingTable &mtx, // external + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_chbuf, + size_t tgtid_bdev, + size_t tgtid_simh, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, // external ram + bool io, // I/O cluster + size_t xfb, // fbf pixels + size_t yfb, // fbf lines + char* disk_name, // virtual disk + size_t block_size, // block size + size_t nic_channels, // number channels + char* nic_rx_name, // filename rx + char* nic_tx_name, // filename tx + uint32_t nic_timeout, // cycles + size_t chbufdma_channels, // number channels + const Loader &loader, + uint32_t frozen_cycles, + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok); + + ~TsarXbarCluster(); + +}; +}} + +#endif Index: trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp =================================================================== --- trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 609) +++ trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 609) @@ -0,0 +1,903 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2011 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// This file define a TSAR cluster architecture with virtual memory: +// - It uses two virtual_dspin_router as distributed global interconnect +// - It uses four dspin_local_crossbar as local interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains a private RAM with a variable latency to emulate the L3 cache +// - It can contains 1, 2 or 4 processors +// - Each processor has a private dma channel (vci_multi_dma) +// - It uses the vci_xicu interrupt controller +// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) +// - The Multi-TTY component controls up to 15 terminals. +// - Each Multi-DMA component controls up to 8 DMA channels. +// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] +// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] +// - The BDEV IRQ is connected to IRQ_IN[31] +////////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_xbar_cluster.h" + + +namespace soclib { +namespace caba { + +//////////////////////////////////////////////////////////////////////////////////// +template TsarXbarCluster::TsarXbarCluster( +//////////////////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + size_t nb_ttys, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t cluster_id, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtx, + size_t x_width, + size_t y_width, + size_t l_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_chbuf, + size_t tgtid_bdev, + size_t tgtid_simh, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + bool io, + size_t xfb, + size_t yfb, + char* disk_name, + size_t block_size, + size_t nic_channels, + char* nic_rx_name, + char* nic_tx_name, + uint32_t nic_timeout, + size_t chbufdma_channels, + const Loader &loader, + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") + +{ + + n_procs = nb_procs; + + // Vectors of ports definition + p_cmd_in = alloc_elems > ("p_cmd_in", 4, 3); + p_cmd_out = alloc_elems > ("p_cmd_out", 4, 3); + p_rsp_in = alloc_elems > ("p_rsp_in", 4, 2); + p_rsp_out = alloc_elems > ("p_rsp_out", 4, 2); + + ///////////////////////////////////////////////////////////////////////////// + // Components definition + ///////////////////////////////////////////////////////////////////////////// + + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream sproc; + sproc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper >( + sproc.str().c_str(), + cluster_id * nb_procs + p, // GLOBAL PROC_ID + mtd, // Mapping Table + IntTab(cluster_id,p), // SRCID + (cluster_id << l_width) + p, // CC_GLOBAL_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets, 16, // ICACHE size + l1_d_ways,l1_d_sets, 16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + + std::ostringstream swip; + swip << "wi_proc_" << x_id << "_" << y_id << "_" << p; + wi_proc[p] = new VciDspinInitiatorWrapper( + swip.str().c_str(), + x_width + y_width + l_width); + } + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + smemc.str().c_str(), + mtd, // Mapping Table direct space + mtx, // Mapping Table external space + IntTab(cluster_id), // SRCID external space + IntTab(cluster_id, tgtid_memc), // TGTID direct space + //(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID + x_width, // Number of x bits in platform + y_width, // Number of y bits in platform + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + 8, // INVALIDATE TABLE DEPTH + debug_start_cycle, + memc_debug_ok); + + wt_memc = new VciDspinTargetWrapper( + "wt_memc", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + sxram.str().c_str(), + IntTab(cluster_id), + mtx, + loader, + xram_latency); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxicu; + sxicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + sxicu.str().c_str(), + mtd, // mapping table + IntTab(cluster_id, tgtid_xicu), // TGTID_D + nb_procs, // number of timer IRQs + 32, // number of hard IRQs + 32, // number of soft IRQs + nb_procs); // number of output IRQs + + wt_xicu = new VciDspinTargetWrapper( + "wt_xicu", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream smdma; + smdma << "mdma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + smdma.str().c_str(), + mtd, + IntTab(cluster_id, nb_procs), // SRCID + IntTab(cluster_id, tgtid_mdma), // TGTID + 64, // burst size + nb_dmas); // number of IRQs + + wt_mdma = new VciDspinTargetWrapper( + "wt_mdma", + x_width + y_width + l_width); + + wi_mdma = new VciDspinInitiatorWrapper( + "wi_mdma", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + size_t nb_direct_initiators = nb_procs + 1; + size_t nb_direct_targets = 3; + if (io) + { + nb_direct_initiators = nb_procs + 3; + nb_direct_targets = 10; + } + + xbar_cmd_d = new DspinLocalCrossbar( + "xbar_cmd_d", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_initiators, // number of local of sources + nb_direct_targets, // number of local dests + 2, 2, // fifo depths + true, // CMD + true, // use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_rsp_d = new DspinLocalCrossbar( + "xbar_rsp_d", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_targets, // number of local sources + nb_direct_initiators, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_m2p_c = new DspinLocalCrossbar( + "xbar_m2p_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 2, 2, // fifo depths + true, // CMD + false, // don't use local routing table + true ); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_p2m_c = new DspinLocalCrossbar( + "xbar_p2m_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // l_width unused on p2m network + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_clack_c = new DspinLocalCrossbar( + "xbar_clack_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 1, 1, // fifo depths + true, // CMD + false, // don't use local routing table + false); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + router_cmd = new VirtualDspinRouter( + "router_cmd", + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 3, // nb virtual channels + 4,4); // input & output fifo depths + + ///////////////////////////////////////////////////////////////////////////// + router_rsp = new VirtualDspinRouter( + "router_rsp", + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 2, // nb virtual channels + 4,4); // input & output fifo depths + + // IO cluster components + if (io) + { + ///////////////////////////////////////////// + brom = new VciSimpleRom( + "brom", + IntTab(cluster_id, tgtid_brom), + mtd, + loader); + + wt_brom = new VciDspinTargetWrapper( + "wt_brom", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + fbuf = new VciFrameBuffer( + "fbuf", + IntTab(cluster_id, tgtid_fbuf), + mtd, + xfb, yfb); + + wt_fbuf = new VciDspinTargetWrapper( + "wt_fbuf", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + bdev = new VciBlockDeviceTsar( + "bdev", + mtd, + IntTab(cluster_id, nb_procs + 1), + IntTab(cluster_id, tgtid_bdev), + disk_name, + block_size, + 64); // burst size + + wt_bdev = new VciDspinTargetWrapper( + "wt_bdev", + x_width + y_width + l_width); + + wi_bdev = new VciDspinInitiatorWrapper( + "wi_bdev", + x_width + y_width + l_width); + + int mac = 0xBEEF0000; + mnic = new VciMultiNic( + "mnic", + IntTab(cluster_id, tgtid_mnic), + mtd, + nic_channels, + nic_rx_name, + nic_tx_name, + mac, // mac_4 address + 0xBABE ); // mac_2 address + + wt_mnic = new VciDspinTargetWrapper( + "wt_mnic", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + chbuf = new VciChbufDma( + "chbuf_dma", + mtd, + IntTab(cluster_id, nb_procs + 2), + IntTab(cluster_id, tgtid_chbuf), + 64, + chbufdma_channels); + + wt_chbuf = new VciDspinTargetWrapper( + "wt_chbuf", + x_width + y_width + l_width); + + wi_chbuf = new VciDspinInitiatorWrapper( + "wi_chbuf", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + std::vector vect_names; + for (size_t tid = 0; tid < nb_ttys; tid++) + { + std::ostringstream term_name; + term_name << "tty" << tid; + vect_names.push_back(term_name.str().c_str()); + } + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_id, tgtid_mtty), + mtd, + vect_names); + + wt_mtty = new VciDspinTargetWrapper( + "wt_mtty", + x_width + y_width + l_width); + + simhelper = new VciSimhelper( + "sim_helper", + IntTab(cluster_id, tgtid_simh), + mtd); + + wt_simhelper = new VciDspinTargetWrapper( + "wt_simhelper", + x_width + y_width + l_width); + } + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + //////////////////////// CMD ROUTER and RSP ROUTER + router_cmd->p_clk (this->p_clk); + router_cmd->p_resetn (this->p_resetn); + router_rsp->p_clk (this->p_clk); + router_rsp->p_resetn (this->p_resetn); + + for (int i = 0; i < 4; i++) + { + for (int k = 0; k < 3; k++) + { + router_cmd->p_out[i][k] (this->p_cmd_out[i][k]); + router_cmd->p_in[i][k] (this->p_cmd_in[i][k]); + } + + for (int k = 0; k < 2; k++) + { + router_rsp->p_out[i][k] (this->p_rsp_out[i][k]); + router_rsp->p_in[i][k] (this->p_rsp_in[i][k]); + } + } + + router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d); + router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c); + router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c); + router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d); + router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c); + router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c); + + router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d); + router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c); + router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d); + router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c); + + + std::cout << " - CMD & RSP routers connected" << std::endl; + + ///////////////////// CMD DSPIN local crossbar direct + xbar_cmd_d->p_clk (this->p_clk); + xbar_cmd_d->p_resetn (this->p_resetn); + xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d); + xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d); + + xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t); + xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t); + xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t); + + xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]); + + if (io) + { + xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t); + xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t); + xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t); + xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t); + xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t); + xbar_cmd_d->p_local_out[tgtid_chbuf] (signal_dspin_cmd_chbuf_t); + xbar_cmd_d->p_local_out[tgtid_simh] (signal_dspin_cmd_simh_t); + + xbar_cmd_d->p_local_in[nb_procs + 1] (signal_dspin_cmd_bdev_i); + xbar_cmd_d->p_local_in[nb_procs + 2] (signal_dspin_cmd_chbuf_i); + } + + std::cout << " - Command Direct crossbar connected" << std::endl; + + //////////////////////// RSP DSPIN local crossbar direct + xbar_rsp_d->p_clk (this->p_clk); + xbar_rsp_d->p_resetn (this->p_resetn); + xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d); + xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d); + + xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t); + xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t); + xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t); + + xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]); + + if (io) + { + xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t); + xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t); + xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t); + xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t); + xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t); + xbar_rsp_d->p_local_in[tgtid_chbuf] (signal_dspin_rsp_chbuf_t); + xbar_rsp_d->p_local_in[tgtid_simh] (signal_dspin_rsp_simh_t); + + xbar_rsp_d->p_local_out[nb_procs + 1] (signal_dspin_rsp_bdev_i); + xbar_rsp_d->p_local_out[nb_procs + 2] (signal_dspin_rsp_chbuf_i); + } + + std::cout << " - Response Direct crossbar connected" << std::endl; + + ////////////////////// M2P DSPIN local crossbar coherence + xbar_m2p_c->p_clk (this->p_clk); + xbar_m2p_c->p_resetn (this->p_resetn); + xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c); + xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c); + xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]); + + std::cout << " - M2P Coherence crossbar connected" << std::endl; + + ////////////////////// CLACK DSPIN local crossbar coherence + xbar_clack_c->p_clk (this->p_clk); + xbar_clack_c->p_resetn (this->p_resetn); + xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c); + xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c); + xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]); + + std::cout << " - Clack Coherence crossbar connected" << std::endl; + + ////////////////////////// P2M DSPIN local crossbar coherence + xbar_p2m_c->p_clk (this->p_clk); + xbar_p2m_c->p_resetn (this->p_resetn); + xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c); + xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c); + xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]); + + std::cout << " - P2M Coherence crossbar connected" << std::endl; + + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_vci_ini_proc[p]); + proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]); + proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]); + proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); + proc[p]->p_irq[0] (signal_proc_it[p]); + for ( size_t j = 1 ; j < 6 ; j++) + { + proc[p]->p_irq[j] (signal_false); + } + + wi_proc[p]->p_clk (this->p_clk); + wi_proc[p]->p_resetn (this->p_resetn); + wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]); + wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]); + wi_proc[p]->p_vci (signal_vci_ini_proc[p]); + } + + std::cout << " - Processors connected" << std::endl; + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_vci_tgt_xicu); + for (size_t p = 0; p < nb_procs; p++) + { + xicu->p_irq[p] (signal_proc_it[p]); + } + +#if 1 + if(io) + { + xicu->p_hwi[0] (signal_irq_bdev); + xicu->p_hwi[1] (signal_irq_mdma[0]); + + for(size_t i=0; i<4; i++) + xicu->p_hwi[2+i] (signal_irq_mtty[i]); + + xicu->p_hwi[6] (signal_irq_memc); + } + else + { + xicu->p_hwi[1] (signal_irq_mdma[0]); + xicu->p_hwi[2] (signal_irq_memc); + } + + for(size_t i=0; i < 32; i++) + { + if((io && (i > 6)) || (!io && ((i == 0) || (i > 2)))) + xicu->p_hwi[i] (signal_false); + } +#else + for (size_t i = 0; i < 32; i++) + { + if (io) // I/O cluster + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); + else if (i < 16) xicu->p_hwi[i] (signal_false); + else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]); + else if (i < 31) xicu->p_hwi[i] (signal_false); + else xicu->p_hwi[i] (signal_irq_bdev); + } + else // other clusters + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); + else xicu->p_hwi[i] (signal_false); + } + } +#endif + + // wrapper XICU + wt_xicu->p_clk (this->p_clk); + wt_xicu->p_resetn (this->p_resetn); + wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t); + wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t); + wt_xicu->p_vci (signal_vci_tgt_xicu); + + std::cout << " - XICU connected" << std::endl; + + //////////////////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_vci_xram); + memc->p_vci_tgt (signal_vci_tgt_memc); + memc->p_dspin_p2m (signal_dspin_p2m_memc); + memc->p_dspin_m2p (signal_dspin_m2p_memc); + memc->p_dspin_clack (signal_dspin_clack_memc); + memc->p_irq (signal_irq_memc); + + // wrapper MEMC + wt_memc->p_clk (this->p_clk); + wt_memc->p_resetn (this->p_resetn); + wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t); + wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t); + wt_memc->p_vci (signal_vci_tgt_memc); + + std::cout << " - MEMC connected" << std::endl; + + /////////////////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_vci_xram); + + std::cout << " - XRAM connected" << std::endl; + + ////////////////////////////////////////////// MDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_vci_tgt_mdma); + mdma->p_vci_initiator (signal_vci_ini_mdma); + for (size_t i = 0; i < nb_dmas; i++) + mdma->p_irq[i] (signal_irq_mdma[i]); + + // wrapper tgt MDMA + wt_mdma->p_clk (this->p_clk); + wt_mdma->p_resetn (this->p_resetn); + wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t); + wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t); + wt_mdma->p_vci (signal_vci_tgt_mdma); + + // wrapper ini MDMA + wi_mdma->p_clk (this->p_clk); + wi_mdma->p_resetn (this->p_resetn); + wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i); + wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i); + wi_mdma->p_vci (signal_vci_ini_mdma); + + std::cout << " - MDMA connected" << std::endl; + + /////////////////////////////// Components in I/O cluster + + if (io) + { + // BDEV + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + + // wrapper tgt BDEV + wt_bdev->p_clk (this->p_clk); + wt_bdev->p_resetn (this->p_resetn); + wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t); + wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t); + wt_bdev->p_vci (signal_vci_tgt_bdev); + + // wrapper ini BDEV + wi_bdev->p_clk (this->p_clk); + wi_bdev->p_resetn (this->p_resetn); + wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i); + wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i); + wi_bdev->p_vci (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF + fbuf->p_clk (this->p_clk); + fbuf->p_resetn (this->p_resetn); + fbuf->p_vci (signal_vci_tgt_fbuf); + + // wrapper tgt FBUF + wt_fbuf->p_clk (this->p_clk); + wt_fbuf->p_resetn (this->p_resetn); + wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t); + wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t); + wt_fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // MNIC + mnic->p_clk (this->p_clk); + mnic->p_resetn (this->p_resetn); + mnic->p_vci (signal_vci_tgt_mnic); + for (size_t i = 0; i < nic_channels; i++) + { + mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + // wrapper tgt MNIC + wt_mnic->p_clk (this->p_clk); + wt_mnic->p_resetn (this->p_resetn); + wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t); + wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t); + wt_mnic->p_vci (signal_vci_tgt_mnic); + + std::cout << " - MNIC connected" << std::endl; + + // CHBUF + chbuf->p_clk (this->p_clk); + chbuf->p_resetn (this->p_resetn); + chbuf->p_vci_target (signal_vci_tgt_chbuf); + chbuf->p_vci_initiator (signal_vci_ini_chbuf); + for (size_t i = 0; i < chbufdma_channels; i++) + { + chbuf->p_irq[i] (signal_irq_chbuf[i]); + } + + // wrapper tgt CHBUF + wt_chbuf->p_clk (this->p_clk); + wt_chbuf->p_resetn (this->p_resetn); + wt_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_t); + wt_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_t); + wt_chbuf->p_vci (signal_vci_tgt_chbuf); + + // wrapper ini CHBUF + wi_chbuf->p_clk (this->p_clk); + wi_chbuf->p_resetn (this->p_resetn); + wi_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_i); + wi_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_i); + wi_chbuf->p_vci (signal_vci_ini_chbuf); + + std::cout << " - CHBUF connected" << std::endl; + + // BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_vci_tgt_brom); + + // wrapper tgt BROM + wt_brom->p_clk (this->p_clk); + wt_brom->p_resetn (this->p_resetn); + wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t); + wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t); + wt_brom->p_vci (signal_vci_tgt_brom); + + std::cout << " - BROM connected" << std::endl; + + // MTTY + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + for (size_t i = 0; i < nb_ttys; i++) + { + mtty->p_irq[i] (signal_irq_mtty[i]); + } + + // wrapper tgt MTTY + wt_mtty->p_clk (this->p_clk); + wt_mtty->p_resetn (this->p_resetn); + wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t); + wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t); + wt_mtty->p_vci (signal_vci_tgt_mtty); + + + // Sim Helper + simhelper->p_clk (this->p_clk); + simhelper->p_resetn (this->p_resetn); + simhelper->p_vci (signal_vci_tgt_simh); + + // wrapper tgt Sim Helper + wt_simhelper->p_clk (this->p_clk); + wt_simhelper->p_resetn (this->p_resetn); + wt_simhelper->p_dspin_cmd (signal_dspin_cmd_simh_t); + wt_simhelper->p_dspin_rsp (signal_dspin_rsp_simh_t); + wt_simhelper->p_vci (signal_vci_tgt_simh); + + std::cout << " - MTTY connected" << std::endl; + } +} // end constructor + + + +template TsarXbarCluster::~TsarXbarCluster() { + + dealloc_elems > (p_cmd_in, 4, 3); + dealloc_elems >(p_cmd_out, 4, 3); + dealloc_elems > (p_rsp_in, 4, 2); + dealloc_elems >(p_rsp_out, 4, 2); + + for (size_t p = 0; p < n_procs; p++) + { + delete proc[p]; + delete wi_proc[p]; + } + + delete memc; + delete wt_memc; + delete xram; + delete xicu; + delete wt_xicu; + delete mdma; + delete wt_mdma; + delete wi_mdma; + delete xbar_cmd_d; + delete xbar_rsp_d; + delete xbar_m2p_c; + delete xbar_p2m_c; + delete xbar_clack_c; + delete router_cmd; + delete router_rsp; + if (brom != NULL) + { + delete brom; + delete wt_brom; + delete fbuf; + delete wt_fbuf; + delete bdev; + delete wt_bdev; + delete wi_bdev; + delete mnic; + delete wt_mnic; + delete chbuf; + delete wt_chbuf; + delete wi_chbuf; + delete mtty; + delete wt_mtty; + delete simhelper; + delete wt_simhelper; + } +} + + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + + +