Index: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 604)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 611)
@@ -454,10 +454,10 @@
       uint32_t     m_cpt_update_cost;    // Number of (flits * distance) for UPDT
 
-      uint32_t     m_cpt_m_inval;        // Number of requests causing M_INV
-      uint32_t     m_cpt_m_inval_local;  // Number of local M_INV transactions
-      uint32_t     m_cpt_m_inval_remote; // Number of remote M_INV transactions
-      uint32_t     m_cpt_m_inval_cost;   // Number of (flits * distance) for M_INV
-
-      uint32_t     m_cpt_br_inval;       // Number of BROADCAST INVAL
+      uint32_t     m_cpt_minval;         // Number of requests causing M_INV
+      uint32_t     m_cpt_minval_local;   // Number of local M_INV transactions
+      uint32_t     m_cpt_minval_remote;  // Number of remote M_INV transactions
+      uint32_t     m_cpt_minval_cost;    // Number of (flits * distance) for M_INV
+
+      uint32_t     m_cpt_binval;         // Number of BROADCAST INVAL
 
       uint32_t     m_cpt_cleanup_local;  // Number of local CLEANUP transactions
@@ -583,4 +583,5 @@
       sc_in<bool>                                 p_clk;
       sc_in<bool>                                 p_resetn;
+      sc_in<bool>                                 p_irq;
       soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
       soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
@@ -645,4 +646,5 @@
       uint32_t req_distance(uint32_t req_srcid);
       bool is_local_req(uint32_t req_srcid);
+      int  read_instrumentation(uint32_t regr, uint32_t & rdata);
 
       // Component attributes
@@ -685,4 +687,11 @@
       // broadcast address
       uint32_t                           m_broadcast_boundaries;
+
+      // configuration interface constants
+      const uint32_t m_config_addr_mask;
+      const uint32_t m_config_regr_width;
+      const uint32_t m_config_func_width;
+      const uint32_t m_config_regr_idx_mask;
+      const uint32_t m_config_func_idx_mask;
 
       // Fifo between TGT_CMD fsm and READ fsm
Index: branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 604)
+++ branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 611)
@@ -412,4 +412,12 @@
         m_broadcast_boundaries(0x7C1F),
 
+        // CONFIG interface
+        m_config_addr_mask((1<<12)-1),
+
+        m_config_regr_width(7),
+        m_config_func_width(3),
+        m_config_regr_idx_mask((1<<m_config_regr_width)-1),
+        m_config_func_idx_mask((1<<m_config_func_width)-1),
+
         //  FIFOs
         m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
@@ -677,4 +685,110 @@
     }
 
+    /////////////////////////////////////////////////////
+    tmpl(int)::read_instrumentation(uint32_t regr, uint32_t & rdata)
+    /////////////////////////////////////////////////////
+    {
+        int error = 0;
+
+        switch(regr)
+        {
+            ///////////////////////////////////////////////////////
+            //       DIRECT instrumentation registers            //
+            // Registers of 32 bits and therefore only LO is     //
+            // implemented.                                      //
+            //                                                   //
+            // The HI may be used in future implementations      //
+            ///////////////////////////////////////////////////////
+
+            // LOCAL
+
+            case MEMC_LOCAL_READ_LO   : rdata = m_cpt_read_local        ; break;
+            case MEMC_LOCAL_WRITE_LO  : rdata = m_cpt_write_flits_local ; break;
+            case MEMC_LOCAL_LL_LO     : rdata = m_cpt_ll_local          ; break;
+            case MEMC_LOCAL_SC_LO     : rdata = m_cpt_sc_local          ; break;
+            case MEMC_LOCAL_CAS_LO    : rdata = m_cpt_cas_local         ; break;
+            case MEMC_LOCAL_READ_HI   :
+            case MEMC_LOCAL_WRITE_HI  :
+            case MEMC_LOCAL_LL_HI     :
+            case MEMC_LOCAL_SC_HI     :
+            case MEMC_LOCAL_CAS_HI    : rdata = 0; break;
+
+            // REMOTE
+
+            case MEMC_REMOTE_READ_LO  : rdata = m_cpt_read_remote        ; break;
+            case MEMC_REMOTE_WRITE_LO : rdata = m_cpt_write_flits_remote ; break;
+            case MEMC_REMOTE_LL_LO    : rdata = m_cpt_ll_remote          ; break;
+            case MEMC_REMOTE_SC_LO    : rdata = m_cpt_sc_remote          ; break;
+            case MEMC_REMOTE_CAS_LO   : rdata = m_cpt_cas_remote         ; break;
+            case MEMC_REMOTE_READ_HI  :
+            case MEMC_REMOTE_WRITE_HI :
+            case MEMC_REMOTE_LL_HI    :
+            case MEMC_REMOTE_SC_HI    :
+            case MEMC_REMOTE_CAS_HI   : rdata = 0; break;
+
+            // COST
+
+            case MEMC_COST_READ_LO    : rdata = m_cpt_read_cost ; break;
+            case MEMC_COST_WRITE_LO   : rdata = m_cpt_write_cost; break;
+            case MEMC_COST_LL_LO      : rdata = m_cpt_ll_cost   ; break;
+            case MEMC_COST_SC_LO      : rdata = m_cpt_sc_cost   ; break;
+            case MEMC_COST_CAS_LO     : rdata = m_cpt_cas_cost  ; break;
+            case MEMC_COST_READ_HI    :
+            case MEMC_COST_WRITE_HI   :
+            case MEMC_COST_LL_HI      :
+            case MEMC_COST_SC_HI      :
+            case MEMC_COST_CAS_HI     : rdata = 0; break;
+
+            ///////////////////////////////////////////////////////
+            //       COHERENCE instrumentation registers         //
+            // Registers of 32 bits and therefore only LO is     //
+            // implemented.                                      //
+            //                                                   //
+            // The HI may be used in future implementations      //
+            ///////////////////////////////////////////////////////
+
+            // LOCAL
+
+            case MEMC_LOCAL_MUPDATE_LO  : rdata = m_cpt_update_local ; break;
+            case MEMC_LOCAL_MINVAL_LO   : rdata = m_cpt_minval_local ; break;
+            case MEMC_LOCAL_CLEANUP_LO  : rdata = m_cpt_cleanup_local; break;
+            case MEMC_LOCAL_MUPDATE_HI  :
+            case MEMC_LOCAL_MINVAL_HI   :
+            case MEMC_LOCAL_CLEANUP_HI  : rdata = 0; break;
+
+            // REMOTE
+
+            case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_update_remote ; break;
+            case MEMC_REMOTE_MINVAL_LO  : rdata = m_cpt_minval_remote ; break;
+            case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break;
+            case MEMC_REMOTE_MUPDATE_HI :
+            case MEMC_REMOTE_MINVAL_HI  :
+            case MEMC_REMOTE_CLEANUP_HI : rdata = 0; break;
+
+            // COST
+
+            case MEMC_COST_MUPDATE_LO   : rdata = m_cpt_update_cost   ; break;
+            case MEMC_COST_MINVAL_LO    : rdata = m_cpt_minval_cost   ; break;
+            case MEMC_COST_CLEANUP_LO   : rdata = m_cpt_cleanup_cost  ; break;
+            case MEMC_COST_MUPDATE_HI   :
+            case MEMC_COST_MINVAL_HI    :
+            case MEMC_COST_CLEANUP_HI   : rdata = 0; break;
+
+            // TOTAL
+
+            case MEMC_TOTAL_MUPDATE_LO  : rdata = m_cpt_update ; break;
+            case MEMC_TOTAL_MINVAL_LO   : rdata = m_cpt_minval ; break;
+            case MEMC_TOTAL_BINVAL_LO   : rdata = m_cpt_binval ; break;
+            case MEMC_TOTAL_MUPDATE_HI  :
+            case MEMC_TOTAL_MINVAL_HI   :
+            case MEMC_TOTAL_BINVAL_HI   : rdata = 0; break;
+
+            // unknown register
+
+            default                     : error = 1;
+        }
+
+        return error;
+    }
 
     //////////////////////////////////////////////////
@@ -746,10 +860,10 @@
                 << "[022] UPDT COST (FLITS * DIST)  = " << m_cpt_update_cost << std::endl
                 << std::endl
-                << "[023] REQUESTS TRIG. M_INV      = " << m_cpt_m_inval << std::endl
-                << "[024] LOCAL M_INV               = " << m_cpt_m_inval_local << std::endl
-                << "[025] REMOTE M_INV              = " << m_cpt_m_inval_remote << std::endl
-                << "[026] M_INV COST (FLITS * DIST) = " << m_cpt_m_inval_cost << std::endl
+                << "[023] REQUESTS TRIG. M_INV      = " << m_cpt_minval << std::endl
+                << "[024] LOCAL M_INV               = " << m_cpt_minval_local << std::endl
+                << "[025] REMOTE M_INV              = " << m_cpt_minval_remote << std::endl
+                << "[026] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl
                 << std::endl
-                << "[027] BROADCAT INVAL            = " << m_cpt_br_inval << std::endl
+                << "[027] BROADCAT INVAL            = " << m_cpt_binval << std::endl
                 << std::endl
                 << "[028] LOCAL CLEANUP             = " << m_cpt_cleanup_local << std::endl
@@ -800,10 +914,10 @@
                 << "[117] AV. REMOTE UPDT PER UP REQ = " << (double) m_cpt_update_remote / m_cpt_update << std::endl
                 << std::endl
-                << "[118] INVAL MULTICAST RATE  = " << (double) m_cpt_m_inval / m_cpt_cycles << std::endl
-                << "[119] AVE. INVAL PER M_INV  = " << (double) (m_cpt_m_inval_local + m_cpt_m_inval_remote) / m_cpt_m_inval << std::endl
-                << "[120] AV. LOC INV PER M_INV = " << (double) m_cpt_m_inval_local / m_cpt_m_inval << std::endl
-                << "[121] AV. REM INV PER M_INV = " << (double) m_cpt_m_inval_remote / m_cpt_m_inval << std::endl
+                << "[118] INVAL MULTICAST RATE  = " << (double) m_cpt_minval / m_cpt_cycles << std::endl
+                << "[119] AVE. INVAL PER M_INV  = " << (double) (m_cpt_minval_local + m_cpt_minval_remote) / m_cpt_minval << std::endl
+                << "[120] AV. LOC INV PER M_INV = " << (double) m_cpt_minval_local / m_cpt_minval << std::endl
+                << "[121] AV. REM INV PER M_INV = " << (double) m_cpt_minval_remote / m_cpt_minval << std::endl
                 << std::endl
-                << "[122] INVAL BROADCAST RATE  = " << (double) m_cpt_br_inval / m_cpt_cycles << std::endl
+                << "[122] INVAL BROADCAST RATE  = " << (double) m_cpt_binval / m_cpt_cycles << std::endl
                 << "[123] WRITE DIRTY RATE      = " << (double) m_cpt_write_dirty / m_cpt_cycles << std::endl
                 << std::endl
@@ -1025,9 +1139,9 @@
             m_cpt_update_remote      = 0;
             m_cpt_update_cost        = 0;
-            m_cpt_m_inval            = 0;
-            m_cpt_m_inval_local      = 0;
-            m_cpt_m_inval_remote     = 0;
-            m_cpt_m_inval_cost       = 0;
-            m_cpt_br_inval           = 0;
+            m_cpt_minval            = 0;
+            m_cpt_minval_local      = 0;
+            m_cpt_minval_remote     = 0;
+            m_cpt_minval_cost       = 0;
+            m_cpt_binval           = 0;
             m_cpt_cleanup_local      = 0;
             m_cpt_cleanup_remote     = 0;
@@ -1308,4 +1422,194 @@
             case TGT_CMD_CONFIG:    // execute config request and return response
                 {
+                    ///////////////////////////////////////////////////////////
+                    //  Decoding CONFIG interface commands                   //
+                    //                                                       //
+                    //  VCI ADDRESS                                          //
+                    //  ================================================     //
+                    //  GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00      //
+                    //   IDX   |  IDX  |     | (3 bits) | (7 bits) |         //
+                    //  ================================================     //
+                    //                                                       //
+                    //  For instrumentation : FUNC_IDX = 0b001               //
+                    //                                                       //
+                    //  REGS_IDX                                             //
+                    //  ============================================         //
+                    //       Z     |    Y      |    X     |   W              //
+                    //    (1 bit)  | (2 bits)  | (3 bits) | (1 bit)          //
+                    //  ============================================         //
+                    //                                                       //
+                    //  Z : DIRECT / COHERENCE                               //
+                    //  Y : SUBTYPE ( LOCAL, REMOTE, OTHER )                 //
+                    //  X : REGISTER INDEX                                   //
+                    //  W : HI / LO                                          //
+                    //                                                       //
+                    //  For configuration: FUNC_IDX = 0b000                  //
+                    //                                                       //
+                    //  REGS_IDX                                             //
+                    //  ============================================         //
+                    //             RESERVED             |    X     |         //
+                    //             (4 bits)             | (3 bits) |         //
+                    //  ============================================         //
+                    //                                                       //
+                    //  X : REGISTER INDEX                                   //
+                    //                                                       //
+                    //  For WRITE MISS error signaling: FUNC = 0x010         //
+                    //                                                       //
+                    //  REGS_IDX                                             //
+                    //  ============================================         //
+                    //             RESERVED             |    X     |         //
+                    //             (4 bits)             | (3 bits) |         //
+                    //  ============================================         //
+                    //                                                       //
+                    //  X : REGISTER INDEX                                   //
+                    //                                                       //
+                    ///////////////////////////////////////////////////////////
+
+                    addr_t addr_lsb = p_vci_tgt.address.read() &
+                                      m_config_addr_mask;
+
+                    addr_t cell = (addr_lsb / vci_param_int::B);
+
+                    size_t regr = cell &
+                                  m_config_regr_idx_mask;
+
+                    size_t func = (cell >> m_config_regr_width) &
+                                  m_config_func_idx_mask;
+
+                    bool     need_rsp; 
+                    int      error;  
+                    uint32_t rdata = 0;         // default value
+                    uint32_t wdata = p_vci_tgt.wdata.read();
+
+                    switch(func)
+                    {
+                        // memory operation
+                        case MEMC_CONFIG:
+                        {
+                            if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
+                                    and (regr == MEMC_LOCK))
+                            {
+                                rdata            = (uint32_t) r_config_lock.read();
+                                need_rsp         = true;
+                                error            = 0;
+                                r_config_lock    = true;
+                            }
+                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)  // release lock
+                                    and (regr == MEMC_LOCK))
+                            {
+                                need_rsp      = true;
+                                error         = 0;
+                                r_config_lock = false;
+                            }
+                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_lo
+                                    and (regr == MEMC_ADDR_LO))
+                            {
+                                assert( ((wdata % (m_words * vci_param_int::B)) == 0) and
+                                        "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line");
+
+                                need_rsp         = true;
+                                error            = 0;
+                                r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) |
+                                    ((addr_t)wdata);
+                            }
+                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set addr_hi
+                                    and (regr == MEMC_ADDR_HI))
+
+                            {
+                                need_rsp         = true;
+                                error            = 0;
+                                r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) |
+                                    (((addr_t) wdata) << 32);
+                            }
+                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set buf_lines
+                                    and (regr == MEMC_BUF_LENGTH))
+                            {
+                                need_rsp         = true;
+                                error            = 0;
+                                size_t lines     = wdata / (m_words << 2);
+                                if (wdata % (m_words << 2)) lines++;
+                                r_config_cmd_lines = lines;
+                                r_config_rsp_lines = 0;
+                            }
+                            else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)   // set cmd type
+                                    and (regr == MEMC_CMD_TYPE))
+                            {
+                                need_rsp         = false;
+                                error            = 0;
+                                r_config_cmd     = wdata;
+
+                                // prepare delayed response from CONFIG FSM
+                                r_config_srcid   = p_vci_tgt.srcid.read();
+                                r_config_trdid   = p_vci_tgt.trdid.read();
+                                r_config_pktid   = p_vci_tgt.pktid.read();
+                            }
+                            else
+                            {
+                                need_rsp         = true;
+                                error            = 1;
+                            }
+
+                            break;
+                        }
+
+                        // instrumentation registers
+                        case MEMC_INSTRM:
+                        {
+                            need_rsp = true;
+
+                            if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
+                            {
+                                error = read_instrumentation(regr, rdata);
+                            }
+                            else
+                            {
+                                error = 1;
+                            }
+
+                            break;
+                        }
+
+                        //unknown function
+                        default:
+                        {
+                            need_rsp = true;
+                            error    = 1;
+
+                            break;
+                        }
+                    }
+
+                    if (need_rsp)
+                    {
+                        // blocked if previous pending request to TGT_RSP FSM
+                        if (r_tgt_cmd_to_tgt_rsp_req.read()) break;
+
+                        r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read();
+                        r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read();
+                        r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read();
+                        r_tgt_cmd_to_tgt_rsp_req   = true;
+                        r_tgt_cmd_to_tgt_rsp_error = error;
+                        r_tgt_cmd_to_tgt_rsp_rdata = rdata;
+                    }
+
+                    r_tgt_cmd_fsm = TGT_CMD_IDLE;
+
+#if DEBUG_MEMC_TGT_CMD
+                    if (m_debug)
+                        std::cout << "  <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:"
+                            << " address = " << std::hex << p_vci_tgt.address.read()
+                            << " / func = " << func
+                            << " / regr = " << regr
+                            << " / rdata = " << rdata
+                            << " / wdata = " << p_vci_tgt.wdata.read()
+                            << " / need_rsp = " << need_rsp
+                            << " / error = " << error << std::endl;
+#endif
+                    break;
+                }
+
+#if 0
+            case TGT_CMD_CONFIG:    // execute config request and return response
+                {
                     addr_t   seg_base = m_seg[m_seg_config]->baseAddress();
                     addr_t   address  = p_vci_tgt.address.read();
@@ -1405,4 +1709,5 @@
                     break;
                 }
+#endif                         // #if 0
                 //////////////////
             case TGT_CMD_READ:    // Push a read request into read fifo
@@ -7191,10 +7496,10 @@
                         if (is_local_req(m_config_to_cc_send_srcid_fifo.read()))
                         {
-                            m_cpt_m_inval_local++;
+                            m_cpt_minval_local++;
                         }
                         else
                         {
-                            m_cpt_m_inval_remote++;
-                            m_cpt_m_inval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read());
+                            m_cpt_minval_remote++;
+                            m_cpt_minval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read());
                         }
                         // </Activity Counters>
@@ -7204,5 +7509,5 @@
                     if(r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false;
                     // <Activity Counters>
-                    m_cpt_m_inval++;
+                    m_cpt_minval++;
                     // </Activity Counters>
                     r_cc_send_fsm = CC_SEND_CONFIG_IDLE;
@@ -7236,5 +7541,5 @@
                     if(not p_dspin_m2p.read) break;
                     // <Activity Counters>
-                    m_cpt_br_inval++;
+                    m_cpt_binval++;
                     // </Activity Counters>
                     r_config_to_cc_send_brdcast_req = false;
@@ -7258,10 +7563,10 @@
                         if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read()))
                         {
-                            m_cpt_m_inval_local++;
+                            m_cpt_minval_local++;
                         }
                         else
                         {
-                            m_cpt_m_inval_remote++;
-                            m_cpt_m_inval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read());
+                            m_cpt_minval_remote++;
+                            m_cpt_minval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read());
                         }
                         // </Activity Counters>
@@ -7271,5 +7576,5 @@
                     if(r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false;
                     // <Activity Counters>
-                    m_cpt_m_inval++;
+                    m_cpt_minval++;
                     // </Activity Counters>
                     r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE;
@@ -7303,5 +7608,5 @@
                     if(not p_dspin_m2p.read) break;
                     // <Activity Counters>
-                    m_cpt_br_inval++;
+                    m_cpt_binval++;
                     // </Activity Counters>
                     r_xram_rsp_to_cc_send_brdcast_req = false;
@@ -7388,5 +7693,5 @@
 
                     // <Activity Counters>
-                    m_cpt_br_inval++;
+                    m_cpt_binval++;
                     // </Activity Counters>
 
@@ -7477,5 +7782,5 @@
                     if(not p_dspin_m2p.read) break;
                     // <Activity Counters>
-                    m_cpt_br_inval++;
+                    m_cpt_binval++;
                     // </Activity Counters>
 
Index: branches/RWT/modules/vci_mem_cache/include/soclib/mem_cache.h
===================================================================
--- branches/RWT/modules/vci_mem_cache/include/soclib/mem_cache.h	(revision 604)
+++ branches/RWT/modules/vci_mem_cache/include/soclib/mem_cache.h	(revision 611)
@@ -28,4 +28,13 @@
 #define MEM_CACHE_REGS_H
 
+enum SoclibMemCacheFunc
+{
+    MEMC_CONFIG = 0,
+    MEMC_INSTRM = 1,
+    MEMC_RERROR = 2,
+
+    MEMC_FUNC_SPAN = 0x200
+};
+
 enum SoclibMemCacheConfigRegs
 {
@@ -43,4 +52,139 @@
     MEMC_CMD_SYNC
 };
+
+///////////////////////////////////////////////////////////
+//  Decoding CONFIG interface commands                   //
+//                                                       //
+//  VCI ADDRESS                                          //
+//  ================================================     //
+//  GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00      //
+//   IDX   |  IDX  |     | (3 bits) | (7 bits) |         //
+//  ================================================     //
+//                                                       //
+//  For instrumentation: FUNC_IDX = 0b001                //
+//                                                       //
+//  REGS_IDX                                             //
+//  ============================================         //
+//       Z     |    Y      |    X     |   W              //
+//    (1 bit)  | (2 bits)  | (3 bits) | (1 bit)          //
+//  ============================================         //
+//                                                       //
+//  For configuration: FUNC_IDX = 0b000                  //
+//                                                       //
+//  REGS_IDX                                             //
+//  ============================================         //
+//             RESERVED             |    X     |         //
+//             (4 bits)             | (3 bits) |         //
+//  ============================================         //
+//                                                       //
+//  X : REGISTER INDEX                                   //
+//                                                       //
+//  For WRITE MISS error signaling: FUNC = 0x010         //
+//                                                       //
+//  REGS_IDX                                             //
+//  ============================================         //
+//             RESERVED             |    X     |         //
+//             (4 bits)             | (3 bits) |         //
+//  ============================================         //
+//                                                       //
+//  X : REGISTER INDEX                                   //
+//                                                       //
+///////////////////////////////////////////////////////////
+
+enum SoclibMemCacheInstrRegs {
+    ///////////////////////////////////////////////////////
+    //          DIRECT instrumentation registers         //
+    ///////////////////////////////////////////////////////
+
+    // LOCAL
+
+    MEMC_LOCAL_READ_LO   = 0x00,
+    MEMC_LOCAL_READ_HI   = 0x01,
+    MEMC_LOCAL_WRITE_LO  = 0x02,
+    MEMC_LOCAL_WRITE_HI  = 0x03,
+    MEMC_LOCAL_LL_LO     = 0x04,
+    MEMC_LOCAL_LL_HI     = 0x05,
+    MEMC_LOCAL_SC_LO     = 0x06,
+    MEMC_LOCAL_SC_HI     = 0x07,
+    MEMC_LOCAL_CAS_LO    = 0x08,
+    MEMC_LOCAL_CAS_HI    = 0x09,
+
+    // REMOTE
+
+    MEMC_REMOTE_READ_LO  = 0x10,
+    MEMC_REMOTE_READ_HI  = 0x11,
+    MEMC_REMOTE_WRITE_LO = 0x12,
+    MEMC_REMOTE_WRITE_HI = 0x13,
+    MEMC_REMOTE_LL_LO    = 0x14,
+    MEMC_REMOTE_LL_HI    = 0x15,
+    MEMC_REMOTE_SC_LO    = 0x16,
+    MEMC_REMOTE_SC_HI    = 0x17,
+    MEMC_REMOTE_CAS_LO   = 0x18,
+    MEMC_REMOTE_CAS_HI   = 0x19,
+
+    // COST
+
+    MEMC_COST_READ_LO    = 0x20,
+    MEMC_COST_READ_HI    = 0x21,
+    MEMC_COST_WRITE_LO   = 0x22,
+    MEMC_COST_WRITE_HI   = 0x23,
+    MEMC_COST_LL_LO      = 0x24,
+    MEMC_COST_LL_HI      = 0x25,
+    MEMC_COST_SC_LO      = 0x26,
+    MEMC_COST_SC_HI      = 0x27,
+    MEMC_COST_CAS_LO     = 0x28,
+    MEMC_COST_CAS_HI     = 0x29,
+
+    ///////////////////////////////////////////////////////
+    //       COHERENCE instrumentation registers         //
+    ///////////////////////////////////////////////////////
+
+    // LOCAL
+
+    MEMC_LOCAL_MUPDATE_LO  = 0x40,
+    MEMC_LOCAL_MUPDATE_HI  = 0x41,
+    MEMC_LOCAL_MINVAL_LO   = 0x42,
+    MEMC_LOCAL_MINVAL_HI   = 0x43,
+    MEMC_LOCAL_CLEANUP_LO  = 0x44,
+    MEMC_LOCAL_CLEANUP_HI  = 0x45,
+
+    // REMOTE
+
+    MEMC_REMOTE_MUPDATE_LO = 0x50,
+    MEMC_REMOTE_MUPDATE_HI = 0x51,
+    MEMC_REMOTE_MINVAL_LO  = 0x52,
+    MEMC_REMOTE_MINVAL_HI  = 0x53,
+    MEMC_REMOTE_CLEANUP_LO = 0x54,
+    MEMC_REMOTE_CLEANUP_HI = 0x55,
+
+    // COST
+
+    MEMC_COST_MUPDATE_LO   = 0x60,
+    MEMC_COST_MUPDATE_HI   = 0x61,
+    MEMC_COST_MINVAL_LO    = 0x62,
+    MEMC_COST_MINVAL_HI    = 0x63,
+    MEMC_COST_CLEANUP_LO   = 0x64,
+    MEMC_COST_CLEANUP_HI   = 0x65,
+
+    // TOTAL
+
+    MEMC_TOTAL_MUPDATE_LO  = 0x68,
+    MEMC_TOTAL_MUPDATE_HI  = 0x69,
+    MEMC_TOTAL_MINVAL_LO   = 0x6A,
+    MEMC_TOTAL_MINVAL_HI   = 0x6B,
+    MEMC_TOTAL_BINVAL_LO   = 0x6C,
+    MEMC_TOTAL_BINVAL_HI   = 0x6D,
+};
+
+enum SoclibMemCacheRerrorRegs
+{
+    MEMC_RERROR_ADDR_LO = 0,
+    MEMC_RERROR_ADDR_HI,
+    MEMC_RERROR_SRCID, 
+    MEMC_RERROR_IRQ_RESET,
+    MEMC_RERROR_IRQ_ENABLE
+};
+
+#define MEMC_REG(func,idx) ((func<<7)|idx) 
 
 #endif /* MEM_CACHE_REGS_H */