Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 583)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 616)
@@ -119,5 +119,6 @@
         "CMD_INS_UNC",
         "CMD_DATA_MISS",
-        "CMD_DATA_UNC",
+        "CMD_DATA_UNC_READ",
+        "CMD_DATA_UNC_WRITE",
         "CMD_DATA_WRITE",
         "CMD_DATA_LL",
@@ -127,5 +128,5 @@
 
 const char *vci_pktid_type_str[] = {
-        "TYPE_READ_DATA_UNC",
+        "TYPE_DATA_UNC",
         "TYPE_READ_DATA_MISS",            
         "TYPE_READ_INS_UNC",          
@@ -296,5 +297,4 @@
       r_dcache_save_be("r_dcache_save_be"),
       r_dcache_save_paddr("r_dcache_save_paddr"),
-      r_dcache_save_cacheable("r_dcache_save_cacheable"),
       r_dcache_save_cache_way("r_dcache_save_cache_way"),
       r_dcache_save_cache_set("r_dcache_save_cache_set"),
@@ -306,6 +306,8 @@
 
       r_dcache_vci_paddr("r_dcache_vci_paddr"),
+      r_dcache_vci_wdata("r_dcache_vci_wdata"),
       r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
       r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
+      r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
       r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
       r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
@@ -318,6 +320,4 @@
       r_dcache_xtn_way("r_dcache_xtn_way"),
       r_dcache_xtn_set("r_dcache_xtn_set"),
-
-      r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
 
       r_dcache_miss_type("r_dcache_miss_type"),
@@ -775,7 +775,4 @@
         r_dcache_vci_ll_req        = false;
         r_dcache_vci_sc_req        = false;
-
-        // No uncacheable write pending
-        r_dcache_pending_unc_write = false;
 
         // No processor XTN request pending
@@ -2145,20 +2142,19 @@
     //    This component implement a strong order between non cacheable access
     //    (read or write) : A new non cacheable VCI transaction starts only when
-    //    the previous non cacheable transaction is completed. Both cacheable and
-    //    non cacheable transactions use the write buffer, but the DCACHE FSM registers
-    //    a non cacheable write transaction posted in the write buffer by setting the
-    //    r_dcache_pending_unc_write flip_flop. All other non cacheable requests
-    //    are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
-    //    pending non cacheable write transaction completes).
+    //    the previous non cacheable transaction is completed. After send the VCI
+    //    transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
+    //    So the processor is blocked until the respone arrives in CACHE L1.
     //
     // 6/ Error handling:
     //    When the MMU is not activated, Read Bus Errors are synchronous events,
-    //    but Write Bus Errors are asynchronous events (processor is not frozen).
-    //    - If a Read Bus Error is detected, the VCI_RSP FSM sets the
+    //    Some Write Bus Errors are synchronous events when the request is a non cacheable access 
+    //    but some Write Bus Errors are asynchronous events when the request is cacheable access 
+    //    (processor is not frozen).
+    //    - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
     //      r_vci_rsp_data_error flip-flop, without writing any data in the
     //      r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
     //      by the DCACHE FSM.
-    //    - If a Write Bus Error is detected, the VCI_RSP FSM  signals
-    //      the asynchronous error using the setWriteBerr() method.
+    //    - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals 
+    //    the asynchronous error using the setWriteBerr() method.
     //    When the MMU is activated bus error are rare events, as the MMU
     //    checks the physical address before the VCI transaction starts.
@@ -2334,27 +2330,14 @@
         if ( r_dcache_wbuf_req.read() )
         {
-            // miss if write not cacheable, and previous non cacheable write registered
-            if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() )
-            {
-                wbuf_write_miss = true;
-            }
-            else		// try a registration into write buffer
-            {
-                bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
-                                         r_dcache_save_be.read(),
-                                         r_dcache_save_wdata.read(),
-                                         r_dcache_save_cacheable.read() );
+            bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
+                                     r_dcache_save_be.read(),
+                                     r_dcache_save_wdata.read(),
+                                     true);
 #ifdef INSTRUMENTATION
 m_cpt_wbuf_write++;
 #endif
-                if ( not wok ) // miss if write buffer full
-                {
-                    wbuf_write_miss = true;
-                }
-                else          // update the write_buffer state extension
-                {
-                    if(not r_dcache_pending_unc_write.read())
-                        r_dcache_pending_unc_write = not r_dcache_save_cacheable.read();
-                }
+            if ( not wok ) // miss if write buffer full
+            {
+                wbuf_write_miss = true;
             }
         } // end WBUF update
@@ -2712,6 +2695,4 @@
                 if ( valid_req ) 	// processor request is valid (after MMU check)
                 {
-                    r_dcache_save_cacheable  = cacheable;
-
                     // READ request
                     // The read requests are taken only if there is no cache update.
@@ -2770,8 +2751,9 @@
                         else					// uncacheable read
                         {
-                            r_dcache_vci_paddr    = paddr;
-                            r_dcache_vci_unc_be   = m_dreq.be;
-                            r_dcache_vci_unc_req  = true;
-                            r_dcache_fsm          = DCACHE_UNC_WAIT;
+                            r_dcache_vci_paddr      = paddr;
+                            r_dcache_vci_unc_be     = m_dreq.be;
+                            r_dcache_vci_unc_write  = false;
+                            r_dcache_vci_unc_req    = true;
+                            r_dcache_fsm            = DCACHE_UNC_WAIT;
 #if DEBUG_DCACHE
 if ( m_debug_activated )
@@ -2837,10 +2819,21 @@
                                 r_dcache_llsc_valid = false;
 
-                            // response to processor
-                            m_drsp.valid        = true;
-
-                            // activating P1 stage
-                            wbuf_request = true;
-                            updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
+                            if (not cacheable) 
+                            {                            
+                                r_dcache_vci_paddr      = paddr;
+                                r_dcache_vci_wdata      = m_dreq.wdata;
+                                r_dcache_vci_unc_write  = true;
+                                r_dcache_vci_unc_be     = m_dreq.be;
+                                r_dcache_vci_unc_req    = true;
+                                r_dcache_fsm            = DCACHE_UNC_WAIT;
+                            }
+                            else
+                            {
+                                // response to processor
+                                m_drsp.valid        = true;
+                                // activating P1 stage
+                                wbuf_request = true;
+                                updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
+                            }
                         }
                     } // end WRITE
@@ -4416,5 +4409,9 @@
         if ( r_vci_rsp_data_error.read() ) 	// bus error
         {
-            r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS;
+            if(r_dcache_vci_unc_write.read())
+                r_mmu_detr           = MMU_WRITE_DATA_ILLEGAL_ACCESS;
+            else
+                r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS;
+                
             r_mmu_dbvar          = m_dreq.addr;
             r_vci_rsp_data_error = false;
@@ -5093,7 +5090,4 @@
             size_t      wbuf_max;
 
-            bool dcache_unc_req = r_dcache_vci_unc_req.read() and
-                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
-
             bool dcache_miss_req = r_dcache_vci_miss_req.read() and
                  ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
@@ -5102,12 +5096,26 @@
                  ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
 
+            bool dcache_sc_req   = r_dcache_vci_sc_req.read() and
+                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
+
+            bool dcache_cas_req   = r_dcache_vci_cas_req.read() and
+                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
+
             bool icache_miss_req = r_icache_miss_req.read() and
                  ( not (r_dcache_vci_miss_req.read() or
-                        r_dcache_vci_ll_req.read() or
-                        r_dcache_vci_unc_req.read())
+                        r_dcache_vci_ll_req.read()   or
+                        r_dcache_vci_cas_req.read()  or
+                        r_dcache_vci_sc_req.read())
                      or r_vci_cmd_imiss_prio.read() );
 
-            // 1 - Data Read Miss
-            if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
+            // 1 - Data unc write
+            if ( r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
+            {
+                r_vci_cmd_fsm        = CMD_DATA_UNC_WRITE;
+                r_dcache_vci_unc_req = false;
+//                m_cpt_dunc_transaction++;
+            }
+            // 2 data read miss
+            else if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
             {
                 r_vci_cmd_fsm         = CMD_DATA_MISS;
@@ -5116,19 +5124,20 @@
 //                m_cpt_dmiss_transaction++;
             }
-            // 2 - Data Read Uncachable
-            else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
-            {
-                r_vci_cmd_fsm        = CMD_DATA_UNC;
+            // 3 - Data Read Uncachable
+            else if ( r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read() )
+            {
+                r_vci_cmd_fsm        = CMD_DATA_UNC_READ;
                 r_dcache_vci_unc_req = false;
 //                m_cpt_dunc_transaction++;
             }
-            // 3 - Data Linked Load
+            // 4 - Data Linked Load
             else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
             {
-                r_dcache_vci_ll_req = false;
-                r_vci_cmd_fsm       = CMD_DATA_LL;
+                r_vci_cmd_fsm         = CMD_DATA_LL;
+                r_dcache_vci_ll_req   = false;
+                r_vci_cmd_imiss_prio  = true;
 //              m_cpt_ll_transaction++;
             }
-            // 4 - Instruction Miss
+            // 5 - Instruction Miss
             else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
             {
@@ -5138,5 +5147,5 @@
 //                m_cpt_imiss_transaction++;
             }
-            // 5 - Instruction Uncachable
+            // 6 - Instruction Uncachable
             else if ( r_icache_unc_req.read() )
             {
@@ -5145,5 +5154,5 @@
 //                m_cpt_iunc_transaction++;
             }
-            // 6 - Data Write
+            // 7 - Data Write
             else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
             {
@@ -5155,18 +5164,20 @@
 //                m_length_write_transaction += (wbuf_max-wbuf_min+1);
             }
-            // 7 - Data Store Conditionnal
-            else if ( r_dcache_vci_sc_req.read() )
-            {
-                r_dcache_vci_sc_req = false;
-                r_vci_cmd_cpt  = 0;
-                r_vci_cmd_fsm  = CMD_DATA_SC;
+            // 8 - Data Store Conditionnal
+            else if ( dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
+            {
+                r_vci_cmd_fsm           = CMD_DATA_SC;
+                r_dcache_vci_sc_req     = false;
+                r_vci_cmd_imiss_prio    = true;
+                r_vci_cmd_cpt           = 0;
 //              m_cpt_sc_transaction++;
             }
-            // 8 - Compare And Swap
-            else if ( r_dcache_vci_cas_req.read() )
-            {
-                r_vci_cmd_fsm        = CMD_DATA_CAS;
-                r_dcache_vci_cas_req = false;
-                r_vci_cmd_cpt        = 0;
+            // 9 - Compare And Swap
+            else if ( dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
+            {
+                r_vci_cmd_fsm           = CMD_DATA_CAS;
+                r_dcache_vci_cas_req    = false;
+                r_vci_cmd_imiss_prio    = true;
+                r_vci_cmd_cpt           = 0;
 //              m_cpt_cas_transaction++;
             }
@@ -5213,5 +5224,6 @@
         case CMD_INS_UNC:
         case CMD_DATA_MISS:
-        case CMD_DATA_UNC:
+        case CMD_DATA_UNC_READ:
+        case CMD_DATA_UNC_WRITE:
         case CMD_DATA_LL:
         {
@@ -5261,5 +5273,5 @@
             r_vci_rsp_cpt = 0;
 
-            if      ( (p_vci.rpktid.read() & 0x7) ==  TYPE_READ_DATA_UNC  )
+            if      ( (p_vci.rpktid.read() & 0x7) ==  TYPE_DATA_UNC  )
             {
                 r_vci_rsp_fsm = RSP_DATA_UNC;
@@ -5470,6 +5482,5 @@
                 r_vci_rsp_fsm = RSP_IDLE;
                 uint32_t   wbuf_index = p_vci.rtrdid.read();
-                bool       cacheable  = r_wbuf.completed(wbuf_index);
-                if ( not cacheable ) r_dcache_pending_unc_write = false;
+                r_wbuf.completed(wbuf_index);
                 if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
             }
@@ -5970,5 +5981,5 @@
         break;
 
-    case CMD_DATA_UNC:
+    case CMD_DATA_UNC_READ:
         p_vci.cmdval  = true;
         p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
@@ -5976,7 +5987,19 @@
         p_vci.be      = r_dcache_vci_unc_be.read();
         p_vci.trdid   = 0;
-        p_vci.pktid   = TYPE_READ_DATA_UNC;
+        p_vci.pktid   = TYPE_DATA_UNC;
         p_vci.plen    = 4;
         p_vci.cmd     = vci_param::CMD_READ;
+        p_vci.eop     = true;
+        break;
+
+    case CMD_DATA_UNC_WRITE:
+        p_vci.cmdval  = true;
+        p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
+        p_vci.wdata   = r_dcache_vci_wdata.read();
+        p_vci.be      = r_dcache_vci_unc_be.read();
+        p_vci.trdid   = 0;
+        p_vci.pktid   = TYPE_DATA_UNC;
+        p_vci.plen    = 4;
+        p_vci.cmd     = vci_param::CMD_WRITE;
         p_vci.eop     = true;
         break;
