Changeset 62 for trunk/modules/vci_cc_vcache_wrapper2_v1
- Timestamp:
- Jul 5, 2010, 12:12:10 PM (14 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r56 r62 33 33 34 34 //#define SOCLIB_MODULE_DEBUG 35 #define DEBUG_START_CYCLE 3306900036 35 #ifdef SOCLIB_MODULE_DEBUG 37 36 namespace { … … 612 611 613 612 #ifdef SOCLIB_MODULE_DEBUG 614 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){615 613 std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles 616 614 << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm] … … 621 619 << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 622 620 << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl; 623 }624 621 #endif 625 622 … … 635 632 636 633 #ifdef SOCLIB_MODULE_DEBUG 637 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){638 634 std::cout << name() << " Instruction Request: " << ireq << std::endl; 639 635 std::cout << name() << " Data Request: " << dreq << std::endl; 640 }641 636 #endif 642 637 … … 2058 2053 2059 2054 #ifdef SOCLIB_MODULE_DEBUG 2060 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){2061 2055 std::cout << name() << " Instruction Response: " << irsp << std::endl; 2062 }2063 2056 #endif 2064 2057 … … 4988 4981 4989 4982 #ifdef SOCLIB_MODULE_DEBUG 4990 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){4991 4983 std::cout << name() << " Data Response: " << drsp << std::endl; 4992 }4993 4984 #endif 4994 4985 … … 5906 5897 5907 5898 #ifdef SOCLIB_MODULE_DEBUG 5908 if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){5909 5899 std::cout << name() 5910 5900 << " Moore R/W:" << std::hex … … 5929 5919 << " p_vci_ini_c.eop: " << p_vci_ini_c.eop 5930 5920 << std::endl; 5931 }5932 5921 #endif 5933 5922 }
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