Index: /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 61)
+++ /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 62)
@@ -33,5 +33,4 @@
 
 //#define SOCLIB_MODULE_DEBUG
-#define DEBUG_START_CYCLE 33069000
 #ifdef SOCLIB_MODULE_DEBUG
 namespace {
@@ -612,5 +611,4 @@
 
 #ifdef SOCLIB_MODULE_DEBUG
-if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
 std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles  
        	  << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
@@ -621,5 +619,4 @@
        	  << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
           << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
-}
 #endif
 
@@ -635,8 +632,6 @@
 
 #ifdef SOCLIB_MODULE_DEBUG
-if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
     std::cout << name() << " Instruction Request: " << ireq << std::endl;
     std::cout << name() << " Data Request: " << dreq << std::endl;
-}
 #endif
 
@@ -2058,7 +2053,5 @@
 
 #ifdef SOCLIB_MODULE_DEBUG
-if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
     std::cout << name() << " Instruction Response: " << irsp << std::endl;
-}
 #endif
 
@@ -4988,7 +4981,5 @@
 
 #ifdef SOCLIB_MODULE_DEBUG
-if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
     std::cout << name() << " Data Response: " << drsp << std::endl;
-}
 #endif
 
@@ -5906,5 +5897,4 @@
 
 #ifdef SOCLIB_MODULE_DEBUG 
-if(m_cpt_total_cycles > DEBUG_START_CYCLE && m_srcid_rw==0){
    std::cout << name() 
       	     << " Moore R/W:" << std::hex
@@ -5929,5 +5919,4 @@
       	     << " p_vci_ini_c.eop: " << p_vci_ini_c.eop
       	     << std::endl;
-}
 #endif
 }