Index: /branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
===================================================================
--- /branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 634)
+++ /branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 635)
@@ -884,7 +884,10 @@
     m_cpt_total_cycles++;
 
-    m_debug_cleanup_fsm    = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
-    m_debug_icache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
-    m_debug_dcache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_cleanup_fsm = m_debug_cleanup_fsm ||
+        ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
+    m_debug_icache_fsm  = m_debug_icache_fsm ||
+        ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
+    m_debug_dcache_fsm  = m_debug_dcache_fsm ||
+        ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
 
     /////////////////////////////////////////////////////////////////////
@@ -2445,4 +2448,12 @@
                         r_dcache_fsm = DCACHE_IDLE;
 		        break;
+
+                    case iss_t::XTN_DEBUG_MASK: 		// debug mask
+                        m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
+                        m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
+                        m_debug_cleanup_fsm = ((m_dreq.wdata & 0x4) != 0);
+                        m_drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
 	
                     default:
@@ -2598,5 +2609,7 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dcache" << std::endl;
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT read in dcache"
+        << " / PADDR=" << std::hex << paddr
+        << std::endl;
 }
 #endif
@@ -3445,4 +3458,13 @@
             r_dcache_fsm = DCACHE_IDLE;
             m_drsp.valid = true;
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "<PROC " << name()
+        << " SWITCH PTPR>: PADDR=" << std::hex
+        << (m_dreq.wdata << (INDEX1_NBITS+2))
+        << std::endl;
+}
+#endif
         }
         break;