- Timestamp:
- Feb 20, 2014, 5:05:48 PM (11 years ago)
- Location:
- branches/v4/platforms/tsarv4_mono_mmu_ioc
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/v4/platforms/tsarv4_mono_mmu_ioc/desc.py
r410 r636 11 11 Uses('caba:vci_logger'), 12 12 Uses('caba:vci_multi_tty'), 13 Uses('caba:vci_xicu'), 13 Uses('caba:vci_icu'), 14 Uses('caba:vci_timer'), 14 15 Uses('caba:vci_block_device_tsar_v4'), 15 16 Uses('caba:vci_vgmn'), -
branches/v4/platforms/tsarv4_mono_mmu_ioc/segmentation.h
r418 r636 2 2 #define _SEGMENTATION_H 3 3 4 #define MEMC_BASE 0x000000005 #define MEMC_SIZE 0x10000000 // 256Mb4 #define MEMC_BASE 0x00000000 5 #define MEMC_SIZE 0x10000000 // 256Mb 6 6 7 #define BOOT_BASE 0xbfc000008 #define BOOT_SIZE 0x000400007 #define BOOT_BASE 0xbfc00000 8 #define BOOT_SIZE 0x00040000 9 9 10 #define EXIT_BASE0x1000000011 #define EXIT_SIZE 0x0000001010 #define ICU_BASE 0x10000000 11 #define ICU_SIZE 0x00000014 // 5 mapped-registers 12 12 13 #define MTTY_BASE 0x2000000014 #define MTTY_SIZE 0x0000001013 #define MTTY_BASE 0x14000000 14 #define MTTY_SIZE 0x0000000c // 3 mapped-registers 15 15 16 #define XICU_BASE 0x3000000017 #define XICU_SIZE 0x0000100016 #define TIMER_BASE 0x18000000 17 #define TIMER_SIZE 0x00000010 // 4 mapped-registers 18 18 19 #define IOBD_BASE 0x4000000020 #define IOBD_SIZE 0x0000002019 #define BD_BASE 0x1c000000 20 #define BD_SIZE 0x00000020 // 8 mapped-registers 21 21 22 22 #endif -
branches/v4/platforms/tsarv4_mono_mmu_ioc/top.cpp
r420 r636 30 30 31 31 #include "vci_simhelper.h" 32 #include "vci_icu.h" 32 33 #include "vci_multi_tty.h" 33 #include "vci_ xicu.h"34 #include "vci_timer.h" 34 35 #include "vci_block_device_tsar_v4.h" 35 36 … … 154 155 std::cout << "--dsk pathname" << std::endl; 155 156 std::cout << "[--dummy-boot]" << std::endl; 156 std::cout << "[- trace trace_start_cycle]" << std::endl;157 std::cout << "[--trace trace_start_cycle]" << std::endl; 157 158 exit(0); 158 159 } … … 185 186 186 187 /* 187 * mapping table 188 * mapping table (data and coherence) 188 189 */ 189 190 … … 193 194 194 195 // uncached peripherals 195 maptabd.add(Segment(" exit_d" , EXIT_BASE , EXIT_SIZE, IntTab(2), false));196 maptabd.add(Segment("mtty_d" , MTTY_BASE , MTTY_SIZE, IntTab(3), false));197 maptabd.add(Segment(" xicu_d" , XICU_BASE , XICU_SIZE , IntTab(4), false));198 maptabd.add(Segment(" iobd_d" , IOBD_BASE , IOBD_SIZE, IntTab(5), false));196 maptabd.add(Segment("icu_d" , ICU_BASE , ICU_SIZE , IntTab(2), false)); 197 maptabd.add(Segment("mtty_d" , MTTY_BASE , MTTY_SIZE , IntTab(3), false)); 198 maptabd.add(Segment("timer_d" , TIMER_BASE , TIMER_SIZE , IntTab(4), false)); 199 maptabd.add(Segment("bd_d" , BD_BASE , BD_SIZE , IntTab(5), false)); 199 200 200 201 std::cout << maptabd << std::endl; … … 223 224 { 224 225 /* boot linux image directly */ 225 const BinaryFileSymbol *bfs = loader.get_symbol_by_name("kernel_entry");226 std::cout << "setResetAdress: " << std::hex << bfs->address()<< std::endl;227 proc_iss::setResetAddress( bfs->address());226 uint64_t entry_addr = loader.get_entry_point_address(); 227 std::cout << "setResetAdress: " << std::hex << entry_addr << std::endl << std::endl; 228 proc_iss::setResetAddress(entry_addr); 228 229 } 229 230 … … 246 247 param.trace_enabled); 247 248 248 VciSimpleRam<vci_param> xram("xram", IntTab(0), maptabd, loader);249 VciSimpleRam<vci_param> ram("ram", IntTab(0), maptabd, loader); 249 250 250 251 VciSimpleRam<vci_param> rom("rom", IntTab(1), maptabd, loader); … … 257 258 param.trace_start_cycle, param.trace_enabled); 258 259 259 VciSimhelper<vci_param> vciexit("vciexit", IntTab(2), maptabd); 260 261 VciXicu<vci_param> xicu("xicu", maptabd, IntTab(4), 262 1, 2, 0, 1); // #timers, #hard_irqs, #soft_irqs, # output_irqs 260 VciIcu<vci_param> icu("icu", IntTab(2), maptabd, 261 3); // #input_irqs 263 262 264 263 VciMultiTty<vci_param> mtty("mtty", IntTab(3), maptabd, "vcitty0", NULL); 265 264 266 VciBlockDeviceTsarV4<vci_param> iobd("iobd", maptabd, IntTab(1), IntTab(5), 265 VciTimer<vci_param> timer("timer", IntTab(4), maptabd, 266 1); // #timers 267 268 VciBlockDeviceTsarV4<vci_param> bd("bd", maptabd, IntTab(1), IntTab(5), 267 269 param.dsk_path); // mapped_file[, block_size=512, latency=0] 268 270 269 VciVgmn<vci_param> ringd("ringd", maptabd,271 VciVgmn<vci_param> vgmnd("vgmnd", maptabd, 270 272 2, 6, // #initiators, #targets 271 273 2, 8, // min_latency, FIFO depth 272 274 IntTab(1)); // default target 273 275 274 VciVgmn<vci_param> ringc("ringc", maptabc,276 VciVgmn<vci_param> vgmnc("vgmnc", maptabc, 275 277 2, 2, // #initiators, #targets 276 278 2, 8); // min_latency, FIFO depth … … 288 290 alloc_elems<sc_signal<bool> >("signal_proc_irq", proc_iss::n_irq); 289 291 sc_signal<bool> signal_mtty_irq("signal_mtty_irq"); 290 sc_signal<bool> signal_iobd_irq("signal_iobd_irq"); 292 sc_signal<bool> signal_timer_irq("signal_timer_irq"); 293 sc_signal<bool> signal_bd_irq("signal_bd_irq"); 291 294 292 295 /* vci */ … … 295 298 VciSignals<vci_param> signal_vci_tgt_c_proc("vci_tgt_c_proc"); 296 299 297 VciSignals<vci_param> signal_vci_ xram("signal_vci_xram");298 299 VciSignals<vci_param> signal_vci_tgt_d_ brom("signal_vci_tgt_d_brom");300 VciSignals<vci_param> signal_vci_ram("signal_vci_ram"); 301 302 VciSignals<vci_param> signal_vci_tgt_d_rom("signal_vci_tgt_d_rom"); 300 303 301 304 VciSignals<vci_param> signal_vci_ini_c_memc("signal_vci_ini_c_memc"); … … 303 306 VciSignals<vci_param> signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"); 304 307 305 VciSignals<vci_param> signal_vci_tgt_d_exit("signal_vci_tgt_d_exit"); 306 307 VciSignals<vci_param> signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"); 308 VciSignals<vci_param> signal_vci_tgt_d_icu("signal_vci_tgt_d_icu"); 308 309 309 310 VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"); 310 311 311 VciSignals<vci_param> signal_vci_ini_d_iobd("signal_vci_ini_d_iobd"); 312 VciSignals<vci_param> signal_vci_tgt_d_iobd("signal_vci_tgt_d_iobd"); 312 VciSignals<vci_param> signal_vci_tgt_d_timer("signal_vci_tgt_d_timer"); 313 314 VciSignals<vci_param> signal_vci_ini_d_bd("signal_vci_ini_d_bd"); 315 VciSignals<vci_param> signal_vci_tgt_d_bd("signal_vci_tgt_d_bd"); 313 316 314 317 /* … … 324 327 proc.p_vci_tgt_c(signal_vci_tgt_c_proc); 325 328 326 xram.p_clk(signal_clk);327 xram.p_resetn(signal_resetn);328 xram.p_vci(signal_vci_xram);329 ram.p_clk(signal_clk); 330 ram.p_resetn(signal_resetn); 331 ram.p_vci(signal_vci_ram); 329 332 330 333 rom.p_clk(signal_clk); 331 334 rom.p_resetn(signal_resetn); 332 rom.p_vci(signal_vci_tgt_d_ brom);335 rom.p_vci(signal_vci_tgt_d_rom); 333 336 334 337 memc.p_clk(signal_clk); … … 337 340 memc.p_vci_tgt_cleanup(signal_vci_tgt_c_memc); 338 341 memc.p_vci_ini(signal_vci_ini_c_memc); 339 memc.p_vci_ixr(signal_vci_xram); 340 341 vciexit.p_clk(signal_clk); 342 vciexit.p_resetn(signal_resetn); 343 vciexit.p_vci(signal_vci_tgt_d_exit); 344 345 xicu.p_resetn(signal_resetn); 346 xicu.p_clk(signal_clk); 347 xicu.p_vci(signal_vci_tgt_d_xicu); 348 xicu.p_hwi[0](signal_mtty_irq); 349 xicu.p_hwi[1](signal_iobd_irq); 350 xicu.p_irq[0](signal_proc_irq[0]); 342 memc.p_vci_ixr(signal_vci_ram); 343 344 icu.p_resetn(signal_resetn); 345 icu.p_clk(signal_clk); 346 icu.p_vci(signal_vci_tgt_d_icu); 347 icu.p_irq_in[0](signal_mtty_irq); 348 icu.p_irq_in[1](signal_timer_irq); 349 icu.p_irq_in[2](signal_bd_irq); 350 icu.p_irq(signal_proc_irq[0]); 351 351 352 352 mtty.p_clk(signal_clk); … … 355 355 mtty.p_irq[0](signal_mtty_irq); 356 356 357 iobd.p_clk(signal_clk); 358 iobd.p_resetn(signal_resetn); 359 iobd.p_vci_target(signal_vci_tgt_d_iobd); 360 iobd.p_vci_initiator(signal_vci_ini_d_iobd); 361 iobd.p_irq(signal_iobd_irq); 362 363 ringd.p_clk(signal_clk); 364 ringd.p_resetn(signal_resetn); 365 ringd.p_to_initiator[0](signal_vci_ini_d_proc); 366 ringd.p_to_initiator[1](signal_vci_ini_d_iobd); 367 ringd.p_to_target[0](signal_vci_tgt_d_memc); 368 ringd.p_to_target[1](signal_vci_tgt_d_brom); 369 ringd.p_to_target[2](signal_vci_tgt_d_exit); 370 ringd.p_to_target[3](signal_vci_tgt_d_mtty); 371 ringd.p_to_target[4](signal_vci_tgt_d_xicu); 372 ringd.p_to_target[5](signal_vci_tgt_d_iobd); 373 374 ringc.p_clk(signal_clk); 375 ringc.p_resetn(signal_resetn); 376 ringc.p_to_initiator[0](signal_vci_ini_c_proc); 377 ringc.p_to_initiator[1](signal_vci_ini_c_memc); 378 ringc.p_to_target[0](signal_vci_tgt_c_proc); 379 ringc.p_to_target[1](signal_vci_tgt_c_memc); 357 timer.p_clk(signal_clk); 358 timer.p_resetn(signal_resetn); 359 timer.p_vci(signal_vci_tgt_d_timer); 360 timer.p_irq[0](signal_timer_irq); 361 362 bd.p_clk(signal_clk); 363 bd.p_resetn(signal_resetn); 364 bd.p_vci_target(signal_vci_tgt_d_bd); 365 bd.p_vci_initiator(signal_vci_ini_d_bd); 366 bd.p_irq(signal_bd_irq); 367 368 vgmnd.p_clk(signal_clk); 369 vgmnd.p_resetn(signal_resetn); 370 vgmnd.p_to_initiator[0](signal_vci_ini_d_proc); 371 vgmnd.p_to_initiator[1](signal_vci_ini_d_bd); 372 vgmnd.p_to_target[0](signal_vci_tgt_d_memc); 373 vgmnd.p_to_target[1](signal_vci_tgt_d_rom); 374 vgmnd.p_to_target[2](signal_vci_tgt_d_icu); 375 vgmnd.p_to_target[3](signal_vci_tgt_d_mtty); 376 vgmnd.p_to_target[4](signal_vci_tgt_d_timer); 377 vgmnd.p_to_target[5](signal_vci_tgt_d_bd); 378 379 vgmnc.p_clk(signal_clk); 380 vgmnc.p_resetn(signal_resetn); 381 vgmnc.p_to_initiator[0](signal_vci_ini_c_proc); 382 vgmnc.p_to_initiator[1](signal_vci_ini_c_memc); 383 vgmnc.p_to_target[0](signal_vci_tgt_c_proc); 384 vgmnc.p_to_target[1](signal_vci_tgt_c_memc); 380 385 381 386 /*
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