Changeset 645 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src

Timestamp:

Feb 27, 2014, 12:32:14 PM (11 years ago)

Author:

devigne

Message:

Invalidation from memcache on a non-coherent line can cause a cleanup_data.
While sending this cleanup the processor can do a write on the same line.
However there is no guarantee that the memcache will receive transactions in
the correct order, ie it can handle writing before cleanup and therefore
overwrite the new value of writing that is more current than the data contained
in the cleanup.
To solve this problem we have block writes to ZOMBIE lines, they are unlocked
when the line becomes EMPTY.

File:

• branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (12 diffs)

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -441 +441 @@
     //r_dcache_in_tlb        = new bool[dcache_ways*dcache_sets];
     //r_dcache_contains_ptd  = new bool[dcache_ways*dcache_sets];
-    r_dcache_content_state = new int [dcache_ways*dcache_sets];
-    r_dcache_dirty_word    = new int [dcache_ways*dcache_sets*dcache_words];
+    r_dcache_content_state = new int  [dcache_ways*dcache_sets];
+    r_dcache_dirty_word    = new int  [dcache_ways*dcache_sets*dcache_words];
+    r_dcache_zombi_ncc     = new bool [dcache_ways*dcache_sets];
     ///////////////////////////////////////////////////////////
 
@@ -474 +475 @@
     delete [] r_dcache_content_state;
     delete [] r_dcache_dirty_word;
+    delete [] r_dcache_zombi_ncc;
     /////////////////////////////////
+    print_stats();
 }
 
@@ -642 +645 @@
         << "- DUNC TRANSACTION        = " << m_cpt_dunc_transaction << std::endl
         << "- LL TRANSACTION          = " << m_cpt_ll_transaction << std::endl
+        << "- WRITE DATA MISS         = " << m_cpt_data_write_miss << std::endl
+        << "- WRITE DATA ON ZOMBI     = " << m_cpt_data_write_on_zombi << std::endl
+        << "- WRITE DATA ON ZOMBI NCC = " << m_cpt_data_write_on_zombi_ncc << std::endl
         << "- CLEANUP DATA NOT DIRTY  = " << m_cpt_cleanup_data_not_dirty << std::endl
         << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl;
@@ -743 +749 @@
     m_cpt_cleanup_data_not_dirty  = 0;
     m_cpt_cleanup_data_dirty_word = 0;
+    m_cpt_data_write_miss = 0;
+    m_cpt_data_write_on_zombi = 0;
+    m_cpt_data_write_on_zombi_ncc = 0;
 
 }
@@ -778 +787 @@
             //r_dcache_contains_ptd[i]  = false;
             r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY;
-            r_dcache_dirty_word[i] = 0;
+            r_dcache_dirty_word[i]    = 0;
+            r_dcache_zombi_ncc[i]     = false;
         }
 
@@ -943 +953 @@
         m_cpt_cleanup_data_not_dirty  = 0;
         m_cpt_cleanup_data_dirty_word = 0;
+        m_cpt_data_write_miss = 0;
+        m_cpt_data_write_on_zombi = 0;
+        m_cpt_data_write_on_zombi_ncc = 0;
 
         m_cpt_itlbmiss_transaction      = 0;
@@ -2293 +2306 @@
 
 
-        // physical address computation : systematic DTLB access if activated)
+        // physical address computation : systematic DTLB access (if activated)
         if ( m_dreq.valid )
         {
-
 
             if ( r_mmu_mode.read() & DATA_TLB_MASK )  // DTLB activated
@@ -2930 +2942 @@
                             // response to processor
                             m_drsp.valid        = true;
+
+
                             // activating P1 stage
-                            if( (cache_state != CACHE_SLOT_STATE_ZOMBI )&&(cache_state != CACHE_SLOT_STATE_EMPTY )&&(cacheable) )
+                            if( (cache_state != CACHE_SLOT_STATE_ZOMBI) && (cache_state != CACHE_SLOT_STATE_EMPTY) && (cacheable) )
                             {
                                 wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC
                                 updt_request = true;
-                                if (cache_state == CACHE_SLOT_STATE_VALID_NCC) 
+                                if ( cache_state == CACHE_SLOT_STATE_VALID_NCC ) 
                                 {
-                                    if (r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY)
+                                    if ( r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY )
                                     {
                                         r_dcache_content_state[cache_way*m_dcache_sets+cache_set] = LINE_CACHE_DATA_DIRTY;
                                     }
-                                    r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;//dirty bit with word granularity (only for stats)
+                                    //dirty bit with word granularity (only for stats)
+                                    r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;
                                     m_cpt_data_write_back ++;
                                 }
                             }
+                            // We stall proc if a write request is on line ZOMBI
+                            // Invalidation from memcache on a non-coherent
+                            // line can cause cleanup_data. While sending this
+                            // cleanup the processor can do a write on the same
+                            // line. However there is no guarantee that the
+                            // memcache will receive transactions in the
+                            // correct order, ie it can handle writing before
+                            // cleanup and therefore overwrite the new value of
+                            // writing that is more current than the data
+                            // contained in the cleanup .
+                            // TODO : MAYBE NEED TO OPTIMIZE
+                            else if ( cache_state == CACHE_SLOT_STATE_ZOMBI )
+                            {
+                                m_drsp.valid = false;
+                                r_dcache_fsm = DCACHE_IDLE;
+                                // STAT : WRITE ON ZOMBI NCC LINE
+                                if (r_dcache_zombi_ncc[cache_way*m_dcache_sets+cache_set] == true)
+                                {
+                                    m_cpt_data_write_on_zombi_ncc++;
+                                }
+
+                                m_cpt_data_write_on_zombi++;
+                            }
                             else
                             {
+                               if ( cacheable ) m_cpt_data_write_miss++;
+                               
                                wbuf_request = true;
                                updt_request = false;
@@ -4086 +4126 @@
 m_cpt_dcache_dir_write++;
 #endif
+
+
+
         r_dcache.write_dir( way,
                             set,
@@ -4818 +4861 @@
 
                     r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+
                 }
                 else
@@ -4830 +4874 @@
                         r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 0;
                     }
+
+                    // STAT : WRITE ON ZOMBI NCC LINE
+                    r_dcache_zombi_ncc[r_dcache_miss_way.read()*m_dcache_sets+r_dcache_miss_set.read()] = true;
                 }
 
@@ -5187 +5234 @@
                                 r_dcache_clack_set.read(),
                                 CACHE_SLOT_STATE_EMPTY);
+
+            // STAT : WRITE ON ZOMBI NCC LINE
+            r_dcache_zombi_ncc[r_dcache_clack_way.read()*m_dcache_sets+r_dcache_clack_set.read()] = false;
 
             if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and