Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 615)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 645)
@@ -541,6 +541,7 @@
     //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
     //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
-    int                     *r_dcache_content_state;    // content state of one cache line
-    int                     *r_dcache_dirty_word;    // content state of one cache line
+    int                     *r_dcache_content_state; // content state of one cache line
+    int                     *r_dcache_dirty_word;    
+    bool                    *r_dcache_zombi_ncc;     
     //////////////////////////////////////////////////////////////////////////////////////
 
@@ -644,67 +645,67 @@
     // Activity counters
     ////////////////////////////////
-    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
-    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
-    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
-    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
-
-    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
-    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
-    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
-    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
-
-    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;	        // total number of cycles
+    uint32_t m_cpt_dcache_data_read;           // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;          // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;            // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;           // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;           // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;          // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;            // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;           // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	               // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	           // total number of cycles
 
     // Cache activity counters
-    uint32_t m_cpt_data_read;               // total number of read data
-    uint32_t m_cpt_data_write;              // total number of write data
+    uint32_t m_cpt_data_read;                  // total number of read data
+    uint32_t m_cpt_data_write;                 // total number of write data
     uint32_t m_cpt_data_write_back;
     uint32_t m_cpt_data_cleanup;
     uint32_t m_cpt_data_sc;
-    uint32_t m_cpt_data_miss;               // number of read miss
-    uint32_t m_cpt_ins_miss;                // number of instruction miss
-    uint32_t m_cpt_unc_read;                // number of read uncached
-    uint32_t m_cpt_write_cached;            // number of cached write
-    uint32_t m_cpt_ins_read;                // number of instruction read
-    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
-
-    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer
-    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
-    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
-    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
-
-    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
-    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
-    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
-    uint32_t m_cpt_dunc_transaction;         // number of VCI uncached read transactions
-    uint32_t m_cpt_ll_transaction;         // number of VCI uncached read transactions
-    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_cpt_data_miss;                  // number of read miss
+    uint32_t m_cpt_ins_miss;                   // number of instruction miss
+    uint32_t m_cpt_unc_read;                   // number of read uncached
+    uint32_t m_cpt_write_cached;               // number of cached write
+    uint32_t m_cpt_ins_read;                   // number of instruction read
+    uint32_t m_cpt_ins_spc_miss;               // number of speculative instruction miss
+
+    uint32_t m_cost_write_frz;                 // number of frozen cycles related to write buffer
+    uint32_t m_cost_data_miss_frz;             // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;              // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;              // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;          // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;          // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;            // number of VCI uncached read transactions
+    uint32_t m_cpt_dunc_transaction;           // number of VCI uncached read transactions
+    uint32_t m_cpt_ll_transaction;             // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;          // number of VCI write transactions
     uint32_t m_cpt_icache_unc_transaction;
 
-    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
-    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
-    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
-    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
-    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions
-    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+    uint32_t m_cost_imiss_transaction;         // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;         // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;           // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;         // cumulated duration for VCI WRITE transactions
+    uint32_t m_cost_icache_unc_transaction;    // cumulated duration for VCI IUNC transactions
+    uint32_t m_length_write_transaction;       // cumulated length for VCI WRITE transactions
 
     // TLB activity counters
-    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
-    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
-    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update
-    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line
-    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
-
-    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
-    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
-    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update
-    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
-    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
-    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
+    uint32_t m_cpt_ins_tlb_read;               // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;               // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_update_acc;         // number of instruction tlb update
+    uint32_t m_cpt_ins_tlb_occup_cache;        // number of instruction tlb occupy data cache line
+    uint32_t m_cpt_ins_tlb_hit_dcache;         // number of instruction tlb hit in data cache
+
+    uint32_t m_cpt_data_tlb_read;              // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;              // number of data tlb miss
+    uint32_t m_cpt_data_tlb_update_acc;        // number of data tlb update
+    uint32_t m_cpt_data_tlb_update_dirty;      // number of data tlb update dirty
+    uint32_t m_cpt_data_tlb_hit_dcache;        // number of data tlb hit in data cache
+    uint32_t m_cpt_data_tlb_occup_cache;       // number of data tlb occupy data cache line
     uint32_t m_cpt_tlb_occup_dcache;
 
-    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
-    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
     uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
     uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
@@ -722,40 +723,43 @@
     uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
 
-    uint32_t m_cost_itlbmiss_transaction;       // cumulated duration for VCI instruction TLB miss transactions
-    uint32_t m_cost_itlb_ll_transaction;        // cumulated duration for VCI instruction TLB ll acc transactions
-    uint32_t m_cost_itlb_sc_transaction;        // cumulated duration for VCI instruction TLB sc acc transactions
-    uint32_t m_cost_dtlbmiss_transaction;       // cumulated duration for VCI data TLB miss transactions
-    uint32_t m_cost_dtlb_ll_transaction;        // cumulated duration for VCI data TLB ll acc transactions
-    uint32_t m_cost_dtlb_sc_transaction;        // cumulated duration for VCI data TLB sc acc transactions
-    uint32_t m_cost_dtlb_ll_dirty_transaction;  // cumulated duration for VCI data TLB ll dirty transactions
-    uint32_t m_cost_dtlb_sc_dirty_transaction;  // cumulated duration for VCI data TLB sc dirty transactions
+    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
+    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
 
     // coherence activity counters
-    uint32_t m_cpt_cc_update_icache;            // number of coherence update instruction commands
-    uint32_t m_cpt_cc_update_dcache;            // number of coherence update data commands
-    uint32_t m_cpt_cc_inval_icache;             // number of coherence inval instruction commands
-    uint32_t m_cpt_cc_inval_dcache;             // number of coherence inval data commands
-    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast commands
-
-    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
-    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
-    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
-    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
-
-    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
-    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
-    uint32_t m_cpt_cleanup_data_not_dirty;
-    uint32_t m_cpt_cleanup_data_dirty_word;
-
-    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
-    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
-    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
-    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
-
-    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
-    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
-
-    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate
-    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
+    uint32_t m_cpt_cc_update_icache;           // number of coherence update instruction commands
+    uint32_t m_cpt_cc_update_dcache;           // number of coherence update data commands
+    uint32_t m_cpt_cc_inval_icache;            // number of coherence inval instruction commands
+    uint32_t m_cpt_cc_inval_dcache;            // number of coherence inval data commands
+    uint32_t m_cpt_cc_broadcast;               // number of coherence broadcast commands
+
+    uint32_t m_cost_updt_data_frz;             // number of frozen cycles related to coherence update data packets
+    uint32_t m_cost_inval_ins_frz;             // number of frozen cycles related to coherence inval instruction packets
+    uint32_t m_cost_inval_data_frz;            // number of frozen cycles related to coherence inval data packets
+    uint32_t m_cost_broadcast_frz;             // number of frozen cycles related to coherence broadcast packets
+
+    uint32_t m_cpt_cc_cleanup_ins;             // number of coherence cleanup packets
+    uint32_t m_cpt_cc_cleanup_data;            // number of coherence cleanup packets
+    uint32_t m_cpt_cleanup_data_not_dirty;     // number of total cleanup data without extra data flits
+    uint32_t m_cpt_cleanup_data_dirty_word;    // number of total words dirty in cleanup data
+    uint32_t m_cpt_data_write_miss;            // number of total write miss
+    uint32_t m_cpt_data_write_on_zombi;        // number of frozen cycles related to blocked write on line NCC/CC ZOMBI
+    uint32_t m_cpt_data_write_on_zombi_ncc;    // number of frozen cycles related to blocked write on line NCC ZOMBI
+
+    uint32_t m_cpt_icleanup_transaction;       // number of instruction cleanup transactions
+    uint32_t m_cpt_dcleanup_transaction;       // number of instructinumber of data cleanup transactions
+    uint32_t m_cost_icleanup_transaction;      // cumulated duration for VCI instruction cleanup transactions
+    uint32_t m_cost_dcleanup_transaction;      // cumulated duration for VCI data cleanup transactions
+
+    uint32_t m_cost_ins_tlb_inval_frz;         // number of frozen cycles related to checking ins tlb invalidate
+    uint32_t m_cpt_ins_tlb_inval;              // number of ins tlb invalidate
+
+    uint32_t m_cost_data_tlb_inval_frz;        // number of frozen cycles related to checking data tlb invalidate
+    uint32_t m_cpt_data_tlb_inval;             // number of data tlb invalidate
 
     // FSM activity counters
Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 615)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 645)
@@ -441,6 +441,7 @@
     //r_dcache_in_tlb        = new bool[dcache_ways*dcache_sets];
     //r_dcache_contains_ptd  = new bool[dcache_ways*dcache_sets];
-    r_dcache_content_state = new int [dcache_ways*dcache_sets];
-    r_dcache_dirty_word    = new int [dcache_ways*dcache_sets*dcache_words];
+    r_dcache_content_state = new int  [dcache_ways*dcache_sets];
+    r_dcache_dirty_word    = new int  [dcache_ways*dcache_sets*dcache_words];
+    r_dcache_zombi_ncc     = new bool [dcache_ways*dcache_sets];
     ///////////////////////////////////////////////////////////
 
@@ -474,5 +475,7 @@
     delete [] r_dcache_content_state;
     delete [] r_dcache_dirty_word;
+    delete [] r_dcache_zombi_ncc;
     /////////////////////////////////
+    print_stats();
 }
 
@@ -642,4 +645,7 @@
         << "- DUNC TRANSACTION        = " << m_cpt_dunc_transaction << std::endl
         << "- LL TRANSACTION          = " << m_cpt_ll_transaction << std::endl
+        << "- WRITE DATA MISS         = " << m_cpt_data_write_miss << std::endl
+        << "- WRITE DATA ON ZOMBI     = " << m_cpt_data_write_on_zombi << std::endl
+        << "- WRITE DATA ON ZOMBI NCC = " << m_cpt_data_write_on_zombi_ncc << std::endl
         << "- CLEANUP DATA NOT DIRTY  = " << m_cpt_cleanup_data_not_dirty << std::endl
         << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl;
@@ -743,4 +749,7 @@
     m_cpt_cleanup_data_not_dirty  = 0;
     m_cpt_cleanup_data_dirty_word = 0;
+    m_cpt_data_write_miss = 0;
+    m_cpt_data_write_on_zombi = 0;
+    m_cpt_data_write_on_zombi_ncc = 0;
 
 }
@@ -778,5 +787,6 @@
             //r_dcache_contains_ptd[i]  = false;
             r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY;
-            r_dcache_dirty_word[i] = 0;
+            r_dcache_dirty_word[i]    = 0;
+            r_dcache_zombi_ncc[i]     = false;
         }
 
@@ -943,4 +953,7 @@
         m_cpt_cleanup_data_not_dirty  = 0;
         m_cpt_cleanup_data_dirty_word = 0;
+        m_cpt_data_write_miss = 0;
+        m_cpt_data_write_on_zombi = 0;
+        m_cpt_data_write_on_zombi_ncc = 0;
 
         m_cpt_itlbmiss_transaction      = 0;
@@ -2293,8 +2306,7 @@
 
 
-        // physical address computation : systematic DTLB access if activated)
+        // physical address computation : systematic DTLB access (if activated)
         if ( m_dreq.valid )
         {
-
 
             if ( r_mmu_mode.read() & DATA_TLB_MASK )  // DTLB activated
@@ -2930,21 +2942,49 @@
                             // response to processor
                             m_drsp.valid        = true;
+
+
                             // activating P1 stage
-                            if( (cache_state != CACHE_SLOT_STATE_ZOMBI )&&(cache_state != CACHE_SLOT_STATE_EMPTY )&&(cacheable) )
+                            if( (cache_state != CACHE_SLOT_STATE_ZOMBI) && (cache_state != CACHE_SLOT_STATE_EMPTY) && (cacheable) )
                             {
                                 wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC
                                 updt_request = true;
-                                if (cache_state == CACHE_SLOT_STATE_VALID_NCC) 
+                                if ( cache_state == CACHE_SLOT_STATE_VALID_NCC ) 
                                 {
-                                    if (r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY)
+                                    if ( r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY )
                                     {
                                         r_dcache_content_state[cache_way*m_dcache_sets+cache_set] = LINE_CACHE_DATA_DIRTY;
                                     }
-                                    r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;//dirty bit with word granularity (only for stats)
+                                    //dirty bit with word granularity (only for stats)
+                                    r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;
                                     m_cpt_data_write_back ++;
                                 }
                             }
+                            // We stall proc if a write request is on line ZOMBI
+                            // Invalidation from memcache on a non-coherent
+                            // line can cause cleanup_data. While sending this
+                            // cleanup the processor can do a write on the same
+                            // line. However there is no guarantee that the
+                            // memcache will receive transactions in the
+                            // correct order, ie it can handle writing before
+                            // cleanup and therefore overwrite the new value of
+                            // writing that is more current than the data
+                            // contained in the cleanup .
+                            // TODO : MAYBE NEED TO OPTIMIZE
+                            else if ( cache_state == CACHE_SLOT_STATE_ZOMBI )
+                            {
+                                m_drsp.valid = false;
+                                r_dcache_fsm = DCACHE_IDLE;
+                                // STAT : WRITE ON ZOMBI NCC LINE
+                                if (r_dcache_zombi_ncc[cache_way*m_dcache_sets+cache_set] == true)
+                                {
+                                    m_cpt_data_write_on_zombi_ncc++;
+                                }
+
+                                m_cpt_data_write_on_zombi++;
+                            }
                             else
                             {
+                               if ( cacheable ) m_cpt_data_write_miss++;
+                               
                                wbuf_request = true;
                                updt_request = false;
@@ -4086,4 +4126,7 @@
 m_cpt_dcache_dir_write++;
 #endif
+
+
+
         r_dcache.write_dir( way,
                             set,
@@ -4818,4 +4861,5 @@
 
                     r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+
                 }
                 else
@@ -4830,4 +4874,7 @@
                         r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 0;
                     }
+
+                    // STAT : WRITE ON ZOMBI NCC LINE
+                    r_dcache_zombi_ncc[r_dcache_miss_way.read()*m_dcache_sets+r_dcache_miss_set.read()] = true;
                 }
 
@@ -5187,4 +5234,7 @@
                                 r_dcache_clack_set.read(),
                                 CACHE_SLOT_STATE_EMPTY);
+
+            // STAT : WRITE ON ZOMBI NCC LINE
+            r_dcache_zombi_ncc[r_dcache_clack_way.read()*m_dcache_sets+r_dcache_clack_set.read()] = false;
 
             if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
