Changeset 646 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source
- Timestamp:
- Feb 28, 2014, 4:45:35 PM (11 years ago)
- Location:
- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r645 r646 152 152 CMD_INS_UNC, 153 153 CMD_DATA_MISS, 154 CMD_DATA_UNC, 154 CMD_DATA_UNC_READ, 155 CMD_DATA_UNC_WRITE, 155 156 CMD_DATA_WRITE, 156 157 CMD_DATA_LL, … … 207 208 // b1 accÚs table llsc type SW / other 208 209 // b2 WRITE/CAS/LL/SC 209 TYPE_ READ_DATA_UNC= 0x0,210 TYPE_DATA_UNC = 0x0, 210 211 TYPE_READ_DATA_MISS = 0x1, 211 212 TYPE_READ_INS_UNC = 0x2, … … 279 280 }; 280 281 281 enum transaction_type_d_e282 {283 // b0 : 1 if cached284 // b1 : 1 if instruction285 TYPE_DATA_UNC = 0x0,286 TYPE_DATA_MISS = 0x1,287 TYPE_INS_UNC = 0x2,288 TYPE_INS_MISS = 0x3,289 };282 // enum transaction_type_d_e 283 // { 284 // // b0 : 1 if cached 285 // // b1 : 1 if instruction 286 // TYPE_DATA_UNC = 0x0, 287 // TYPE_DATA_MISS = 0x1, 288 // TYPE_INS_UNC = 0x2, 289 // TYPE_INS_MISS = 0x3, 290 // }; 290 291 291 292 //////////////////MODIFIED//////////////// … … 428 429 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 429 430 sc_signal<paddr_t> r_dcache_save_paddr; // physical address 430 sc_signal<bool> r_dcache_save_cacheable; // address cacheable431 431 sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) 432 432 sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) … … 439 439 // communication between DCACHE FSM and VCI_CMD FSM 440 440 sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command 441 sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command 441 442 sc_signal<bool> r_dcache_vci_miss_req; // read miss request 442 sc_signal<bool> r_dcache_vci_unc_req; // uncacheable read request 443 sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable read byte enable 443 sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) 444 sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable byte enable 445 sc_signal<uint32_t> r_dcache_vci_unc_write; // uncacheable data write request 444 446 sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS 445 447 sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS … … 458 460 sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) 459 461 sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) 460 461 // write buffer state extension462 sc_signal<bool> r_dcache_pending_unc_write; // pending uncacheable write in WBUF463 462 464 463 // handling dcache miss -
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r645 r646 124 124 "CMD_INS_UNC", 125 125 "CMD_DATA_MISS", 126 "CMD_DATA_UNC", 126 "CMD_DATA_UNC_READ", 127 "CMD_DATA_UNC_WRITE", 127 128 "CMD_DATA_WRITE", 128 129 "CMD_DATA_LL", … … 132 133 133 134 const char *vci_pktid_type_str[] = { 134 "TYPE_ READ_DATA_UNC",135 "TYPE_DATA_UNC", 135 136 "TYPE_READ_DATA_MISS", 136 137 "TYPE_READ_INS_UNC", … … 302 303 r_dcache_save_be("r_dcache_save_be"), 303 304 r_dcache_save_paddr("r_dcache_save_paddr"), 304 r_dcache_save_cacheable("r_dcache_save_cacheable"),305 305 r_dcache_save_cache_way("r_dcache_save_cache_way"), 306 306 r_dcache_save_cache_set("r_dcache_save_cache_set"), … … 312 312 313 313 r_dcache_vci_paddr("r_dcache_vci_paddr"), 314 r_dcache_vci_wdata("r_dcache_vci_wdata"), 314 315 r_dcache_vci_miss_req("r_dcache_vci_miss_req"), 315 316 r_dcache_vci_unc_req("r_dcache_vci_unc_req"), 316 317 r_dcache_vci_unc_be("r_dcache_vci_unc_be"), 318 r_dcache_vci_unc_write("r_dcache_vci_unc_write"), 317 319 r_dcache_vci_cas_req("r_dcache_vci_cas_req"), 318 320 r_dcache_vci_cas_old("r_dcache_vci_cas_old"), … … 324 326 r_dcache_xtn_way("r_dcache_xtn_way"), 325 327 r_dcache_xtn_set("r_dcache_xtn_set"), 326 327 r_dcache_pending_unc_write("r_dcache_pending_unc_write"),328 328 329 329 r_dcache_miss_type("r_dcache_miss_type"), … … 822 822 r_dcache_vci_ll_req = false; 823 823 r_dcache_vci_sc_req = false; 824 825 // No uncacheable write pending826 r_dcache_pending_unc_write = false;827 824 828 825 // No processor XTN request pending … … 2426 2423 if ( r_dcache_wbuf_req.read() ) 2427 2424 { 2428 // miss if write not cacheable, and previous non cacheable write registered 2429 if ( not r_dcache_save_cacheable.read() and r_dcache_pending_unc_write.read() ) 2430 { 2431 wbuf_write_miss = true; 2432 } 2433 else // try a registration into write buffer 2434 { 2435 bool wok = r_wbuf.write( r_dcache_save_paddr.read(), 2436 r_dcache_save_be.read(), 2437 r_dcache_save_wdata.read(), 2438 r_dcache_save_cacheable.read() ); 2425 bool wok = r_wbuf.write( r_dcache_save_paddr.read(), 2426 r_dcache_save_be.read(), 2427 r_dcache_save_wdata.read(), 2428 true ); 2439 2429 /*#ifdef INSTRUMENTATION 2440 2430 m_cpt_wbuf_write++; 2441 2431 #endif*/ 2442 if ( not wok ) // miss if write buffer full 2443 { 2444 wbuf_write_miss = true; 2445 } 2446 else // update the write_buffer state extension 2447 { 2448 if(not r_dcache_pending_unc_write.read()) 2449 r_dcache_pending_unc_write = not r_dcache_save_cacheable.read(); 2450 } 2451 } 2432 2433 if ( not wok ) // miss if write buffer full 2434 { 2435 wbuf_write_miss = true; 2436 } 2452 2437 } // end WBUF update 2453 2438 … … 2803 2788 if ( valid_req ) // processor request is valid (after MMU check) 2804 2789 { 2805 r_dcache_save_cacheable = cacheable;2806 2807 2790 // READ request 2808 2791 // The read requests are taken only if there is no cache update. … … 2871 2854 else // uncacheable read 2872 2855 { 2873 r_dcache_vci_paddr = paddr; 2874 r_dcache_vci_unc_be = m_dreq.be; 2875 r_dcache_vci_unc_req = true; 2876 r_dcache_fsm = DCACHE_UNC_WAIT; 2856 r_dcache_vci_paddr = paddr; 2857 r_dcache_vci_unc_be = m_dreq.be; 2858 r_dcache_vci_unc_write = false; 2859 r_dcache_vci_unc_req = true; 2860 r_dcache_fsm = DCACHE_UNC_WAIT; 2877 2861 #if DEBUG_DCACHE 2878 2862 if ( m_debug_activated ) … … 2940 2924 r_dcache_llsc_valid = false; 2941 2925 2942 // response to processor 2943 m_drsp.valid = true; 2944 2945 2926 if (not cacheable) 2927 { 2928 r_dcache_vci_paddr = paddr; 2929 r_dcache_vci_wdata = m_dreq.wdata; 2930 r_dcache_vci_unc_write = true; 2931 r_dcache_vci_unc_be = m_dreq.be; 2932 r_dcache_vci_unc_req = true; 2933 r_dcache_fsm = DCACHE_UNC_WAIT; 2934 } 2946 2935 // activating P1 stage 2947 if( (cache_state != CACHE_SLOT_STATE_ZOMBI) && (cache_state != CACHE_SLOT_STATE_EMPTY) && (cacheable) )2936 else if( (cache_state != CACHE_SLOT_STATE_ZOMBI) && (cache_state != CACHE_SLOT_STATE_EMPTY) ) 2948 2937 { 2949 2938 wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC 2950 2939 updt_request = true; 2940 m_drsp.valid = true; 2951 2941 if ( cache_state == CACHE_SLOT_STATE_VALID_NCC ) 2952 2942 { … … 2985 2975 else 2986 2976 { 2987 if ( cacheable )m_cpt_data_write_miss++;2977 m_cpt_data_write_miss++; 2988 2978 2979 m_drsp.valid = true; 2989 2980 wbuf_request = true; 2990 2981 updt_request = false; … … 4920 4911 if ( r_vci_rsp_data_error.read() ) // bus error 4921 4912 { 4922 r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; 4913 if(r_dcache_vci_unc_write.read()) 4914 r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; 4915 else 4916 r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; 4923 4917 r_mmu_dbvar = m_dreq.addr; 4924 4918 r_vci_rsp_data_error = false; … … 5746 5740 size_t wbuf_max; 5747 5741 5748 bool dcache_unc_req = r_dcache_vci_unc_req.read() and5749 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );5750 5751 5742 bool dcache_miss_req = r_dcache_vci_miss_req.read() and 5752 5743 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); … … 5755 5746 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); 5756 5747 5748 bool dcache_sc_req = r_dcache_vci_sc_req.read() and 5749 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); 5750 5751 bool dcache_cas_req = r_dcache_vci_cas_req.read() and 5752 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() ); 5753 5757 5754 bool icache_miss_req = r_icache_miss_req.read() and 5758 5755 ( not (r_dcache_vci_miss_req.read() or 5759 r_dcache_vci_ll_req.read() or 5760 r_dcache_vci_unc_req.read()) 5756 r_dcache_vci_ll_req.read() or 5757 r_dcache_vci_cas_req.read() or 5758 r_dcache_vci_sc_req.read()) 5761 5759 or r_vci_cmd_imiss_prio.read() ); 5762 // 1 - Data Read Miss 5763 if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) 5760 5761 // 1 - Data unc write 5762 if ( r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read()) 5763 { 5764 r_vci_cmd_fsm = CMD_DATA_UNC_WRITE; 5765 r_dcache_vci_unc_req = false; 5766 // m_cpt_dunc_transaction++; 5767 } 5768 // 2 data read miss 5769 else if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) 5764 5770 { 5765 5771 r_vci_cmd_fsm = CMD_DATA_MISS; … … 5768 5774 m_cpt_dmiss_transaction++; 5769 5775 } 5770 // 2- Data Read Uncachable5771 else if ( dcache_unc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))5772 { 5773 r_vci_cmd_fsm = CMD_DATA_UNC ;5776 // 3 - Data Read Uncachable 5777 else if ( r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read() ) 5778 { 5779 r_vci_cmd_fsm = CMD_DATA_UNC_READ; 5774 5780 r_dcache_vci_unc_req = false; 5775 5781 m_cpt_dunc_transaction++; 5776 5782 } 5777 // 3- Data Linked Load5783 // 4 - Data Linked Load 5778 5784 else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read())) 5779 5785 { 5780 r_dcache_vci_ll_req = false; 5781 r_vci_cmd_fsm = CMD_DATA_LL; 5786 r_vci_cmd_fsm = CMD_DATA_LL; 5787 r_dcache_vci_ll_req = false; 5788 r_vci_cmd_imiss_prio = true; 5782 5789 m_cpt_ll_transaction++; 5783 5790 } 5784 // 4- Instruction Miss5791 // 5 - Instruction Miss 5785 5792 else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) ) 5786 5793 { … … 5790 5797 m_cpt_imiss_transaction++; 5791 5798 } 5792 // 5- Instruction Uncachable5799 // 6 - Instruction Uncachable 5793 5800 else if ( r_icache_unc_req.read() ) 5794 5801 { … … 5797 5804 //m_cpt_iunc_transaction++; 5798 5805 } 5799 // 6- Data Write5806 // 7 - Data Write 5800 5807 else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) ) 5801 5808 { … … 5807 5814 m_length_write_transaction += (wbuf_max-wbuf_min+1); 5808 5815 } 5809 // 7 - Data Store Conditionnal 5810 else if ( r_dcache_vci_sc_req.read() ) 5811 { 5812 r_dcache_vci_sc_req = false; 5813 r_vci_cmd_cpt = 0; 5814 r_vci_cmd_fsm = CMD_DATA_SC; 5816 // 8 - Data Store Conditionnal 5817 else if ( dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) 5818 { 5819 r_vci_cmd_fsm = CMD_DATA_SC; 5820 r_dcache_vci_sc_req = false; 5821 r_vci_cmd_imiss_prio = true; 5822 r_vci_cmd_cpt = 0; 5815 5823 //m_cpt_sc_transaction++; 5816 5824 } 5817 // 8 - Compare And Swap 5818 else if ( r_dcache_vci_cas_req.read() ) 5819 { 5820 r_vci_cmd_fsm = CMD_DATA_CAS; 5821 r_dcache_vci_cas_req = false; 5822 r_vci_cmd_cpt = 0; 5825 // 9 - Compare And Swap 5826 else if ( dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()) ) 5827 { 5828 r_vci_cmd_fsm = CMD_DATA_CAS; 5829 r_dcache_vci_cas_req = false; 5830 r_vci_cmd_imiss_prio = true; 5831 r_vci_cmd_cpt = 0; 5823 5832 //m_cpt_cas_transaction++; 5824 5833 } … … 5865 5874 case CMD_INS_UNC: 5866 5875 case CMD_DATA_MISS: 5867 case CMD_DATA_UNC: 5876 case CMD_DATA_UNC_READ: 5877 case CMD_DATA_UNC_WRITE: 5868 5878 case CMD_DATA_LL: 5869 5879 { … … 5913 5923 r_vci_rsp_cpt = 0; 5914 5924 if (r_dcache_vci_paddr.read() == 0x1f624) std::cout << "Tansaction on barrier, pktid = " << p_vci.rpktid.read() << std::endl; 5915 if ( (p_vci.rpktid.read() & 0x7) == TYPE_ READ_DATA_UNC )5925 if ( (p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC ) 5916 5926 { 5917 5927 r_vci_rsp_fsm = RSP_DATA_UNC; … … 6135 6145 r_vci_rsp_fsm = RSP_IDLE; 6136 6146 uint32_t wbuf_index = p_vci.rtrdid.read(); 6137 bool cacheable = r_wbuf.completed(wbuf_index); 6138 if ( not cacheable ) r_dcache_pending_unc_write = false; 6147 r_wbuf.completed(wbuf_index); 6139 6148 if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); 6140 6149 } … … 6683 6692 break; 6684 6693 6685 case CMD_DATA_UNC :6694 case CMD_DATA_UNC_READ: 6686 6695 p_vci.cmdval = true; 6687 6696 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; … … 6689 6698 p_vci.be = r_dcache_vci_unc_be.read(); 6690 6699 p_vci.trdid = 0; 6691 p_vci.pktid = TYPE_ READ_DATA_UNC;6700 p_vci.pktid = TYPE_DATA_UNC; 6692 6701 p_vci.plen = 4; 6693 6702 p_vci.cmd = vci_param::CMD_READ; 6703 p_vci.eop = true; 6704 break; 6705 6706 case CMD_DATA_UNC_WRITE: 6707 p_vci.cmdval = true; 6708 p_vci.address = r_dcache_vci_paddr.read() & ~0x3; 6709 p_vci.wdata = r_dcache_vci_wdata.read(); 6710 p_vci.be = r_dcache_vci_unc_be.read(); 6711 p_vci.trdid = 0; 6712 p_vci.pktid = TYPE_DATA_UNC; 6713 p_vci.plen = 4; 6714 p_vci.cmd = vci_param::CMD_WRITE; 6694 6715 p_vci.eop = true; 6695 6716 break;
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