Index: branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/metadata/vci_xicu.sd =================================================================== --- branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/metadata/vci_xicu.sd (revision 647) +++ branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/metadata/vci_xicu.sd (revision 647) @@ -0,0 +1,43 @@ + +# -*- python -*- + +__id__ = "$Id: vci_xicu.sd 1698 2010-04-14 03:29:34Z nipo $" +__version__ = "$Revision: 1698 $" + +Module('caba:vci_xicu', + classname = 'soclib::caba::VciXicu', + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + ], + header_files = ['../source/include/vci_xicu.h', + ], + interface_files = [ + '../../include/soclib/xicu.h', + ], + implementation_files = ['../source/src/vci_xicu.cpp',], + ports = [ + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:vci_target', 'p_vci'), + Port('caba:bit_in', 'p_hwi', parameter.Reference('hwi_count')), + Port('caba:bit_out', 'p_irq', parameter.Reference('irq_count')), + ], + uses = [ + Uses('caba:base_module'), + Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'), + ], + instance_parameters = [ + parameter.Module('mt', 'common:mapping_table'), + parameter.IntTab('index'), + parameter.Int('pti_count'), + parameter.Int('hwi_count'), + parameter.Int('wti_count'), + parameter.Int('irq_count'), + ], + extensions = [ + 'dsx:addressable=index', + 'dsx:max_segments=1', + 'dsx:get_ident=index:p_vci:mt', + 'dsx:device=xicu', + ], +) Index: branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/source/include/vci_xicu.h =================================================================== --- branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/source/include/vci_xicu.h (revision 647) +++ branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/source/include/vci_xicu.h (revision 647) @@ -0,0 +1,115 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6 + * Nicolas Pouillon , 2009 + * + * Maintainers: nipo + */ +#ifndef SOCLIB_VCI_XICU_H +#define SOCLIB_VCI_XICU_H + +#include +#include "vci_target_fsm.h" +#include "caba_base_module.h" +#include "mapping_table.h" + +namespace soclib { +namespace caba { + +template +class VciXicu + : public caba::BaseModule +{ +private: + std::list m_seglist; + soclib::caba::VciTargetFsm m_vci_fsm; + + const size_t m_pti_count; + const size_t m_hwi_count; + const size_t m_wti_count; + const size_t m_irq_count; + + uint32_t* r_msk_pti; + uint32_t* r_msk_wti; + uint32_t* r_msk_hwi; + uint32_t r_pti_pending; + uint32_t r_wti_pending; + uint32_t r_hwi_pending; + uint32_t *r_pti_per; + uint32_t *r_pti_val; + uint32_t *r_wti_reg; + + uint32_t m_clock_cycles; + + + bool on_write( int seg, + typename vci_param::addr_t addr, + typename vci_param::data_t data, + int be ); + bool on_read( int seg, + typename vci_param::addr_t addr, + typename vci_param::data_t &data ); + + void transition(); + void genMoore(); + + +protected: + SC_HAS_PROCESS(VciXicu); + +public: + sc_core::sc_in p_clk; + sc_core::sc_in p_resetn; + soclib::caba::VciTarget p_vci; + sc_core::sc_out* p_irq; + sc_core::sc_in* p_hwi; + + void print_trace( size_t channel ); + + ~VciXicu(); + + VciXicu( + sc_core::sc_module_name name, + const soclib::common::MappingTable &mt, + const soclib::common::IntTab &index, + size_t pti_count, + size_t hwi_count, + size_t wti_count, + size_t irq_count); + + soclib_static_assert(vci_param::B == 4); +}; + +}} + +#endif /* SOCLIB_VCI_XICU_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/source/src/vci_xicu.cpp =================================================================== --- branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/source/src/vci_xicu.cpp (revision 647) +++ branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/caba/source/src/vci_xicu.cpp (revision 647) @@ -0,0 +1,508 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6 + * Nicolas Pouillon , 2009 + */ + +#include + +#include "xicu.h" +#include "register.h" +#include "arithmetics.h" +#include "alloc_elems.h" +#include "../include/vci_xicu.h" + +namespace soclib { +namespace caba { + +using namespace soclib; + +#define tmpl(t) template t VciXicu + +#ifdef SOCLIB_MODULE_DEBUG +#define CHECK_BOUNDS(x) \ + do { \ + if ( idx >= (m_##x##_count) ) { \ + std::cout << name() << " error: " #x " index " << idx \ + << " out of bounds (" \ + << m_##x##_count << ")" \ + << std::endl; \ + return false; \ + } \ + } while(0) +#else +#define CHECK_BOUNDS(x) do { if ( idx >= (m_##x##_count) ) return false; } while(0) +#endif + +////////////////////////////////////////////////////// +tmpl(bool)::on_write( int seg, + typename vci_param::addr_t addr, + typename vci_param::data_t data, + int be) +{ + size_t cell = (size_t)addr / vci_param::B; + size_t idx = cell & 0x1f; + size_t func = (cell >> 5) & 0x1f; + + if ( be != 0xf ) + return false; + + switch (func) + { + case XICU_WTI_REG: + CHECK_BOUNDS(wti); + r_wti_reg[idx] = data; + r_wti_pending |= 1< >("irq", irq_count)), + p_hwi(soclib::common::alloc_elems >("hwi", hwi_count)) +{ + std::cout << " - Building VciXicu : " << name << std::endl; + + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; + } + + m_vci_fsm.on_read_write( on_read, on_write ); + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); +} + +////////////////////// +tmpl(/**/)::~VciXicu() +{ + delete [] r_msk_pti; + delete [] r_msk_wti; + delete [] r_msk_hwi; + delete [] r_pti_per; + delete [] r_pti_val; + delete [] r_wti_reg; + soclib::common::dealloc_elems(p_irq, m_irq_count); + soclib::common::dealloc_elems(p_hwi, m_hwi_count); +} + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/include/soclib/xicu.h =================================================================== --- branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/include/soclib/xicu.h (revision 647) +++ branches/fault_tolerance/module/infrastructure_component/interrupt_infrastructure/vci_xicu/include/soclib/xicu.h (revision 647) @@ -0,0 +1,69 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6 + * Nicolas Pouillon , 2009 + * + * Maintainers: nipo + */ + +#ifndef XICU_REGS_H +#define XICU_REGS_H + +enum SoclibXicuFunc { + XICU_WTI_REG = 0, + XICU_PTI_PER = 1, + XICU_PTI_VAL = 2, + XICU_PTI_ACK = 3, + + XICU_MSK_PTI = 4, + XICU_MSK_PTI_ENABLE = 5, + XICU_MSK_PTI_DISABLE = 6, + XICU_PTI_ACTIVE = 6, + + XICU_MSK_HWI = 8, + XICU_MSK_HWI_ENABLE = 9, + XICU_MSK_HWI_DISABLE = 10, + XICU_HWI_ACTIVE = 10, + + XICU_MSK_WTI = 12, + XICU_MSK_WTI_ENABLE = 13, + XICU_MSK_WTI_DISABLE = 14, + XICU_WTI_ACTIVE = 14, + + XICU_PRIO = 15, + + XICU_CONFIG = 16, +}; + +#define XICU_REG(func, idx) (((func)<<5)|(idx)) + +#endif /* XICU_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd =================================================================== --- branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd (revision 647) @@ -0,0 +1,73 @@ + +# -*- python -*- + +Module('caba:vci_cc_vcache_wrapper', + classname = 'soclib::caba::VciCcVCacheWrapper', + + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + parameter.Int('dspin_in_width'), + parameter.Int('dspin_out_width'), + parameter.Module('iss_t') + ], + + header_files = [ '../source/include/vci_cc_vcache_wrapper.h' ], + + implementation_files = [ '../source/src/vci_cc_vcache_wrapper.cpp' ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + Uses('caba:multi_write_buffer'), + Uses('caba:generic_fifo'), + Uses('caba:generic_cache_tsar', + addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', + parameter.Reference('addr_size'))), + Uses('caba:generic_tlb', + addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', + parameter.Reference('addr_size'))), + Uses('common:address_masking_table', + data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', + parameter.Reference('addr_size')) + ), + Uses('caba:dspin_dhccp_param'), + ], + + ports = [ + Port('caba:vci_initiator', 'p_vci'), + Port('caba:dspin_input', 'p_dspin_m2p', + dspin_data_size = parameter.Reference('dspin_in_width')), + Port('caba:dspin_output', 'p_dspin_p2m', + dspin_data_size = parameter.Reference('dspin_out_width')), + Port('caba:dspin_input', 'p_dspin_clack', + dspin_data_size = parameter.Reference('dspin_in_width')), + Port('caba:bit_in','p_irq', parameter.Constant('n_irq')), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock') + ], + + instance_parameters = [ + parameter.Int('proc_id'), + parameter.Module('mt', 'common:mapping_table'), + parameter.Module('mc', 'common:mapping_table'), + parameter.IntTab('initiator_rw_index'), + parameter.IntTab('initiator_c_index'), + parameter.IntTab('target_index'), + parameter.Int('itlb_ways'), + parameter.Int('itlb_sets'), + parameter.Int('dtlb_ways'), + parameter.Int('dtlb_sets'), + parameter.Int('icache_ways'), + parameter.Int('icache_sets'), + parameter.Int('icache_words'), + parameter.Int('dcache_ways'), + parameter.Int('dcache_sets'), + parameter.Int('dcache_words'), + parameter.Int('wbuf_nlines'), + parameter.Int('wbuf_nwords'), + parameter.Int('max_frozen_cycles') + ], +) + + Index: branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 647) @@ -0,0 +1,768 @@ +/* -*- c++ -*- + * + * File : vci_cc_vcache_wrapper.h + * Copyright (c) UPMC, Lip6, SoC + * Authors : Alain GREINER, Yang GAO + * Date : 27/11/2011 + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Maintainers: cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr + */ + +#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H +#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H + +#include +#include +#include "caba_base_module.h" +#include "multi_write_buffer.h" +#include "generic_fifo.h" +#include "generic_tlb.h" +#include "generic_cache.h" +#include "vci_initiator.h" +#include "dspin_interface.h" +#include "dspin_dhccp_param.h" +#include "mapping_table.h" +#include "static_assert.h" +#include "iss2.h" + +#define LLSC_TIMEOUT 10000 + +namespace soclib { +namespace caba { + +using namespace sc_core; + +//////////////////////////////////////////// +template +class VciCcVCacheWrapper +//////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + + typedef typename vci_param::fast_addr_t paddr_t; + + enum icache_fsm_state_e + { + ICACHE_IDLE, + // handling XTN processor requests + ICACHE_XTN_TLB_FLUSH, + ICACHE_XTN_CACHE_FLUSH, + ICACHE_XTN_CACHE_FLUSH_GO, + ICACHE_XTN_TLB_INVAL, + ICACHE_XTN_CACHE_INVAL_VA, + ICACHE_XTN_CACHE_INVAL_PA, + ICACHE_XTN_CACHE_INVAL_GO, + // handling tlb miss + ICACHE_TLB_WAIT, + // handling cache miss + ICACHE_MISS_SELECT, + ICACHE_MISS_CLEAN, + ICACHE_MISS_WAIT, + ICACHE_MISS_DATA_UPDT, + ICACHE_MISS_DIR_UPDT, + // handling unc read + ICACHE_UNC_WAIT, + // handling coherence requests + ICACHE_CC_CHECK, + ICACHE_CC_UPDT, + ICACHE_CC_INVAL, + }; + + enum dcache_fsm_state_e + { + DCACHE_IDLE, + // handling itlb & dtlb miss + DCACHE_TLB_MISS, + DCACHE_TLB_PTE1_GET, + DCACHE_TLB_PTE1_SELECT, + DCACHE_TLB_PTE1_UPDT, + DCACHE_TLB_PTE2_GET, + DCACHE_TLB_PTE2_SELECT, + DCACHE_TLB_PTE2_UPDT, + DCACHE_TLB_LR_UPDT, + DCACHE_TLB_LR_WAIT, + DCACHE_TLB_RETURN, + // handling processor XTN requests + DCACHE_XTN_SWITCH, + DCACHE_XTN_SYNC, + DCACHE_XTN_IC_INVAL_VA, + DCACHE_XTN_IC_FLUSH, + DCACHE_XTN_IC_INVAL_PA, + DCACHE_XTN_IT_INVAL, + DCACHE_XTN_DC_FLUSH, + DCACHE_XTN_DC_FLUSH_GO, + DCACHE_XTN_DC_INVAL_VA, + DCACHE_XTN_DC_INVAL_PA, + DCACHE_XTN_DC_INVAL_END, + DCACHE_XTN_DC_INVAL_GO, + DCACHE_XTN_DT_INVAL, + //handling dirty bit update + DCACHE_DIRTY_GET_PTE, + DCACHE_DIRTY_WAIT, + // handling processor miss requests + DCACHE_MISS_SELECT, + DCACHE_MISS_CLEAN, + DCACHE_MISS_WAIT, + DCACHE_MISS_DATA_UPDT, + DCACHE_MISS_DIR_UPDT, + // handling processor unc, ll and sc requests + DCACHE_UNC_WAIT, + DCACHE_LL_WAIT, + DCACHE_SC_WAIT, + // handling coherence requests + DCACHE_CC_CHECK, + DCACHE_CC_UPDT, + DCACHE_CC_INVAL, + // handling TLB inval (after a coherence or XTN request) + DCACHE_INVAL_TLB_SCAN, + }; + + enum cmd_fsm_state_e + { + CMD_IDLE, + CMD_INS_MISS, + CMD_INS_UNC, + CMD_DATA_MISS, + CMD_DATA_UNC_READ, + CMD_DATA_UNC_WRITE, + CMD_DATA_WRITE, + CMD_DATA_LL, + CMD_DATA_SC, + CMD_DATA_CAS, + }; + + enum rsp_fsm_state_e + { + RSP_IDLE, + RSP_INS_MISS, + RSP_INS_UNC, + RSP_DATA_MISS, + RSP_DATA_UNC, + RSP_DATA_LL, + RSP_DATA_WRITE, + }; + + enum cc_receive_fsm_state_e + { + CC_RECEIVE_IDLE, + CC_RECEIVE_BRDCAST_HEADER, + CC_RECEIVE_BRDCAST_NLINE, + CC_RECEIVE_INS_INVAL_HEADER, + CC_RECEIVE_INS_INVAL_NLINE, + CC_RECEIVE_INS_UPDT_HEADER, + CC_RECEIVE_INS_UPDT_NLINE, + CC_RECEIVE_DATA_INVAL_HEADER, + CC_RECEIVE_DATA_INVAL_NLINE, + CC_RECEIVE_DATA_UPDT_HEADER, + CC_RECEIVE_DATA_UPDT_NLINE, + CC_RECEIVE_INS_UPDT_DATA, + CC_RECEIVE_DATA_UPDT_DATA, + }; + + enum cc_send_fsm_state_e + { + CC_SEND_IDLE, + CC_SEND_CLEANUP_1, + CC_SEND_CLEANUP_2, + CC_SEND_MULTI_ACK, + }; + + /* transaction type, pktid field */ + enum transaction_type_e + { + // b3 unused + // b2 READ / NOT READ + // if READ + // b1 DATA / INS + // b0 UNC / MISS + // else + // b1 accÚs table llsc type SW / other + // b2 WRITE/CAS/LL/SC + TYPE_DATA_UNC = 0x0, + TYPE_READ_DATA_MISS = 0x1, + TYPE_READ_INS_UNC = 0x2, + TYPE_READ_INS_MISS = 0x3, + TYPE_WRITE = 0x4, + TYPE_CAS = 0x5, + TYPE_LL = 0x6, + TYPE_SC = 0x7 + }; + + /* SC return values */ + enum sc_status_type_e + { + SC_SUCCESS = 0x00000000, + SC_FAIL = 0x00000001 + }; + + // cc_send_type + typedef enum + { + CC_TYPE_CLEANUP, + CC_TYPE_MULTI_ACK, + } cc_send_t; + + // cc_receive_type + typedef enum + { + CC_TYPE_CLACK, + CC_TYPE_BRDCAST, + CC_TYPE_INVAL, + CC_TYPE_UPDT, + } cc_receive_t; + + // TLB Mode : ITLB / DTLB / ICACHE / DCACHE + enum + { + INS_TLB_MASK = 0x8, + DATA_TLB_MASK = 0x4, + INS_CACHE_MASK = 0x2, + DATA_CACHE_MASK = 0x1, + }; + + // Error Type + enum mmu_error_type_e + { + MMU_NONE = 0x0000, // None + MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 + MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 + MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode + MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page + MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write & undefined external access + MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write & Bus Error accessing PT1 + MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 + MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access + MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 + MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 + MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode + MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page + MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access + MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 + MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 + MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access + }; + + // miss types for data cache + enum dcache_miss_type_e + { + PTE1_MISS, + PTE2_MISS, + PROC_MISS, + }; + +// enum transaction_type_d_e +// { +// // b0 : 1 if cached +// // b1 : 1 if instruction +// TYPE_DATA_UNC = 0x0, +// TYPE_DATA_MISS = 0x1, +// TYPE_INS_UNC = 0x2, +// TYPE_INS_MISS = 0x3, +// }; + +public: + sc_in p_clk; + sc_in p_resetn; + sc_in p_irq[iss_t::n_irq]; + soclib::caba::VciInitiator p_vci; + soclib::caba::DspinInput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_p2m; + soclib::caba::DspinInput p_dspin_clack; + +private: + + // STRUCTURAL PARAMETERS + soclib::common::AddressDecodingTable m_cacheability_table; + + const size_t m_srcid; + const size_t m_cc_global_id; + const size_t m_nline_width; + const size_t m_itlb_ways; + const size_t m_itlb_sets; + const size_t m_dtlb_ways; + const size_t m_dtlb_sets; + const size_t m_icache_ways; + const size_t m_icache_sets; + const paddr_t m_icache_yzmask; + const size_t m_icache_words; + const size_t m_dcache_ways; + const size_t m_dcache_sets; + const paddr_t m_dcache_yzmask; + const size_t m_dcache_words; + const size_t m_x_width; + const size_t m_y_width; + const size_t m_proc_id; + const uint32_t m_max_frozen_cycles; + const size_t m_paddr_nbits; + uint32_t m_debug_start_cycle; + bool m_debug_ok; + + //////////////////////////////////////// + // Communication with processor ISS + //////////////////////////////////////// + typename iss_t::InstructionRequest m_ireq; + typename iss_t::InstructionResponse m_irsp; + typename iss_t::DataRequest m_dreq; + typename iss_t::DataResponse m_drsp; + + ///////////////////////////////////////////// + // debug variables + ///////////////////////////////////////////// + bool m_debug_previous_i_hit; + bool m_debug_previous_d_hit; + bool m_debug_activated; + + /////////////////////////////// + // Software visible REGISTERS + /////////////////////////////// + sc_signal r_mmu_ptpr; // page table pointer register + sc_signal r_mmu_mode; // mmu mode register + sc_signal r_mmu_word_lo; // mmu misc data low + sc_signal r_mmu_word_hi; // mmu misc data hight + sc_signal r_mmu_ibvar; // mmu bad instruction address + sc_signal r_mmu_dbvar; // mmu bad data address + sc_signal r_mmu_ietr; // mmu instruction error type + sc_signal r_mmu_detr; // mmu data error type + uint32_t r_mmu_params; // read-only + uint32_t r_mmu_release; // read_only + + + ////////////////////////////// + // ICACHE FSM REGISTERS + ////////////////////////////// + sc_signal r_icache_fsm; // state register + sc_signal r_icache_fsm_save; // return state for coherence op + sc_signal r_icache_vci_paddr; // physical address + sc_signal r_icache_vaddr_save; // virtual address from processor + + // icache miss handling + sc_signal r_icache_miss_way; // selected way for cache update + sc_signal r_icache_miss_set; // selected set for cache update + sc_signal r_icache_miss_word; // word index ( cache update) + sc_signal r_icache_miss_inval; // coherence request matching a miss + sc_signal r_icache_miss_clack; // waiting for a cleanup acknowledge + + // coherence request handling + sc_signal r_icache_cc_way; // selected way for cc update/inval + sc_signal r_icache_cc_set; // selected set for cc update/inval + sc_signal r_icache_cc_word; // word counter for cc update + sc_signal r_icache_cc_need_write; // activate the cache for writing + + // coherence clack handling + sc_signal r_icache_clack_req; // clack request + sc_signal r_icache_clack_way; // clack way + sc_signal r_icache_clack_set; // clack set + + // icache flush handling + sc_signal r_icache_flush_count; // slot counter used for cache flush + + // communication between ICACHE FSM and VCI_CMD FSM + sc_signal r_icache_miss_req; // cached read miss + sc_signal r_icache_unc_req; // uncached read miss + + // communication between ICACHE FSM and DCACHE FSM + sc_signal r_icache_tlb_miss_req; // (set icache/reset dcache) + sc_signal r_icache_tlb_rsp_error; // tlb miss response error + + // Filp-Flop in ICACHE FSM for saving the cleanup victim request + sc_signal r_icache_cleanup_victim_req; + sc_signal r_icache_cleanup_victim_nline; + + // communication between ICACHE FSM and CC_SEND FSM + sc_signal r_icache_cc_send_req; // ICACHE cc_send request + sc_signal r_icache_cc_send_type; // ICACHE cc_send request type + sc_signal r_icache_cc_send_nline; // ICACHE cc_send nline + sc_signal r_icache_cc_send_way; // ICACHE cc_send way + sc_signal r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index + + /////////////////////////////// + // DCACHE FSM REGISTERS + /////////////////////////////// + sc_signal r_dcache_fsm; // state register + sc_signal r_dcache_fsm_cc_save; // return state for coherence op + sc_signal r_dcache_fsm_scan_save; // return state for tlb scan op + // registers written in P0 stage (used in P1 stage) + sc_signal r_dcache_wbuf_req; // WBUF must be written in P1 stage + sc_signal r_dcache_updt_req; // DCACHE must be updated in P1 stage + sc_signal r_dcache_save_vaddr; // virtual address (from proc) + sc_signal r_dcache_save_wdata; // write data (from proc) + sc_signal r_dcache_save_be; // byte enable (from proc) + sc_signal r_dcache_save_paddr; // physical address + sc_signal r_dcache_save_cache_way; // selected way (from dcache) + sc_signal r_dcache_save_cache_set; // selected set (from dcache) + sc_signal r_dcache_save_cache_word; // selected word (from dcache) + // registers used by the Dirty bit sub-fsm + sc_signal r_dcache_dirty_paddr; // PTE physical address + sc_signal r_dcache_dirty_way; // way to invalidate in dcache + sc_signal r_dcache_dirty_set; // set to invalidate in dcache + + // communication between DCACHE FSM and VCI_CMD FSM + sc_signal r_dcache_vci_paddr; // physical address for VCI command + sc_signal r_dcache_vci_wdata; // write unc data for VCI command + sc_signal r_dcache_vci_miss_req; // read miss request + sc_signal r_dcache_vci_unc_req; // uncacheable request (read/write) + sc_signal r_dcache_vci_unc_be; // uncacheable byte enable + sc_signal r_dcache_vci_unc_write; // uncacheable data write request + sc_signal r_dcache_vci_cas_req; // atomic write request CAS + sc_signal r_dcache_vci_cas_old; // previous data value for a CAS + sc_signal r_dcache_vci_cas_new; // new data value for a CAS + sc_signal r_dcache_vci_ll_req; // atomic read request LL + sc_signal r_dcache_vci_sc_req; // atomic write request SC + sc_signal r_dcache_vci_sc_data; // SC data (command) + + // register used for XTN inval + sc_signal r_dcache_xtn_way; // selected way (from dcache) + sc_signal r_dcache_xtn_set; // selected set (from dcache) + + // handling dcache miss + sc_signal r_dcache_miss_type; // depending on the requester + sc_signal r_dcache_miss_word; // word index for cache update + sc_signal r_dcache_miss_way; // selected way for cache update + sc_signal r_dcache_miss_set; // selected set for cache update + sc_signal r_dcache_miss_inval; // coherence request matching a miss + sc_signal r_dcache_miss_clack; // waiting for a cleanup acknowledge + + // handling coherence requests + sc_signal r_dcache_cc_way; // selected way for cc update/inval + sc_signal r_dcache_cc_set; // selected set for cc update/inval + sc_signal r_dcache_cc_word; // word counter for cc update + sc_signal r_dcache_cc_need_write; // activate the cache for writing + + // coherence clack handling + sc_signal r_dcache_clack_req; // clack request + sc_signal r_dcache_clack_way; // clack way + sc_signal r_dcache_clack_set; // clack set + + // dcache flush handling + sc_signal r_dcache_flush_count; // slot counter used for cache flush + + // ll response handling + sc_signal r_dcache_ll_rsp_count; // flit counter used for ll rsp + + // used by the TLB miss sub-fsm + sc_signal r_dcache_tlb_vaddr; // virtual address for a tlb miss + sc_signal r_dcache_tlb_ins; // target tlb (itlb if true) + sc_signal r_dcache_tlb_paddr; // physical address of pte + sc_signal r_dcache_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_dcache_tlb_pte_ppn; // second word of pte2 + sc_signal r_dcache_tlb_cache_way; // selected way in dcache + sc_signal r_dcache_tlb_cache_set; // selected set in dcache + sc_signal r_dcache_tlb_cache_word; // selected word in dcache + sc_signal r_dcache_tlb_way; // selected way in tlb + sc_signal r_dcache_tlb_set; // selected set in tlb + + // ITLB and DTLB invalidation + sc_signal r_dcache_tlb_inval_line; // line index + sc_signal r_dcache_tlb_inval_set; // tlb set counter + + // communication between DCACHE FSM and ICACHE FSM + sc_signal r_dcache_xtn_req; // xtn request (caused by processor) + sc_signal r_dcache_xtn_opcode; // xtn request type + + // Filp-Flop in DCACHE FSM for saving the cleanup victim request + sc_signal r_dcache_cleanup_victim_req; + sc_signal r_dcache_cleanup_victim_nline; + + // communication between DCACHE FSM and CC_SEND FSM + sc_signal r_dcache_cc_send_req; // DCACHE cc_send request + sc_signal r_dcache_cc_send_type; // DCACHE cc_send request type + sc_signal r_dcache_cc_send_nline; // DCACHE cc_send nline + sc_signal r_dcache_cc_send_way; // DCACHE cc_send way + sc_signal r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index + + // dcache directory extension + bool *r_dcache_in_tlb; // copy exist in dtlb or itlb + bool *r_dcache_contains_ptd; // cache line contains a PTD + + // Physical address extension for data access + sc_signal r_dcache_paddr_ext; // CP2 register (if vci_address > 32) + + /////////////////////////////////// + // VCI_CMD FSM REGISTERS + /////////////////////////////////// + sc_signal r_vci_cmd_fsm; + sc_signal r_vci_cmd_min; // used for write bursts + sc_signal r_vci_cmd_max; // used for write bursts + sc_signal r_vci_cmd_cpt; // used for write bursts + sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss + + /////////////////////////////////// + // VCI_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_vci_rsp_fsm; + sc_signal r_vci_rsp_cpt; + sc_signal r_vci_rsp_ins_error; + sc_signal r_vci_rsp_data_error; + GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM + GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM + + /////////////////////////////////// + // CC_SEND FSM REGISTER + /////////////////////////////////// + sc_signal r_cc_send_fsm; // state register + sc_signal r_cc_send_last_client; // 0 dcache / 1 icache + + /////////////////////////////////// + // CC_RECEIVE FSM REGISTER + /////////////////////////////////// + sc_signal r_cc_receive_fsm; // state register + sc_signal r_cc_receive_data_ins; // request to : 0 dcache / 1 icache + + // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM + sc_signal r_cc_receive_word_idx; // word index + GenericFifo r_cc_receive_updt_fifo_be; + GenericFifo r_cc_receive_updt_fifo_data; + GenericFifo r_cc_receive_updt_fifo_eop; + + // communication between CC_RECEIVE FSM and ICACHE FSM + sc_signal r_cc_receive_icache_req; // cc_receive to icache request + sc_signal r_cc_receive_icache_type; // cc_receive type of request + sc_signal r_cc_receive_icache_way; // cc_receive to icache way + sc_signal r_cc_receive_icache_set; // cc_receive to icache set + sc_signal r_cc_receive_icache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_icache_nline; // cache line physical address + + // communication between CC_RECEIVE FSM and DCACHE FSM + sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request + sc_signal r_cc_receive_dcache_type; // cc_receive type of request + sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way + sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set + sc_signal r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_dcache_nline; // cache line physical address + + /////////////////////////////////// + // DSPIN CLACK INTERFACE REGISTER + /////////////////////////////////// + sc_signal r_dspin_clack_req; + sc_signal r_dspin_clack_flit; + + ////////////////////////////////////////////////////////////////// + // processor, write buffer, caches , TLBs + ////////////////////////////////////////////////////////////////// + + iss_t r_iss; + MultiWriteBuffer r_wbuf; + GenericCache r_icache; + GenericCache r_dcache; + GenericTlb r_itlb; + GenericTlb r_dtlb; + + ////////////////////////////////////////////////////////////////// + // llsc registration buffer + ////////////////////////////////////////////////////////////////// + + sc_signal r_dcache_llsc_paddr; + sc_signal r_dcache_llsc_key; + sc_signal r_dcache_llsc_count; + sc_signal r_dcache_llsc_valid; + + //////////////////////////////// + // Activity counters + //////////////////////////////// + uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ + uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE + uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ + uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE + + uint32_t m_cpt_icache_data_read; // ICACHE DATA READ + uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE + uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ + uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE + + uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen + uint32_t m_cpt_total_cycles; // total number of cycles + + // Cache activity counters + uint32_t m_cpt_data_read; // total number of read data + uint32_t m_cpt_data_write; // total number of write data + uint32_t m_cpt_data_miss; // number of read miss + uint32_t m_cpt_ins_miss; // number of instruction miss + uint32_t m_cpt_unc_read; // number of read uncached + uint32_t m_cpt_write_cached; // number of cached write + uint32_t m_cpt_ins_read; // number of instruction read + uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss + + uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer + uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss + uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read + uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss + + uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions + uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions + uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions + uint32_t m_cpt_write_transaction; // number of VCI write transactions + uint32_t m_cpt_icache_unc_transaction; + + uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions + uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions + uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions + uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions + uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions + uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions + + // TLB activity counters + uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read + uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss + uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update + uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line + uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache + + uint32_t m_cpt_data_tlb_read; // number of data tlb read + uint32_t m_cpt_data_tlb_miss; // number of data tlb miss + uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update + uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty + uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache + uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line + uint32_t m_cpt_tlb_occup_dcache; + + uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss + uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss + uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc + uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc + uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty + uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache + uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache + + uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions + uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions + uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions + uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions + uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions + uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions + uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions + uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions + + uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions + uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions + uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions + uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions + uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions + uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions + uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions + uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions + + // coherence activity counters + uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands + uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands + uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands + uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands + uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands + + uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets + uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets + uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets + uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets + + uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets + uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets + + uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions + uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions + uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions + uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions + + uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate + uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate + + uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate + uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate + + // FSM activity counters + uint32_t m_cpt_fsm_icache [64]; + uint32_t m_cpt_fsm_dcache [64]; + uint32_t m_cpt_fsm_cmd [64]; + uint32_t m_cpt_fsm_rsp [64]; + uint32_t m_cpt_fsm_cc_receive [64]; + uint32_t m_cpt_fsm_cc_send [64]; + + uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen + bool m_monitor_ok; // used to debug cache output + uint32_t m_monitor_base; + uint32_t m_monitor_length; + +protected: + SC_HAS_PROCESS(VciCcVCacheWrapper); + +public: + VciCcVCacheWrapper( + sc_module_name name, + const int proc_id, + const soclib::common::MappingTable &mtd, + const soclib::common::IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ); + + ~VciCcVCacheWrapper(); + + void print_cpi(); + void print_stats(); + void clear_stats(); + void print_trace(size_t mode = 0); + void cache_monitor(paddr_t addr); + void start_monitor(paddr_t,paddr_t); + void stop_monitor(); + inline void iss_set_debug_mask(uint v) + { + r_iss.set_debug_mask(v); + } + +private: + void transition(); + void genMoore(); + + soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); + soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); +}; + +}} + +#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 647) @@ -0,0 +1,6365 @@ +/* -*- c++ -*- + * File : vci_cc_vcache_wrapper.cpp + * Copyright (c) UPMC, Lip6, SoC + * Authors : Alain GREINER, Yang GAO + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Maintainers: cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr + */ + +#include +#include "arithmetics.h" +#include "../include/vci_cc_vcache_wrapper.h" + +#define DEBUG_DCACHE 1 +#define DEBUG_ICACHE 1 +#define DEBUG_CMD 0 + +namespace soclib { +namespace caba { + +namespace { +const char *icache_fsm_state_str[] = { + "ICACHE_IDLE", + + "ICACHE_XTN_TLB_FLUSH", + "ICACHE_XTN_CACHE_FLUSH", + "ICACHE_XTN_CACHE_FLUSH_GO", + "ICACHE_XTN_TLB_INVAL", + "ICACHE_XTN_CACHE_INVAL_VA", + "ICACHE_XTN_CACHE_INVAL_PA", + "ICACHE_XTN_CACHE_INVAL_GO", + + "ICACHE_TLB_WAIT", + + "ICACHE_MISS_SELECT", + "ICACHE_MISS_CLEAN", + "ICACHE_MISS_WAIT", + "ICACHE_MISS_DATA_UPDT", + "ICACHE_MISS_DIR_UPDT", + + "ICACHE_UNC_WAIT", + + "ICACHE_CC_CHECK", + "ICACHE_CC_UPDT", + "ICACHE_CC_INVAL", + }; + +const char *dcache_fsm_state_str[] = { + "DCACHE_IDLE", + + "DCACHE_TLB_MISS", + "DCACHE_TLB_PTE1_GET", + "DCACHE_TLB_PTE1_SELECT", + "DCACHE_TLB_PTE1_UPDT", + "DCACHE_TLB_PTE2_GET", + "DCACHE_TLB_PTE2_SELECT", + "DCACHE_TLB_PTE2_UPDT", + "DCACHE_TLB_LR_UPDT", + "DCACHE_TLB_LR_WAIT", + "DCACHE_TLB_RETURN", + + "DCACHE_XTN_SWITCH", + "DCACHE_XTN_SYNC", + "DCACHE_XTN_IC_INVAL_VA", + "DCACHE_XTN_IC_FLUSH", + "DCACHE_XTN_IC_INVAL_PA", + "DCACHE_XTN_IT_INVAL", + "DCACHE_XTN_DC_FLUSH", + "DCACHE_XTN_DC_FLUSH_GO", + "DCACHE_XTN_DC_INVAL_VA", + "DCACHE_XTN_DC_INVAL_PA", + "DCACHE_XTN_DC_INVAL_END", + "DCACHE_XTN_DC_INVAL_GO", + "DCACHE_XTN_DT_INVAL", + + "DCACHE_DIRTY_GET_PTE", + "DCACHE_DIRTY_WAIT", + + "DCACHE_MISS_SELECT", + "DCACHE_MISS_CLEAN", + "DCACHE_MISS_WAIT", + "DCACHE_MISS_DATA_UPDT", + "DCACHE_MISS_DIR_UPDT", + + "DCACHE_UNC_WAIT", + "DCACHE_LL_WAIT", + "DCACHE_SC_WAIT", + + "DCACHE_CC_CHECK", + "DCACHE_CC_UPDT", + "DCACHE_CC_INVAL", + + "DCACHE_INVAL_TLB_SCAN", + }; + +const char *cmd_fsm_state_str[] = { + "CMD_IDLE", + "CMD_INS_MISS", + "CMD_INS_UNC", + "CMD_DATA_MISS", + "CMD_DATA_UNC_READ", + "CMD_DATA_UNC_WRITE", + "CMD_DATA_WRITE", + "CMD_DATA_LL", + "CMD_DATA_SC", + "CMD_DATA_CAS", + }; + +const char *vci_pktid_type_str[] = { + "TYPE_DATA_UNC", + "TYPE_READ_DATA_MISS", + "TYPE_READ_INS_UNC", + "TYPE_READ_INS_MISS", + "TYPE_WRITE", + "TYPE_CAS", + "TYPE_LL", + "TYPE_SC", + }; + +const char *vci_cmd_type_str[] = { + "NOP or STORE_COND", + "READ", + "WRITE", + "LOCKED_READ" + }; + +const char *rsp_fsm_state_str[] = { + "RSP_IDLE", + "RSP_INS_MISS", + "RSP_INS_UNC", + "RSP_DATA_MISS", + "RSP_DATA_UNC", + "RSP_DATA_LL", + "RSP_DATA_WRITE", + }; + +const char *cc_receive_fsm_state_str[] = { + "CC_RECEIVE_IDLE", + "CC_RECEIVE_BRDCAST_HEADER", + "CC_RECEIVE_BRDCAST_NLINE", + "CC_RECEIVE_INS_INVAL_HEADER", + "CC_RECEIVE_INS_INVAL_NLINE", + "CC_RECEIVE_INS_UPDT_HEADER", + "CC_RECEIVE_INS_UPDT_NLINE", + "CC_RECEIVE_INS_UPDT_DATA", + "CC_RECEIVE_DATA_INVAL_HEADER", + "CC_RECEIVE_DATA_INVAL_NLINE", + "CC_RECEIVE_DATA_UPDT_HEADER", + "CC_RECEIVE_DATA_UPDT_NLINE", + "CC_RECEIVE_DATA_UPDT_DATA", + }; + +const char *cc_send_fsm_state_str[] = { + "CC_SEND_IDLE", + "CC_SEND_CLEANUP_1", + "CC_SEND_CLEANUP_2", + "CC_SEND_MULTI_ACK", + }; +} + +#define tmpl(...) \ + template __VA_ARGS__ \ + VciCcVCacheWrapper + +using namespace soclib::common; + +///////////////////////////////// +tmpl(/**/)::VciCcVCacheWrapper( + sc_module_name name, + const int proc_id, + const MappingTable &mtd, + const IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ) + : soclib::caba::BaseModule(name), + + p_clk("p_clk"), + p_resetn("p_resetn"), + p_vci("p_vci"), + p_dspin_m2p("p_dspin_m2p"), + p_dspin_p2m("p_dspin_p2m"), + p_dspin_clack("p_dspin_clack"), + + m_cacheability_table( mtd.getCacheabilityTable() ), + m_srcid( mtd.indexForId(srcid) ), + m_cc_global_id( cc_global_id ), + m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ), + m_itlb_ways( itlb_ways ), + m_itlb_sets( itlb_sets ), + m_dtlb_ways( dtlb_ways ), + m_dtlb_sets( dtlb_sets ), + m_icache_ways( icache_ways ), + m_icache_sets( icache_sets ), + m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ), + m_icache_words( icache_words ), + m_dcache_ways( dcache_ways ), + m_dcache_sets( dcache_sets ), + m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ), + m_dcache_words( dcache_words ), + m_x_width( x_width ), + m_y_width( y_width ), + m_proc_id( proc_id ), + m_max_frozen_cycles( max_frozen_cycles ), + m_paddr_nbits( vci_param::N ), + m_debug_start_cycle( debug_start_cycle ), + m_debug_ok( debug_ok ), + + r_mmu_ptpr("r_mmu_ptpr"), + r_mmu_mode("r_mmu_mode"), + r_mmu_word_lo("r_mmu_word_lo"), + r_mmu_word_hi("r_mmu_word_hi"), + r_mmu_ibvar("r_mmu_ibvar"), + r_mmu_dbvar("r_mmu_dbvar"), + r_mmu_ietr("r_mmu_ietr"), + r_mmu_detr("r_mmu_detr"), + + r_icache_fsm("r_icache_fsm"), + r_icache_fsm_save("r_icache_fsm_save"), + r_icache_vci_paddr("r_icache_vci_paddr"), + r_icache_vaddr_save("r_icache_vaddr_save"), + + r_icache_miss_way("r_icache_miss_way"), + r_icache_miss_set("r_icache_miss_set"), + r_icache_miss_word("r_icache_miss_word"), + r_icache_miss_inval("r_icache_miss_inval"), + r_icache_miss_clack("r_icache_miss_clack"), + + r_icache_cc_way("r_icache_cc_way"), + r_icache_cc_set("r_icache_cc_set"), + r_icache_cc_word("r_icache_cc_word"), + r_icache_cc_need_write("r_icache_cc_need_write"), + + r_icache_flush_count("r_icache_flush_count"), + + r_icache_miss_req("r_icache_miss_req"), + r_icache_unc_req("r_icache_unc_req"), + + r_icache_tlb_miss_req("r_icache_tlb_read_req"), + r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), + + r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"), + r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"), + + r_icache_cc_send_req("r_icache_cc_send_req"), + r_icache_cc_send_type("r_icache_cc_send_type"), + r_icache_cc_send_nline("r_icache_cc_send_nline"), + r_icache_cc_send_way("r_icache_cc_send_way"), + r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"), + + r_dcache_fsm("r_dcache_fsm"), + r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"), + r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), + + r_dcache_wbuf_req("r_dcache_wbuf_req"), + r_dcache_updt_req("r_dcache_updt_req"), + r_dcache_save_vaddr("r_dcache_save_vaddr"), + r_dcache_save_wdata("r_dcache_save_wdata"), + r_dcache_save_be("r_dcache_save_be"), + r_dcache_save_paddr("r_dcache_save_paddr"), + r_dcache_save_cache_way("r_dcache_save_cache_way"), + r_dcache_save_cache_set("r_dcache_save_cache_set"), + r_dcache_save_cache_word("r_dcache_save_cache_word"), + + r_dcache_dirty_paddr("r_dcache_dirty_paddr"), + r_dcache_dirty_way("r_dcache_dirty_way"), + r_dcache_dirty_set("r_dcache_dirty_set"), + + r_dcache_vci_paddr("r_dcache_vci_paddr"), + r_dcache_vci_wdata("r_dcache_vci_wdata"), + r_dcache_vci_miss_req("r_dcache_vci_miss_req"), + r_dcache_vci_unc_req("r_dcache_vci_unc_req"), + r_dcache_vci_unc_be("r_dcache_vci_unc_be"), + r_dcache_vci_unc_write("r_dcache_vci_unc_write"), + r_dcache_vci_cas_req("r_dcache_vci_cas_req"), + r_dcache_vci_cas_old("r_dcache_vci_cas_old"), + r_dcache_vci_cas_new("r_dcache_vci_cas_new"), + r_dcache_vci_ll_req("r_dcache_vci_ll_req"), + r_dcache_vci_sc_req("r_dcache_vci_sc_req"), + r_dcache_vci_sc_data("r_dcache_vci_sc_data"), + + r_dcache_xtn_way("r_dcache_xtn_way"), + r_dcache_xtn_set("r_dcache_xtn_set"), + + r_dcache_miss_type("r_dcache_miss_type"), + r_dcache_miss_word("r_dcache_miss_word"), + r_dcache_miss_way("r_dcache_miss_way"), + r_dcache_miss_set("r_dcache_miss_set"), + r_dcache_miss_inval("r_dcache_miss_inval"), + + r_dcache_cc_way("r_dcache_cc_way"), + r_dcache_cc_set("r_dcache_cc_set"), + r_dcache_cc_word("r_dcache_cc_word"), + r_dcache_cc_need_write("r_dcache_cc_need_write"), + + r_dcache_flush_count("r_dcache_flush_count"), + + r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"), + + r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"), + r_dcache_tlb_ins("r_dcache_tlb_ins"), + r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), + r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), + r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), + r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), + r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), + r_dcache_tlb_way("r_dcache_tlb_way"), + r_dcache_tlb_set("r_dcache_tlb_set"), + + r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"), + r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"), + + r_dcache_xtn_req("r_dcache_xtn_req"), + r_dcache_xtn_opcode("r_dcache_xtn_opcode"), + + r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), + r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), + + r_dcache_cc_send_req("r_dcache_cc_send_req"), + r_dcache_cc_send_type("r_dcache_cc_send_type"), + r_dcache_cc_send_nline("r_dcache_cc_send_nline"), + r_dcache_cc_send_way("r_dcache_cc_send_way"), + r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"), + + r_vci_cmd_fsm("r_vci_cmd_fsm"), + r_vci_cmd_min("r_vci_cmd_min"), + r_vci_cmd_max("r_vci_cmd_max"), + r_vci_cmd_cpt("r_vci_cmd_cpt"), + r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"), + + r_vci_rsp_fsm("r_vci_rsp_fsm"), + r_vci_rsp_cpt("r_vci_rsp_cpt"), + r_vci_rsp_ins_error("r_vci_rsp_ins_error"), + r_vci_rsp_data_error("r_vci_rsp_data_error"), + r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth + r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth + + r_cc_send_fsm("r_cc_send_fsm"), + r_cc_send_last_client("r_cc_send_last_client"), + + r_cc_receive_fsm("r_cc_receive_fsm"), + r_cc_receive_data_ins("r_cc_receive_data_ins"), + r_cc_receive_word_idx("r_cc_receive_word_idx"), + r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth + r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth + r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth + + r_cc_receive_icache_req("r_cc_receive_icache_req"), + r_cc_receive_icache_type("r_cc_receive_icache_type"), + r_cc_receive_icache_way("r_cc_receive_icache_way"), + r_cc_receive_icache_set("r_cc_receive_icache_set"), + r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"), + r_cc_receive_icache_nline("r_cc_receive_icache_nline"), + + r_cc_receive_dcache_req("r_cc_receive_dcache_req"), + r_cc_receive_dcache_type("r_cc_receive_dcache_type"), + r_cc_receive_dcache_way("r_cc_receive_dcache_way"), + r_cc_receive_dcache_set("r_cc_receive_dcache_set"), + r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"), + r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"), + + r_iss(this->name(), proc_id), + r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ), + r_icache("icache", icache_ways, icache_sets, icache_words), + r_dcache("dcache", dcache_ways, dcache_sets, dcache_words), + r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N), + r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N) +{ + std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl; + + assert( ((icache_words*vci_param::B) < (1< 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and + "Need more TRDID bits."); + + assert( (icache_words == dcache_words) and + "icache_words and dcache_words parameters must be equal"); + + assert( (itlb_sets == dtlb_sets) and + "itlb_sets and dtlb_sets parameters must be etqual"); + + assert( (itlb_ways == dtlb_ways) and + "itlb_ways and dtlb_ways parameters must be etqual"); + + r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | + (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | + (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | + (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | + (uint32_log2(m_icache_words<<2)); + + r_mmu_release = (uint32_t)(1 << 16) | 0x1; + + r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; + r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + typename iss_t::CacheInfo cache_info; + cache_info.has_mmu = true; + cache_info.icache_line_size = icache_words*sizeof(uint32_t); + cache_info.icache_assoc = icache_ways; + cache_info.icache_n_lines = icache_sets; + cache_info.dcache_line_size = dcache_words*sizeof(uint32_t); + cache_info.dcache_assoc = dcache_ways; + cache_info.dcache_n_lines = dcache_sets; + r_iss.setCacheInfo(cache_info); +} + +///////////////////////////////////// +tmpl(/**/)::~VciCcVCacheWrapper() +///////////////////////////////////// +{ + delete [] r_dcache_in_tlb; + delete [] r_dcache_contains_ptd; +} + +//////////////////////// +tmpl(void)::print_cpi() +//////////////////////// +{ + std::cout << name() << " CPI = " + << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ; +} + +//////////////////////////////////// +tmpl(void)::print_trace(size_t mode) +//////////////////////////////////// +{ + // b0 : write buffer trace + // b1 : write buffer verbose + // b2 : dcache trace + // b3 : icache trace + // b4 : dtlb trace + // b5 : itlb trace + + std::cout << std::dec << "PROC " << name() << std::endl; + + std::cout << " " << m_ireq << std::endl; + std::cout << " " << m_irsp << std::endl; + std::cout << " " << m_dreq << std::endl; + std::cout << " " << m_drsp << std::endl; + + std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] + << " | " << dcache_fsm_state_str[r_dcache_fsm.read()] + << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()] + << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] + << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()] + << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] + << " | MMU = " << r_mmu_mode.read(); + if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; + if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; + std::cout << std::endl; + + if(mode & 0x01) + { + r_wbuf.printTrace((mode>>1)&1); + } + if(mode & 0x04) + { + std::cout << " Data Cache" << std::endl; + r_dcache.printTrace(); + } + if(mode & 0x08) + { + std::cout << " Instruction Cache" << std::endl; + r_icache.printTrace(); + } + if(mode & 0x10) + { + std::cout << " Data TLB" << std::endl; + r_dtlb.printTrace(); + } + if(mode & 0x20) + { + std::cout << " Instruction TLB" << std::endl; + r_itlb.printTrace(); + } +} + +////////////////////////////////////////// +tmpl(void)::cache_monitor( paddr_t addr ) +////////////////////////////////////////// +{ + bool cache_hit; + size_t cache_way = 0; + size_t cache_set = 0; + size_t cache_word = 0; + uint32_t cache_rdata = 0; + + cache_hit = r_dcache.read_neutral( addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word ); + + if ( cache_hit != m_debug_previous_d_hit ) + { + std::cout << "Monitor PROC " << name() + << " DCACHE at cycle " << std::dec << m_cpt_total_cycles + << " / HIT = " << cache_hit + << " / PADDR = " << std::hex << addr + << " / DATA = " << cache_rdata + << " / WAY = " << cache_way << std::endl; + m_debug_previous_d_hit = cache_hit; + } + + cache_hit = r_icache.read_neutral( addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word ); + + if ( cache_hit != m_debug_previous_i_hit ) + { + std::cout << "Monitor PROC " << name() + << " ICACHE at cycle " << std::dec << m_cpt_total_cycles + << " / HIT = " << cache_hit + << " / PADDR = " << std::hex << addr + << " / DATA = " << cache_rdata + << " / WAY = " << cache_way << std::endl; + m_debug_previous_i_hit = cache_hit; + } +} + +/* +//////////////////////// +tmpl(void)::print_stats() +//////////////////////// +{ + float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); + std::cout << name() << std::endl + << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl + << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl + << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl + << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl + << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl + << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl + << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl + << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl + << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl + << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl + << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl + << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl + << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl + << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl + << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl + << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl + << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl + << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl + << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl + << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl + << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl + << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl + << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl + << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl + << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl + << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl + << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl + << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl + << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl + << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl + << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl + << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl + << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl + << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl + << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl + << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl + << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl + << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl + << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; +} + +//////////////////////// +tmpl(void)::clear_stats() +//////////////////////// +{ + m_cpt_dcache_data_read = 0; + m_cpt_dcache_data_write = 0; + m_cpt_dcache_dir_read = 0; + m_cpt_dcache_dir_write = 0; + m_cpt_icache_data_read = 0; + m_cpt_icache_data_write = 0; + m_cpt_icache_dir_read = 0; + m_cpt_icache_dir_write = 0; + + m_cpt_frz_cycles = 0; + m_cpt_dcache_frz_cycles = 0; + m_cpt_total_cycles = 0; + + m_cpt_read = 0; + m_cpt_write = 0; + m_cpt_data_miss = 0; + m_cpt_ins_miss = 0; + m_cpt_unc_read = 0; + m_cpt_write_cached = 0; + m_cpt_ins_read = 0; + + m_cost_write_frz = 0; + m_cost_data_miss_frz = 0; + m_cost_unc_read_frz = 0; + m_cost_ins_miss_frz = 0; + + m_cpt_imiss_transaction = 0; + m_cpt_dmiss_transaction = 0; + m_cpt_unc_transaction = 0; + m_cpt_write_transaction = 0; + m_cpt_icache_unc_transaction = 0; + + m_cost_imiss_transaction = 0; + m_cost_dmiss_transaction = 0; + m_cost_unc_transaction = 0; + m_cost_write_transaction = 0; + m_cost_icache_unc_transaction = 0; + m_length_write_transaction = 0; + + m_cpt_ins_tlb_read = 0; + m_cpt_ins_tlb_miss = 0; + m_cpt_ins_tlb_update_acc = 0; + + m_cpt_data_tlb_read = 0; + m_cpt_data_tlb_miss = 0; + m_cpt_data_tlb_update_acc = 0; + m_cpt_data_tlb_update_dirty = 0; + m_cpt_ins_tlb_hit_dcache = 0; + m_cpt_data_tlb_hit_dcache = 0; + m_cpt_ins_tlb_occup_cache = 0; + m_cpt_data_tlb_occup_cache = 0; + + m_cost_ins_tlb_miss_frz = 0; + m_cost_data_tlb_miss_frz = 0; + m_cost_ins_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_dirty_frz = 0; + m_cost_ins_tlb_occup_cache_frz = 0; + m_cost_data_tlb_occup_cache_frz = 0; + + m_cpt_itlbmiss_transaction = 0; + m_cpt_itlb_ll_transaction = 0; + m_cpt_itlb_sc_transaction = 0; + m_cpt_dtlbmiss_transaction = 0; + m_cpt_dtlb_ll_transaction = 0; + m_cpt_dtlb_sc_transaction = 0; + m_cpt_dtlb_ll_dirty_transaction = 0; + m_cpt_dtlb_sc_dirty_transaction = 0; + + m_cost_itlbmiss_transaction = 0; + m_cost_itlb_ll_transaction = 0; + m_cost_itlb_sc_transaction = 0; + m_cost_dtlbmiss_transaction = 0; + m_cost_dtlb_ll_transaction = 0; + m_cost_dtlb_sc_transaction = 0; + m_cost_dtlb_ll_dirty_transaction = 0; + m_cost_dtlb_sc_dirty_transaction = 0; + + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; + m_cpt_cc_broadcast = 0; + + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; +} + +*/ + +///////////////////////// +tmpl(void)::transition() +///////////////////////// +{ + if ( not p_resetn.read() ) + { + r_iss.reset(); + r_wbuf.reset(); + r_icache.reset(); + r_dcache.reset(); + r_itlb.reset(); + r_dtlb.reset(); + + r_dcache_fsm = DCACHE_IDLE; + r_icache_fsm = ICACHE_IDLE; + r_vci_cmd_fsm = CMD_IDLE; + r_vci_rsp_fsm = RSP_IDLE; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + r_cc_send_fsm = CC_SEND_IDLE; + + // reset data physical address extension + r_dcache_paddr_ext = 0; + + // reset dcache directory extension + for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) + { + r_dcache_in_tlb[i] = false; + r_dcache_contains_ptd[i] = false; + } + + // Response FIFOs and cleanup buffer + r_vci_rsp_fifo_icache.init(); + r_vci_rsp_fifo_dcache.init(); + + // ICACHE & DCACHE activated + // ITLB & DTLB desactivated + r_mmu_mode = 0x3; + + // No request from ICACHE FSM to CMD FSM + r_icache_miss_req = false; + r_icache_unc_req = false; + + // No request from ICACHE_FSM to DCACHE FSM + r_icache_tlb_miss_req = false; + + // No request from ICACHE_FSM to CC_SEND FSM + r_icache_cc_send_req = false; + r_icache_cleanup_victim_req = false; + + r_icache_clack_req = false; + + // No pending write in pipeline + r_dcache_wbuf_req = false; + r_dcache_updt_req = false; + + // No request from DCACHE_FSM to CMD_FSM + r_dcache_vci_miss_req = false; + r_dcache_vci_unc_req = false; + r_dcache_vci_cas_req = false; + r_dcache_vci_ll_req = false; + r_dcache_vci_sc_req = false; + + // No processor XTN request pending + r_dcache_xtn_req = false; + + // No request from DCACHE FSM to CC_SEND FSM + r_dcache_cc_send_req = false; + r_dcache_cleanup_victim_req = false; + + r_dcache_clack_req = false; + + // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs + r_cc_receive_icache_req = false; + r_cc_receive_dcache_req = false; + + // last cc_send client was dcache + r_cc_send_last_client = false; + + // No pending cleanup after a replacement + r_icache_miss_clack = false; + r_dcache_miss_clack = false; + + // No signalisation of a coherence request matching a pending miss + r_icache_miss_inval = false; + r_dcache_miss_inval = false; + + r_dspin_clack_req = false; + + // No signalisation of errors + r_vci_rsp_ins_error = false; + r_vci_rsp_data_error = false; + + // Debug variables + m_debug_previous_i_hit = false; + m_debug_previous_d_hit = false; + m_debug_activated = false; + + // activity counters + m_cpt_dcache_data_read = 0; + m_cpt_dcache_data_write = 0; + m_cpt_dcache_dir_read = 0; + m_cpt_dcache_dir_write = 0; + m_cpt_icache_data_read = 0; + m_cpt_icache_data_write = 0; + m_cpt_icache_dir_read = 0; + m_cpt_icache_dir_write = 0; + + m_cpt_frz_cycles = 0; + m_cpt_total_cycles = 0; + m_cpt_stop_simulation = 0; + + m_cpt_data_miss = 0; + m_cpt_ins_miss = 0; + m_cpt_unc_read = 0; + m_cpt_write_cached = 0; + m_cpt_ins_read = 0; + + m_cost_write_frz = 0; + m_cost_data_miss_frz = 0; + m_cost_unc_read_frz = 0; + m_cost_ins_miss_frz = 0; + + m_cpt_imiss_transaction = 0; + m_cpt_dmiss_transaction = 0; + m_cpt_unc_transaction = 0; + m_cpt_write_transaction = 0; + m_cpt_icache_unc_transaction = 0; + + m_cost_imiss_transaction = 0; + m_cost_dmiss_transaction = 0; + m_cost_unc_transaction = 0; + m_cost_write_transaction = 0; + m_cost_icache_unc_transaction = 0; + m_length_write_transaction = 0; + + m_cpt_ins_tlb_read = 0; + m_cpt_ins_tlb_miss = 0; + m_cpt_ins_tlb_update_acc = 0; + + m_cpt_data_tlb_read = 0; + m_cpt_data_tlb_miss = 0; + m_cpt_data_tlb_update_acc = 0; + m_cpt_data_tlb_update_dirty = 0; + m_cpt_ins_tlb_hit_dcache = 0; + m_cpt_data_tlb_hit_dcache = 0; + m_cpt_ins_tlb_occup_cache = 0; + m_cpt_data_tlb_occup_cache = 0; + + m_cost_ins_tlb_miss_frz = 0; + m_cost_data_tlb_miss_frz = 0; + m_cost_ins_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_dirty_frz = 0; + m_cost_ins_tlb_occup_cache_frz = 0; + m_cost_data_tlb_occup_cache_frz = 0; + + m_cpt_ins_tlb_inval = 0; + m_cpt_data_tlb_inval = 0; + m_cost_ins_tlb_inval_frz = 0; + m_cost_data_tlb_inval_frz = 0; + + m_cpt_cc_broadcast = 0; + + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; + + m_cpt_itlbmiss_transaction = 0; + m_cpt_itlb_ll_transaction = 0; + m_cpt_itlb_sc_transaction = 0; + m_cpt_dtlbmiss_transaction = 0; + m_cpt_dtlb_ll_transaction = 0; + m_cpt_dtlb_sc_transaction = 0; + m_cpt_dtlb_ll_dirty_transaction = 0; + m_cpt_dtlb_sc_dirty_transaction = 0; + + m_cost_itlbmiss_transaction = 0; + m_cost_itlb_ll_transaction = 0; + m_cost_itlb_sc_transaction = 0; + m_cost_dtlbmiss_transaction = 0; + m_cost_dtlb_ll_transaction = 0; + m_cost_dtlb_sc_transaction = 0; + m_cost_dtlb_ll_dirty_transaction = 0; + m_cost_dtlb_sc_dirty_transaction = 0; +/* + m_cpt_dcache_frz_cycles = 0; + m_cpt_read = 0; + m_cpt_write = 0; + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; +*/ + + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0; + + // init the llsc reservation buffer + r_dcache_llsc_valid = false; + m_monitor_ok = false; + + return; + } + + // Response FIFOs default values + bool vci_rsp_fifo_icache_get = false; + bool vci_rsp_fifo_icache_put = false; + uint32_t vci_rsp_fifo_icache_data = 0; + + bool vci_rsp_fifo_dcache_get = false; + bool vci_rsp_fifo_dcache_put = false; + uint32_t vci_rsp_fifo_dcache_data = 0; + + // updt fifo + bool cc_receive_updt_fifo_get = false; + bool cc_receive_updt_fifo_put = false; + uint32_t cc_receive_updt_fifo_be = 0; + uint32_t cc_receive_updt_fifo_data = 0; + bool cc_receive_updt_fifo_eop = false; + +#ifdef INSTRUMENTATION + m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; + m_cpt_fsm_icache [r_icache_fsm.read() ] ++; + m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++; + m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++; + m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++; + m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++; +#endif + + m_cpt_total_cycles++; + + m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; + + ///////////////////////////////////////////////////////////////////// + // Get data and instruction requests from processor + /////////////////////////////////////////////////////////////////////// + + r_iss.getRequests(m_ireq, m_dreq); + + //////////////////////////////////////////////////////////////////////////////////// + // ICACHE_FSM + // + // 1/ Coherence operations + // They are handled as interrupts generated by the CC_RECEIVE FSM. + // - There is a coherence request when r_tgt_icache_req is set. + // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states. + // - There is a cleanup ack request when r_cleanup_icache_req is set. + // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, + // MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states. + // - For both types of requests, actions associated to the pre-empted state + // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK + // or CC_CLACK) to execute the requested coherence operation, and returns + // to the pre-empted state. + // + // 2/ Processor requests + // They are taken in IDLE state only. In case of cache miss, or uncacheable + // instruction, the ICACHE FSM request a VCI transaction to CMD FSM, + // using the r_icache_miss_req or r_icache_unc_req flip-flops. These + // flip-flops are reset when the transaction starts. + // - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state + // to select a slot and possibly request a cleanup transaction to the CC_SEND FSM. + // It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM, + // The availability of the missing cache line is signaled by the response fifo, + // and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT + // and ICACHE_MISS_DIR_UPDT states. + // - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT + // to wait the response from the RSP FSM, through the response fifo. + // The missing instruction is directly returned to processor in this state. + // + // 3/ TLB miss + // In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the + // ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr + // register, and goes to the ICACHE_TLB_WAIT state. + // The tlb update is entirely done by the DCACHE FSM (who becomes the owner + // of ITLB until the update is completed, and reset r_icache_tlb_miss_req + // to signal the completion. + // + // 4/ XTN requests + // The DCACHE FSM signals XTN processor requests to ICACHE_FSM + // using the r_dcache_xtn_req flip-flop. + // The request opcode and the address to be invalidated are transmitted + // in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively. + // The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation + // is completed. + // + // 5/ Error Handling + // The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error + // in a cache miss or uncacheable read VCI transaction. Nothing is written + // in the response fifo. This flip-flop is reset by the ICACHE-FSM. + //////////////////////////////////////////////////////////////////////////////////////// + + // default value for m_irsp + m_irsp.valid = false; + m_irsp.error = false; + m_irsp.instruction = 0; + + switch( r_icache_fsm.read() ) + { + ///////////////// + case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests, + // and coherence requests with a fixed priority: + // 1/ Coherence requests => ICACHE_CC_CHECK + // 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_* + // 3/ tlb miss => ICACHE_TLB_WAIT + // 4/ cacheable read miss => ICACHE_MISS_SELECT + // 5/ uncacheable read miss => ICACHE_UNC_REQ + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // XTN requests sent by DCACHE FSM + // These request are not executed in this IDLE state, because + // they require access to icache or itlb, that are already accessed + if ( r_dcache_xtn_req.read() ) + { + if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) + { + r_icache_fsm = ICACHE_XTN_TLB_FLUSH; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH) + { + r_icache_flush_count = 0; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) + { + r_icache_fsm = ICACHE_XTN_TLB_INVAL; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) + { + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) + { + if (sizeof(paddr_t) <= 32) + { + assert(r_mmu_word_hi.read() == 0 && + "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); + r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); + } + else + { + r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | + (paddr_t)r_mmu_word_lo.read(); + } + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else + { + assert( false and + "undefined XTN request received by ICACHE FSM"); + } + break; + } // end if xtn_req + + // processor request + if ( m_ireq.valid ) + { + bool cacheable; + paddr_t paddr; + bool tlb_hit = false; + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline; + uint32_t cache_inst = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + int cache_state = CACHE_SLOT_STATE_EMPTY; + + // We register processor request + r_icache_vaddr_save = m_ireq.addr; + + // sytematic itlb access (if activated) + if ( r_mmu_mode.read() & INS_TLB_MASK ) + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + tlb_hit = r_itlb.translate( m_ireq.addr, + &paddr, + &tlb_flags, + &tlb_nline, // unused + &tlb_way, // unused + &tlb_set ); // unused + } + else + { + paddr = (paddr_t)m_ireq.addr; + } + + // systematic icache access (if activated) + if ( r_mmu_mode.read() & INS_CACHE_MASK ) + { + + +#ifdef INSTRUMENTATION +m_cpt_icache_data_read++; +m_cpt_icache_dir_read++; +#endif + r_icache.read( paddr, + &cache_inst, + &cache_way, + &cache_set, + &cache_word, + &cache_state ); + } + + // We compute cacheability and check access rights: + // - If MMU activated : cacheability is defined by the C bit in the PTE, + // and the access rights are defined by the U and X bits in the PTE. + // - If MMU not activated : cacheability is defined by the segment table, + // and there is no access rights checking + + if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: + { + // cacheability + if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; + else cacheable = m_cacheability_table[(uint64_t)m_ireq.addr]; + } + else // itlb activated + { + if ( tlb_hit ) // ITLB hit + { + // cacheability + if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; + else cacheable = tlb_flags.c; + + // access rights checking + if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) ) + { + r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; + break; + } + else if ( not tlb_flags.x ) + { + r_mmu_ietr = MMU_READ_EXEC_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; + break; + } + } + else // ITLB miss + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_miss++; +#endif + r_icache_fsm = ICACHE_TLB_WAIT; + r_icache_tlb_miss_req = true; + break; + } + } // end if itlb activated + + // physical address registration + r_icache_vci_paddr = paddr; + + // Finally, we send the response to processor, and compute next state + if ( cacheable ) + { + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss + { + +#ifdef INSTRUMENTATION +m_cpt_icache_miss++; +#endif + // we request a VCI transaction + r_icache_fsm = ICACHE_MISS_SELECT; +#if DEBUG_ICACHE +if ( m_debug_activated ) +std::cout << " READ MISS in icache" + << " : PADDR = " << std::hex << paddr << std::endl; +#endif + r_icache_miss_req = true; + } + else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_icache_fsm = ICACHE_IDLE; + } + else // cache hit + { + +#ifdef INSTRUMENTATION +m_cpt_ins_read++; +#endif + // return instruction to processor + m_irsp.valid = true; + m_irsp.instruction = cache_inst; + r_icache_fsm = ICACHE_IDLE; +#if DEBUG_ICACHE +if ( m_debug_activated ) +std::cout << " READ HIT in icache" + << " : PADDR = " << std::hex << paddr << std::endl; +#endif + } + } + else // non cacheable read + { + r_icache_unc_req = true; + r_icache_fsm = ICACHE_UNC_WAIT; + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " READ UNCACHEABLE in icache" + << " : PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + } // end if m_ireq.valid + break; + } + ///////////////////// + case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss + // the itlb is udated by the DCACHE FSM, as well as the + // r_mmu_ietr and r_mmu_ibvar registers in case of error. + // the itlb is not accessed by ICACHE FSM until DCACHE FSM + // reset the r_icache_tlb_miss_req flip-flop + // external coherence request are accepted in this state. + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++; + + // DCACHE FSM signals response by reseting the request flip-flop + if ( not r_icache_tlb_miss_req.read() ) + { + if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated + { + r_icache_tlb_rsp_error = false; + m_irsp.error = true; + m_irsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + else // tlb updated : return to IDLE state + { + r_icache_fsm = ICACHE_IDLE; + } + } + break; + } + ////////////////////////// + case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries + { + r_itlb.flush(); + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + break; + } + //////////////////////////// + case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using + // r_icache_flush_count as a slot counter, + // looping in this state until all slots are visited. + // It can require two cycles per slot: + // We test here the slot state, and make the actual inval + // (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state. + // A cleanup request is generated for each valid line + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_icache_flush_count.read()/m_icache_sets; + size_t set = r_icache_flush_count.read()%m_icache_sets; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_dir( way, + set, + &tag, + &state ); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval required + { + // request cleanup + r_icache_cc_send_req = true; + r_icache_cc_send_nline = tag * m_icache_sets + set; + r_icache_cc_send_way = way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + + // goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval + r_icache_miss_way = way; + r_icache_miss_set = set; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO; + } + else if ( r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1) ) // last slot + { + r_dcache_xtn_req = false; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + + // saturation counter, to have the same last slot condition + // in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states + if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) ) + { + r_icache_flush_count = r_icache_flush_count.read() + 1; + } + } + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush + { + size_t way = r_icache_miss_way.read(); + size_t set = r_icache_miss_set.read(); + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + + r_icache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + if ( r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1) ) // last slot + { + r_dcache_xtn_req = false; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + else + { + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + } + break; + } + + ////////////////////////// + case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address + // stored in the r_dcache_save_wdata register + { + r_itlb.inval(r_dcache_save_wdata.read()); + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address + // requires 3 cycles (in case of hit on itlb and icache). + // In this state, access TLB to translate virtual address + // stored in the r_dcache_save_wdata register. + { + paddr_t paddr; + bool hit; + + // read physical address in TLB when MMU activated + if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + hit = r_itlb.translate(r_dcache_save_wdata.read(), + &paddr); + } + else // itlb not activated + { + paddr = (paddr_t)r_dcache_save_wdata.read(); + hit = true; + } + + if ( hit ) // continue the selective inval process + { + r_icache_vci_paddr = paddr; + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else // miss : send a request to DCACHE FSM + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_miss++; +#endif + r_icache_tlb_miss_req = true; + r_icache_vaddr_save = r_dcache_save_wdata.read(); + r_icache_fsm = ICACHE_TLB_WAIT; + } + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address + // require 2 cycles. In this state, we read directory + // with address stored in r_icache_vci_paddr register. + { + int state; + size_t way; + size_t set; + size_t word; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_dir(r_icache_vci_paddr.read(), + &state, + &way, + &set, + &word); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + { + r_icache_miss_way = way; + r_icache_miss_set = set; + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; + } + else // miss : acknowlege the XTN request and return + { + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + } + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval + { + if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent + { + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI ); + + // request cleanup + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_way = r_icache_miss_way.read(); + r_icache_cc_send_type = CC_TYPE_CLEANUP; + + // acknowledge the XTN request and return + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + } + break; + } + //////////////////////// + case ICACHE_MISS_SELECT: // Try to select a slot in associative set, + // Waiting in this state if no slot available. + // If a victim slot has been choosen and the r_icache_cc_send_req is false, + // we send the cleanup request in this state. + // If not, a r_icache_cleanup_victim_req flip-flop is + // utilized for saving this cleanup request, and it will be sent later + // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. + // The r_icache_miss_clack flip-flop is set + // when a cleanup is required + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + + bool found; + bool cleanup; + size_t way; + size_t set; + paddr_t victim; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_select(r_icache_vci_paddr.read(), + &victim, + &way, + &set, + &found, + &cleanup ); + if ( not found ) + { + break; + } + else + { + r_icache_miss_way = way; + r_icache_miss_set = set; + + if ( cleanup ) + { + if ( not r_icache_cc_send_req.read() ) + { + r_icache_cc_send_req = true; + r_icache_cc_send_nline = victim; + r_icache_cc_send_way = way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + } + else + { + r_icache_cleanup_victim_req = true; + r_icache_cleanup_victim_nline = victim; + } + + r_icache_miss_clack = true; + r_icache_fsm = ICACHE_MISS_CLEAN; + } + else + { + r_icache_fsm = ICACHE_MISS_WAIT; + } + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set; + if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl; + else std::cout << std::endl; +} +#endif + } + break; + } + /////////////////////// + case ICACHE_MISS_CLEAN: // switch the slot to zombi state + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Switch to ZOMBI state" << std::dec + << " / WAY = " << r_icache_miss_way.read() + << " / SET = " << r_icache_miss_set.read() << std::endl; +} +#endif + + r_icache_fsm = ICACHE_MISS_WAIT; + break; + } + ////////////////////// + case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + + // send cleanup victim request + if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + { + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_cleanup_victim_nline; + r_icache_cc_send_way = r_icache_miss_way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cleanup_victim_req = false; + } + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( r_vci_rsp_ins_error.read() ) // bus error + { + r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_ibvar = r_icache_vaddr_save.read(); + m_irsp.valid = true; + m_irsp.error = true; + r_vci_rsp_ins_error = false; + r_icache_fsm = ICACHE_IDLE; + } + else if ( r_vci_rsp_fifo_icache.rok() ) // response available + { + r_icache_miss_word = 0; + r_icache_fsm = ICACHE_MISS_DATA_UPDT; + } + break; + } + /////////////////////////// + case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) + { + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + + if ( r_vci_rsp_fifo_icache.rok() ) // response available + { + +#ifdef INSTRUMENTATION +m_cpt_icache_data_write++; +#endif + r_icache.write( r_icache_miss_way.read(), + r_icache_miss_set.read(), + r_icache_miss_word.read(), + r_vci_rsp_fifo_icache.read() ); +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Write one word:" + << " WDATA = " << r_vci_rsp_fifo_icache.read() + << " WAY = " << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() + << " WORD = " << r_icache_miss_word.read() << std::endl; +} +#endif + vci_rsp_fifo_icache_get = true; + r_icache_miss_word = r_icache_miss_word.read() + 1; + + if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word + { + r_icache_fsm = ICACHE_MISS_DIR_UPDT; + } + } + break; + } + ////////////////////////// + case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted, + // and the cleanup ack has not been received, + // as indicated by r_icache_miss_clack. + // - If no matching coherence request (r_icache_miss_inval) + // switch directory slot to VALID state. + // - If matching coherence request, switch directory slot + // to ZOMBI state, and send a cleanup request. + { + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + + // send cleanup victim request + if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + { + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_cleanup_victim_nline; + r_icache_cc_send_way = r_icache_miss_way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cleanup_victim_req = false; + } + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line + { + if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup + { + if ( not r_icache_cc_send_req.read() ) + { + r_icache_miss_inval = false; + // request cleanup + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_way = r_icache_miss_way.read(); + r_icache_cc_send_type = CC_TYPE_CLEANUP; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI ); +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Switch cache slot to ZOMBI state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; +} +#endif + } + else + break; + } + else // Switch slot to VALID state + { + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_VALID ); +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Switch cache slot to VALID state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; +} +#endif + } + + r_icache_fsm = ICACHE_IDLE; + } + break; + } + //////////////////// + case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( r_vci_rsp_ins_error.read() ) // bus error + { + r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_ibvar = m_ireq.addr; + r_vci_rsp_ins_error = false; + m_irsp.valid = true; + m_irsp.error = true; + r_icache_fsm = ICACHE_IDLE; + } + else if (r_vci_rsp_fifo_icache.rok() ) // instruction available + { + vci_rsp_fifo_icache_get = true; + r_icache_fsm = ICACHE_IDLE; + if ( m_ireq.valid and + (m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified + { + m_irsp.valid = true; + m_irsp.instruction = r_vci_rsp_fifo_icache.read(); + } + } + break; + } + ///////////////////// + case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm + // handling coherence requests. + // if there is a matching pending miss, it is + // signaled in the r_icache_miss_inval flip-flop. + // The return state is defined in r_icache_fsm_save. + { + paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4; + paddr_t mask = ~((m_icache_words<<2)-1); + + // CLACK handler + // We switch the directory slot to EMPTY state + // and reset r_icache_miss_clack if the cleanup ack + // is matching a pending miss. + if ( r_icache_clack_req.read() ) + { + + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( 0, + r_icache_clack_way.read(), + r_icache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read()) ) + { + r_icache_miss_clack = false; + } + + r_icache_clack_req = false; + + // return to cc_save state + r_icache_fsm = r_icache_fsm_save.read(); + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " CC_TYPE_CLACK slot returns to empty state" + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; +} +#endif + + break; + } + + assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); + + // Match between MISS address and CC address + if (r_cc_receive_icache_req.read() and + ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and + ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching + { + // signaling the matching + r_icache_miss_inval = true; + + // in case of update, go to CC_UPDT + // JUST TO POP THE FIFO + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_icache_cc_need_write = false; + } + // the request is dealt with + else + { + r_cc_receive_icache_req = false; + r_icache_fsm = r_icache_fsm_save.read(); + } +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + + // CC request handler + + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_dir(paddr, + &state, + &way, + &set, + &word); + + r_icache_cc_way = way; + r_icache_cc_set = set; + + if ( state == CACHE_SLOT_STATE_VALID) // hit + { + // need to update the cache state + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update + { + r_icache_cc_need_write = true; + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + } + else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval + { + r_icache_fsm = ICACHE_CC_INVAL; + } + } + else // miss + { + // multicast acknowledgement required in case of update + if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_icache_cc_need_write = false; + } + else // No response needed + { + r_cc_receive_icache_req = false; + r_icache_fsm = r_icache_fsm_save.read(); + } + } + break; + } + ///////////////////// + case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state + { + assert (not r_icache_cc_send_req.read() && + "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req " + "must not be set"); + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + + // Switch slot state to ZOMBI and send CLEANUP command + r_icache.write_dir( r_icache_cc_way.read(), + r_icache_cc_set.read(), + CACHE_SLOT_STATE_ZOMBI ); + + // coherence request completed + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); + r_icache_cc_send_way = r_icache_cc_way.read(); + r_icache_cc_send_type = CC_TYPE_CLEANUP; + + r_icache_fsm = r_icache_fsm_save.read(); + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ +std::cout << " slot returns to ZOMBI state" + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() << std::endl; +} +#endif + + break; + } + //////////////////// + case ICACHE_CC_UPDT: // hit update : write one word per cycle + { + assert (not r_icache_cc_send_req.read() && + "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req " + "must not be set"); + + if ( not r_cc_receive_updt_fifo_be.rok() ) break; + + + size_t word = r_icache_cc_word.read(); + size_t way = r_icache_cc_way.read(); + size_t set = r_icache_cc_set.read(); + + if (r_icache_cc_need_write.read()) + { + r_icache.write( way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read() ); + + r_icache_cc_word = word+1; + +#ifdef INSTRUMENTATION +m_cpt_icache_data_write++; +#endif + +#if DEBUG_ICACHE +if ( m_debug_activated ) +{ + std::cout << " Write one word " + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() + << " / word = " << r_icache_cc_word.read() << std::endl; +} +#endif + } + + if ( r_cc_receive_updt_fifo_eop.read() ) // last word + { + // no need to write in the cache anymore + r_icache_cc_need_write = false; + + // coherence request completed + r_cc_receive_icache_req = false; + + // request multicast acknowledgement + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); + r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); + r_icache_cc_send_type = CC_TYPE_MULTI_ACK; + + r_icache_fsm = r_icache_fsm_save.read(); + } + //consume fifo if not eop + cc_receive_updt_fifo_get = true; + + break; + } + + } // end switch r_icache_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // DCACHE FSM + // + // 1/ Coherence operations + // They are handled as interrupts generated by the CC_RECEIVE FSM. + // - There is a coherence request when r_tgt_dcache_req is set. + // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT + // and SC_WAIT states. + // - There is a cleanup acknowledge request when r_cleanup_dcache_req is set. + // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT, + // MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states. + // - For both types of requests, actions associated to the pre-empted state + // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK + // or CC_CLACK) to execute the requested coherence operation, and returns + // to the pre-empted state. + // + // 2/ TLB miss + // The page tables are generally cacheable. + // In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated + // sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE, + // this sub-fsm implement the table-walk... + // + // 3/ processor requests + // Processor requests are taken in IDLE state only. + // The IDLE state implements a two stages pipe-line to handle write bursts: + // - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid). + // - The registration in wbuf and the dcache update is done in stage P1 + // (if the processor request is a write). + // The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define + // the operations that must be done in P1 stage, and the access type + // (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req. + // READ requests are delayed if a cache update is requested. + // WRITE or SC requests can require a PTE Dirty bit update (in memory), + // that is done (before handling the processor request) by a dedicated sub-fsm. + // If a PTE is modified, both the itlb and dtlb are selectively, but sequencially + // cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state). + // + // 4/ Atomic instructions LL/SC + // The LL/SC address are non cacheable (systematic access to memory). + // The llsc buffer contains a registration for an active LL/SC operation + // (with an address, a registration key, an aging counter and a valid bit). + // - LL requests from the processor are transmitted as a one flit VCI command + // (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must + // be 8 as the response is 2 flits long (data and registration key) + // - SC requests from the processor are systematically transmitted to the + // memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC + // as PKTID value). The first flit contains the registration key, the second + // flit contains the data to write in case of success. + // The cache is not updated, as this is done in case of success by the + // coherence transaction. + // + // 5/ Non cacheable access: + // This component implement a strong order between non cacheable access + // (read or write) : A new non cacheable VCI transaction starts only when + // the previous non cacheable transaction is completed. After send the VCI + // transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state. + // So the processor is blocked until the respone arrives in CACHE L1. + // + // 6/ Error handling: + // When the MMU is not activated, Read Bus Errors are synchronous events, + // Some Write Bus Errors are synchronous events when the request is a non cacheable access + // but some Write Bus Errors are asynchronous events when the request is cacheable access + // (processor is not frozen). + // - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the + // r_vci_rsp_data_error flip-flop, without writing any data in the + // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled + // by the DCACHE FSM. + // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals + // the asynchronous error using the setWriteBerr() method. + // When the MMU is activated bus error are rare events, as the MMU + // checks the physical address before the VCI transaction starts. + //////////////////////////////////////////////////////////////////////////////////////// + + // default value for m_drsp + m_drsp.valid = false; + m_drsp.error = false; + m_drsp.rdata = 0; + + switch ( r_dcache_fsm.read() ) + { + case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state : + // 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN + // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK + // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS + // 4) XTN request (processor) => DCACHE_XTN_* + // 5) DTLB miss (processor) => DCACHE_TLB_MISS + // 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE + // 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT + // 8) Uncacheable read (processor) => DCACHE_UNC_WAIT + // 9) LL access (processor) => DCACHE_LL_WAIT + // 10) SC access (processor) => DCACHE_SC_WAIT + // + // There is a fixed priority to handle requests to DCACHE: + // 1/ the ITLB/DTLB invalidate requests + // 2/ the coherence requests, + // 3/ the processor requests (including DTLB miss), + // 4/ the ITLB miss requests, + // The address space processor request are handled as follows: + // - WRITE request is blocked if the Dirty bit mus be set. + // If DTLB hit, the P1 stage is activated (writes WBUF, and + // updates DCACHE if DCACHE hit) & processor request acknowledged. + // - READ request generate a simultaneouss access to DCACHE.DATA + // and DCACHE.DIR, but is delayed if DCACHE update required. + // + // There is 4 configurations defining the access type to + // DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the + // dreq.valid (dreq) and r_dcache_updt_req (updt) signals: + // dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA / + // 0 / 0 / NOP / NOP / NOP / + // 0 / 1 / NOP / NOP / WRITE / + // 1 / 0 / READ / READ / NOP / + // 1 / 1 / READ / READ / WRITE / + // Those two registers are set at each cycle from the 3 signals + // updt_request, wbuf_request, wbuf_write_miss. + { + paddr_t paddr; // physical address + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + uint32_t cache_rdata = 0; + bool tlb_hit = false; + int cache_state = CACHE_SLOT_STATE_EMPTY; + + bool tlb_inval_required = false; // request TLB inval after cache update + bool wbuf_write_miss = false; // miss a WBUF write request + bool updt_request = false; // request DCACHE update in P1 stage + bool wbuf_request = false; // request WBUF write in P1 stage + + // physical address computation : systematic DTLB access if activated) + if ( m_dreq.valid ) + { + if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated + { + tlb_hit = r_dtlb.translate( m_dreq.addr, + &paddr, + &tlb_flags, + &tlb_nline, + &tlb_way, + &tlb_set ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + } + else // identity mapping + { + paddr = (paddr_t)m_dreq.addr; + // we take into account the paddr extension + if (vci_param::N > 32) + paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); + } + } // end physical address computation + + // systematic DCACHE access depending on r_dcache_updt_req (if activated) + if ( r_mmu_mode.read() & DATA_CACHE_MASK) + { + if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA + { + r_dcache.read_dir( paddr, + &cache_state, + &cache_way, + &cache_set, + &cache_word ); + + r_dcache.write( r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read() ); +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +m_cpt_dcache_data_write++; +#endif + } + else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA + { + r_dcache.read( paddr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word, + &cache_state ); + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +m_cpt_dcache_data_read++; +#endif + } + else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA + { + r_dcache.write( r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read() ); +#ifdef INSTRUMENTATION +m_cpt_dcache_data_write++; +#endif + } + } // end dcache access + + // DCACHE update in P1 stage can require ITLB / DTLB inval or flush + if ( r_dcache_updt_req.read() ) + { + size_t way = r_dcache_save_cache_way.read(); + size_t set = r_dcache_save_cache_set.read(); + + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) + { + tlb_inval_required = true; + r_dcache_tlb_inval_set = 0; + r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> + (uint32_log2(m_dcache_words<<2)); + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + } + else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " Cache update in P1 stage" << std::dec + << " / WAY = " << r_dcache_save_cache_way.read() + << " / SET = " << r_dcache_save_cache_set.read() + << " / WORD = " << r_dcache_save_cache_word.read() << std::hex + << " / WDATA = " << r_dcache_save_wdata.read() + << " / BE = " << r_dcache_save_be.read() << std::endl; +#endif + } // end test TLB inval + + // Try WBUF update in P1 stage + // Miss if the write request is non cacheable, and there is a pending + // non cacheable write, or if the write buffer is full. + if ( r_dcache_wbuf_req.read() ) + { + bool wok = r_wbuf.write( r_dcache_save_paddr.read(), + r_dcache_save_be.read(), + r_dcache_save_wdata.read(), + true); +#ifdef INSTRUMENTATION +m_cpt_wbuf_write++; +#endif + if ( not wok ) // miss if write buffer full + { + wbuf_write_miss = true; + } + } // end WBUF update + + // Computing the response to processor, + // and the next value for r_dcache_fsm + + // itlb/dtlb invalidation self-request + if ( tlb_inval_required ) + { + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + } + + // coherence clack request (from DSPIN CLACK) + else if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + } + // coherence request (from CC_RECEIVE FSM) + else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + } + + // processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE) + // we don't take the processor request, and registers + // are frozen in case of wbuf_write_miss + else if ( m_dreq.valid and not wbuf_write_miss ) + { + // register processor request and DCACHE response + r_dcache_save_vaddr = m_dreq.addr; + r_dcache_save_be = m_dreq.be; + r_dcache_save_wdata = m_dreq.wdata; + r_dcache_save_paddr = paddr; + r_dcache_save_cache_way = cache_way; + r_dcache_save_cache_set = cache_set; + r_dcache_save_cache_word = cache_word; + + // READ XTN requests from processor + // They are executed in this DCACHE_IDLE state. + // The processor must not be in user mode + if (m_dreq.type == iss_t::XTN_READ) + { + int xtn_opcode = (int)m_dreq.addr/4; + + // checking processor mode: + if (m_dreq.mode == iss_t::MODE_USER) + { + r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; + r_dcache_fsm = DCACHE_IDLE; + } + else + { + switch( xtn_opcode ) + { + case iss_t::XTN_INS_ERROR_TYPE: + m_drsp.rdata = r_mmu_ietr.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_DATA_ERROR_TYPE: + m_drsp.rdata = r_mmu_detr.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_INS_BAD_VADDR: + m_drsp.rdata = r_mmu_ibvar.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_DATA_BAD_VADDR: + m_drsp.rdata = r_mmu_dbvar.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_PTPR: + m_drsp.rdata = r_mmu_ptpr.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_TLB_MODE: + m_drsp.rdata = r_mmu_mode.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_PARAMS: + m_drsp.rdata = r_mmu_params; + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_RELEASE: + m_drsp.rdata = r_mmu_release; + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_WORD_LO: + m_drsp.rdata = r_mmu_word_lo.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_WORD_HI: + m_drsp.rdata = r_mmu_word_hi.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_DATA_PADDR_EXT: + m_drsp.rdata = r_dcache_paddr_ext.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + default: + r_mmu_detr = MMU_READ_UNDEFINED_XTN; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; + break; + } // end switch xtn_opcode + } // end else + } // end if XTN_READ + + // Handling WRITE XTN requests from processor. + // They are not executed in this DCACHE_IDLE state + // if they require access to the caches or the TLBs + // that are already accessed. + // Caches can be invalidated or flushed in user mode, + // and the sync instruction can be executed in user mode + else if (m_dreq.type == iss_t::XTN_WRITE) + { + int xtn_opcode = (int)m_dreq.addr/4; + r_dcache_xtn_opcode = xtn_opcode; + + // checking processor mode: + if ( (m_dreq.mode == iss_t::MODE_USER) && + (xtn_opcode != iss_t::XTN_SYNC) && + (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && + (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && + (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && + (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) ) + { + r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; + r_dcache_fsm = DCACHE_IDLE; + } + else + { + switch( xtn_opcode ) + { + case iss_t::XTN_PTPR: // itlb & dtlb must be flushed + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_SWITCH; + break; + + case iss_t::XTN_TLB_MODE: // no cache or tlb access + r_mmu_mode = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_DTLB_INVAL: // dtlb access + r_dcache_fsm = DCACHE_XTN_DT_INVAL; + break; + + case iss_t::XTN_ITLB_INVAL: // itlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IT_INVAL; + break; + + case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; + break; + + case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + if (sizeof(paddr_t) <= 32) + { + assert(r_mmu_word_hi.read() == 0 && + "high bits should be 0 for 32bit paddr"); + r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read(); + } + else + { + r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | + (paddr_t)r_mmu_word_lo.read(); + } + break; + + case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset + r_dcache_flush_count = 0; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH; + break; + + case iss_t::XTN_ICACHE_INVAL: // icache and itlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; + break; + + case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; + break; + + case iss_t::XTN_ICACHE_FLUSH: // icache access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_FLUSH; + break; + + case iss_t::XTN_SYNC: // wait until write buffer empty + r_dcache_fsm = DCACHE_XTN_SYNC; + break; + + case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access + r_mmu_word_lo = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access + r_mmu_word_hi = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access + r_dcache_llsc_valid = false; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access + r_dcache_paddr_ext = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + default: + r_mmu_detr = MMU_WRITE_UNDEFINED_XTN; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } // end switch xtn_opcode + } // end else + } // end if XTN_WRITE + + // Handling processor requests to address space (READ/WRITE/LL/SC) + // The dtlb and dcache can be activated or not. + // We compute the cacheability, and check processor request validity: + // - If DTLB not activated : cacheability is defined by the segment table, + // and there is no access rights checking. + // - If DTLB activated : cacheability is defined by the C bit in the PTE, + // and the U & W bits of the PTE are checked, as well as the DTLB hit. + // Jumps to the TLB_MISS sub-fsm in case of dtlb miss. + else + { + bool valid_req; + bool cacheable; + + if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated + { + valid_req = true; + + if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr]; + } + else // dtlb activated + { + if ( tlb_hit ) // tlb hit + { + // cacheability + if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + else cacheable = tlb_flags.c; + + // access rights checking + if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) + { + if ( (m_dreq.type == iss_t::DATA_READ) or + (m_dreq.type == iss_t::DATA_LL) ) + { + r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; + } + else + { + r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; + } + valid_req = false; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " HIT in dtlb, but privilege violation" << std::endl; +#endif + } + else if ( not tlb_flags.w and + ((m_dreq.type == iss_t::DATA_WRITE) or + (m_dreq.type == iss_t::DATA_SC)) ) + { + r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; + valid_req = false; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " HIT in dtlb, but writable violation" << std::endl; +#endif + } + else + { + valid_req = true; + } + } + else // tlb miss + { + valid_req = false; + r_dcache_tlb_vaddr = m_dreq.addr; + r_dcache_tlb_ins = false; + r_dcache_fsm = DCACHE_TLB_MISS; + } + } // end DTLB activated + + if ( valid_req ) // processor request is valid (after MMU check) + { + // READ request + // The read requests are taken only if there is no cache update. + // We request a VCI transaction to CMD FSM if miss or uncachable + + if ( ((m_dreq.type == iss_t::DATA_READ)) + and not r_dcache_updt_req.read() ) + { + if ( cacheable ) // cacheable read + { + if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss + { +#ifdef INSTRUMENTATION +m_cpt_dcache_miss++; +#endif + // request a VCI DMISS transaction + r_dcache_vci_paddr = paddr; + r_dcache_vci_miss_req = true; + r_dcache_miss_type = PROC_MISS; + r_dcache_fsm = DCACHE_MISS_SELECT; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " READ MISS in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif + } + else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_dcache_fsm = DCACHE_IDLE; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " Pending cleanup, stalled until cleanup acknowledge" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif + } + else // cache hit + { +#ifdef INSTRUMENTATION +m_cpt_data_read++; +#endif + // returns data to processor + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = cache_rdata; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " READ HIT in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif + } + } + else // uncacheable read + { + r_dcache_vci_paddr = paddr; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_write = false; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " " + << " READ UNCACHEABLE in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif + } + } // end READ + + // LL request (non cachable) + // We request a VCI LL transaction to CMD FSM and register + // the LL/SC operation in llsc buffer. + else if (m_dreq.type == iss_t::DATA_LL) + { + // register paddr in LLSC buffer + r_dcache_llsc_paddr = paddr; + r_dcache_llsc_count = LLSC_TIMEOUT; + r_dcache_llsc_valid = true; + + // request an LL VCI transaction and go to DCACHE_LL_WAIT state + r_dcache_vci_ll_req = true; + r_dcache_vci_paddr = paddr; + r_dcache_ll_rsp_count = 0; + r_dcache_fsm = DCACHE_LL_WAIT; + + }// end LL + + // WRITE request: + // If the TLB is activated and the PTE Dirty bit is not set, we stall + // the processor and set the Dirty bit before handling the write request, + // going to the DCACHE_DIRTY_GT_PTE state. + // If we don't need to set the Dirty bit, we can acknowledge + // the processor request, as the write arguments (including the + // physical address) are registered in r_dcache_save registers, + // and the write will be done in the P1 pipeline stage. + else if ( m_dreq.type == iss_t::DATA_WRITE ) + { + if ( (r_mmu_mode.read() & DATA_TLB_MASK ) + and not tlb_flags.d ) // Dirty bit must be set + { + // The PTE physical address is obtained from the nline value (dtlb), + // and from the virtual address (word index) + if ( tlb_flags.b ) // PTE1 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>19) & 0x3c); + } + else // PTE2 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>9) & 0x38); + } + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + } + else // Write request accepted + { +#ifdef INSTRUMENTATION +m_cpt_data_write++; +#endif + // cleaning llsc buffer if address matching + if ( paddr == r_dcache_llsc_paddr.read() ) + r_dcache_llsc_valid = false; + + if (not cacheable) + { + r_dcache_vci_paddr = paddr; + r_dcache_vci_wdata = m_dreq.wdata; + r_dcache_vci_unc_write = true; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; + } + else + { + // response to processor + m_drsp.valid = true; + // activating P1 stage + wbuf_request = true; + updt_request = (cache_state == CACHE_SLOT_STATE_VALID); + } + } + } // end WRITE + + // SC request: + // If the TLB is activated and the PTE Dirty bit is not set, we stall + // the processor and set the Dirty bit before handling the write request, + // going to the DCACHE_DIRTY_GT_PTE state. + // If we don't need to set the Dirty bit, we test the llsc buffer: + // If failure, we send a negative response to processor. + // If success, we request a SC transaction to CMD FSM and go + // to DCACHE_SC_WAIT state. + // We don't check a possible write hit in dcache, as the cache update + // is done by the coherence transaction induced by the SC... + else if ( m_dreq.type == iss_t::DATA_SC ) + { + if ( (r_mmu_mode.read() & DATA_TLB_MASK ) + and not tlb_flags.d ) // Dirty bit must be set + { + // The PTE physical address is obtained from the nline value (dtlb), + // and the word index (virtual address) + if ( tlb_flags.b ) // PTE1 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>19) & 0x3c); + } + else // PTE2 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>9) & 0x38); + } + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + m_drsp.valid = false; + m_drsp.error = false; + m_drsp.rdata = 0; + } + else // SC request accepted + { +#ifdef INSTRUMENTATION +m_cpt_data_sc++; +#endif + // checking local success + if( r_dcache_llsc_valid.read() and + (r_dcache_llsc_paddr.read() == paddr) ) // local success + { + // request an SC CMD and go to DCACHE_SC_WAIT state + r_dcache_vci_paddr = paddr; + r_dcache_vci_sc_req = true; + r_dcache_vci_sc_data = m_dreq.wdata; + r_dcache_fsm = DCACHE_SC_WAIT; + } + else // local fail + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = 0x1; + } + } + } // end SC + } // end valid_req + } // end if read/write/ll/sc request + } // end processor request + + // itlb miss request + else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss ) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + } + + // Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req + r_dcache_updt_req = updt_request; + r_dcache_wbuf_req = wbuf_request or + (r_dcache_wbuf_req.read() and wbuf_write_miss); + break; + } + ///////////////////// + case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss. + // Input arguments are: + // - r_dcache_tlb_vaddr + // - r_dcache_tlb_ins (true when itlb miss) + // The sub-fsm access the dcache to find the missing TLB entry, + // and activates the cache miss procedure in case of miss. + // It bypass the first level page table access if possible. + // It uses atomic access to update the R/L access bits + // in the page table if required. + // It directly updates the itlb or dtlb, and writes into the + // r_mmu_ins_* or r_mmu_data* error reporting registers. + { + uint32_t ptba = 0; + bool bypass; + paddr_t pte_paddr; + + // evaluate bypass in order to skip first level page table access + if ( r_dcache_tlb_ins.read() ) // itlb miss + { + bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); + } + else // dtlb miss + { + bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); + } + + if ( not bypass ) // Try to read PTE1/PTD1 in dcache + { + pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) | + ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); + r_dcache_tlb_paddr = pte_paddr; + r_dcache_fsm = DCACHE_TLB_PTE1_GET; + } + else // Try to read PTE2 in dcache + { + pte_paddr = (paddr_t)ptba << PAGE_K_NBITS | + (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); + r_dcache_tlb_paddr = pte_paddr; + r_dcache_fsm = DCACHE_TLB_PTE2_GET; + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + if ( r_dcache_tlb_ins.read() ) + std::cout << " ITLB miss"; + else + std::cout << " DTLB miss"; + std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() + << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) + << " / BYPASS = " << bypass + << " / PTE_ADR = " << pte_paddr << std::endl; +} +#endif + + break; + } + ///////////////////////// + case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + uint32_t entry; + size_t way; + size_t set; + size_t word; + int cache_state; + r_dcache.read( r_dcache_tlb_paddr.read(), + &entry, + &way, + &set, + &word, + &cache_state ); +#ifdef INSTRUMENTATION +m_cpt_dcache_data_read++; +m_cpt_dcache_dir_read++; +#endif + if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache + { + if ( not (entry & PTE_V_MASK) ) // unmapped + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT1_UNMAPPED; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT1_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " HIT in dcache, but unmapped" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; +} +#endif + + } + else if( entry & PTE_T_MASK ) // PTD : me must access PT2 + { + // mark the cache line ac containing a PTD + r_dcache_contains_ptd[m_dcache_sets*way+set] = true; + + // register bypass + if ( r_dcache_tlb_ins.read() ) // itlb + { + r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), + entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), + r_dcache_tlb_paddr.read() / (m_icache_words<<2) ); + } + else // dtlb + { + r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), + entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), + r_dcache_tlb_paddr.read() / (m_dcache_words<<2) ); + } + r_dcache_tlb_paddr = + (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | + (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); + r_dcache_fsm = DCACHE_TLB_PTE2_GET; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTD = " << entry << std::endl; +} +#endif + } + else // PTE1 : we must update the TLB + { + r_dcache_in_tlb[m_icache_sets*way+set] = true; + r_dcache_tlb_pte_flags = entry; + r_dcache_tlb_cache_way = way; + r_dcache_tlb_cache_set = set; + r_dcache_tlb_cache_word = word; + r_dcache_fsm = DCACHE_TLB_PTE1_SELECT; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; +} +#endif + } + } + else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_dcache_fsm = DCACHE_TLB_PTE1_GET; + } + else // we must load the missing cache line in dcache + { + r_dcache_vci_miss_req = true; + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); + r_dcache_miss_type = PTE1_MISS; + r_dcache_fsm = DCACHE_MISS_SELECT; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " MISS in dcache:" + << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; +} +#endif + } + break; + } + //////////////////////////// + case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 + { + size_t way; + size_t set; + + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.select( r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + } + else + { + r_dtlb.select( r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + } + r_dcache_tlb_way = way; + r_dcache_tlb_set = set; + r_dcache_fsm = DCACHE_TLB_PTE1_UPDT; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + if ( r_dcache_tlb_ins.read() ) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; +} +#endif + break; + } + ////////////////////////// + case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit + // - if L/R bit already set, exit the sub-fsm. + // - if not, we update the page table but we dont write + // neither in DCACHE, nor in TLB, as this will be done by + // the coherence mechanism. + { + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); + uint32_t pte = r_dcache_tlb_pte_flags.read(); + bool pt_updt = false; + bool local = true; + + // We should compute the access locality: + // The PPN MSB bits define the destination cluster index. + // The m_srcid MSB bits define the source cluster index. + // The number of bits to compare depends on the number of clusters, + // and can be obtained in the mapping table. + // As long as this computation is not done, all access are local. + + if ( local ) // local access + { + if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_L_MASK; + pte = pte | PTE_L_MASK; + r_dcache_tlb_pte_flags = pte; + } + } + else // remote access + { + if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_R_MASK; + pte = pte | PTE_R_MASK; + r_dcache_tlb_pte_flags = pte; + } + } + + if ( not pt_updt ) // update TLB and return + { + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.write( true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_itlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " write PTE1 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); +} +#endif + } + else + { + r_dtlb.write( true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " write PTE1 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); +} +#endif + } + r_dcache_fsm = DCACHE_TLB_RETURN; + } + else // update page table but not TLB + { + r_dcache_fsm = DCACHE_TLB_LR_UPDT; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " L/R bit update required" + << std::endl; +} +#endif + } + break; + } + ///////////////////////// + case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + uint32_t pte_flags; + uint32_t pte_ppn; + size_t way; + size_t set; + size_t word; + int cache_state; + + r_dcache.read( r_dcache_tlb_paddr.read(), + &pte_flags, + &pte_ppn, + &way, + &set, + &word, + &cache_state ); +#ifdef INSTRUMENTATION +m_cpt_dcache_data_read++; +m_cpt_dcache_dir_read++; +#endif + if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache + { + if ( not (pte_flags & PTE_V_MASK) ) // unmapped + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT2_UNMAPPED; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT2_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " HIT in dcache, but PTE unmapped" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; +} +#endif + } + else // mapped : we must update the TLB + { + r_dcache_in_tlb[m_dcache_sets*way+set] = true; + r_dcache_tlb_pte_flags = pte_flags; + r_dcache_tlb_pte_ppn = pte_ppn; + r_dcache_tlb_cache_way = way; + r_dcache_tlb_cache_set = set; + r_dcache_tlb_cache_word = word; + r_dcache_fsm = DCACHE_TLB_PTE2_SELECT; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " HIT in dcache:" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; +} +#endif + } + } + else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_dcache_fsm = DCACHE_TLB_PTE2_GET; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " ZOMBI in dcache: waiting cleanup ack" + << std::endl; +} +#endif + } + else // we must load the missing cache line in dcache + { + r_dcache_fsm = DCACHE_MISS_SELECT; + r_dcache_vci_miss_req = true; + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); + r_dcache_miss_type = PTE2_MISS; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " MISS in dcache:" + << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; +} +#endif + } + break; + } + //////////////////////////// + case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2 + { + size_t way; + size_t set; + + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.select( r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + } + else + { + r_dtlb.select( r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + if ( r_dcache_tlb_ins.read() ) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; +} +#endif + r_dcache_tlb_way = way; + r_dcache_tlb_set = set; + r_dcache_fsm = DCACHE_TLB_PTE2_UPDT; + break; + } + ////////////////////////// + case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit + // - if L/R bit already set, exit the sub-fsm. + // - if not, we update the page table but we dont write + // neither in DCACHE, nor in TLB, as this will be done by + // the coherence mechanism. + { + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); + uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); + uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); + bool pt_updt = false; + bool local = true; + + // We should compute the access locality: + // The PPN MSB bits define the destination cluster index. + // The m_srcid MSB bits define the source cluster index. + // The number of bits to compare depends on the number of clusters, + // and can be obtained in the mapping table. + // As long as this computation is not done, all access are local. + + if ( local ) // local access + { + if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte_flags; + r_dcache_vci_cas_new = pte_flags | PTE_L_MASK; + pte_flags = pte_flags | PTE_L_MASK; + r_dcache_tlb_pte_flags = pte_flags; + } + } + else // remote access + { + if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte_flags; + r_dcache_vci_cas_new = pte_flags | PTE_R_MASK; + pte_flags = pte_flags | PTE_R_MASK; + r_dcache_tlb_pte_flags = pte_flags; + } + } + + if ( not pt_updt ) // update TLB + { + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.write( false, // 4K page + pte_flags, + pte_ppn, + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_itlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " write PTE2 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); +} +#endif + } + else + { + r_dtlb.write( false, // 4K page + pte_flags, + pte_ppn, + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " write PTE2 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); +} +#endif + + } + r_dcache_fsm = DCACHE_TLB_RETURN; + } + else // update page table but not TLB + { + r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " L/R bit update required" << std::endl; +} +#endif + } + break; + } + //////////////////////// + case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit + { +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Update dcache: (L/R) bit" << std::endl; +} +#endif + // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + + // checking llsc reservation buffer + if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) + r_dcache_llsc_valid = false; + + // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state + r_dcache_vci_cas_req = true; + r_dcache_fsm = DCACHE_TLB_LR_WAIT; + break; + } + //////////////////////// + case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit. + // We consume the response in rsp FIFO, + // and exit the sub-fsm, but we don't + // analyse the response, because we don't + // care if the L/R bit update is not done. + // We must take the coherence requests because + // there is a risk of dead-lock + + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl; + std::cout << "This should not happen in this state" << std::endl; + exit(0); + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + { +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " SC response received" << std::endl; +} +#endif + vci_rsp_fifo_dcache_get = true; + r_dcache_fsm = DCACHE_TLB_RETURN; + } + break; + } + /////////////////////// + case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type + { +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " TLB MISS completed" << std::endl; +} +#endif + if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false; + r_dcache_fsm = DCACHE_IDLE; + break; + } + /////////////////////// + case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written, + // and both itlb and dtlb must be flushed. + // Caution : the itlb miss requests must be taken + // to avoid dead-lock in case of simultaneous ITLB miss + // Caution : the clack and cc requests must be taken + // to avoid dead-lock + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // itlb miss request + if ( r_icache_tlb_miss_req.read() ) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + break; + } + + if ( not r_dcache_xtn_req.read() ) + { + r_dtlb.flush(); + r_mmu_ptpr = m_dreq.wdata; + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + break; + } + ///////////////////// + case DCACHE_XTN_SYNC: // waiting until write buffer empty + // The coherence request must be taken + // as there is a risk of dead-lock + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_wbuf.empty() ) + { + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + } + break; + } + //////////////////////// + case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM + case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken + case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache + case DCACHE_XTN_IT_INVAL: // can generate an itlb miss, + // and because it can exist a simultaneous ITLB miss + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // itlb miss request + if ( r_icache_tlb_miss_req.read() ) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + break; + } + + // test if XTN request to icache completed + if ( not r_dcache_xtn_req.read() ) + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + break; + } + ///////////////////////// + case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using + // r_dcache_flush_count as a slot counter, + // looping in this state until all slots have been visited. + // It can require two cycles per slot: + // We test here the slot state, and make the actual inval + // (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state. + // A cleanup request is generated for each valid line. + // returns to IDLE and flush TLBs when last slot + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_dcache_flush_count.read()/m_dcache_sets; + size_t set = r_dcache_flush_count.read()%m_dcache_sets; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir( way, + set, + &tag, + &state ); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval required + { + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = tag * m_dcache_sets + set; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + + // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory + r_dcache_miss_way = way; + r_dcache_miss_set = set; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; + } + else if ( r_dcache_flush_count.read() == + (m_dcache_sets*m_dcache_ways - 1) ) // last slot + { + r_dtlb.reset(); + r_itlb.reset(); + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + + // saturation counter + if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) ) + r_dcache_flush_count = r_dcache_flush_count.read() + 1; + } + break; + } + //////////////////////////// + case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state + // and reset directory extension. + // returns to IDLE and flush TLBs when last slot + { + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); + + r_dcache_in_tlb[m_dcache_sets*way+set] = false; + r_dcache_contains_ptd[m_dcache_sets*way+set] = false; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + if ( r_dcache_flush_count.read() == + (m_dcache_sets*m_dcache_ways - 1) ) // last slot + { + r_dtlb.reset(); + r_itlb.reset(); + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + else + { + r_dcache_fsm = DCACHE_XTN_DC_FLUSH; + } + break; + } + ///////////////////////// + case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request + { + r_dtlb.inval(r_dcache_save_wdata.read()); + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + break; + } + //////////////////////////// + case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address + // requires 3 cycles: access tlb, read cache, inval cache + // we compute the physical address in this state + { + paddr_t paddr; + bool hit; + + if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated + { + +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + hit = r_dtlb.translate( r_dcache_save_wdata.read(), + &paddr ); + } + else // dtlb not activated + { + paddr = (paddr_t)r_dcache_save_wdata.read(); + if (vci_param::N > 32) + paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); + hit = true; + } + + if ( hit ) // tlb hit + { + r_dcache_save_paddr = paddr; + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + } + else // tlb miss + { + +#ifdef INSTRUMENTATION +m_cpt_dtlb_miss++; +#endif + r_dcache_tlb_ins = false; // dtlb + r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Compute physical address" << std::hex + << " / VADDR = " << r_dcache_save_wdata.read() + << " / PADDR = " << paddr << std::endl; +} +#endif + + break; + } + //////////////////////////// + case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address + // requires 2 cycles: read cache / inval cache + // In this state we read dcache. + { + size_t way; + size_t set; + size_t word; + int state; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir( r_dcache_save_paddr.read(), + &state, + &way, + &set, + &word ); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + { + r_dcache_xtn_way = way; + r_dcache_xtn_set = set; + r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; + } + else // miss : nothing to do + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Test hit in dcache" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::dec + << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) + << " / SET = " << set + << " / WAY = " << way << std::endl; +} +#endif + break; + } + //////////////////////////// + case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line + // Blocked if previous cleanup not completed + // Test if itlb or dtlb inval is required + { + if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent + { + size_t way = r_dcache_xtn_way.read(); + size_t set = r_dcache_xtn_set.read(); + paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2); + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = nline; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + + // possible itlb & dtlb invalidate + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) + { + r_dcache_tlb_inval_line = nline; + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + } + else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + else + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Actual dcache inval" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::endl; +} +#endif + } + break; + } + ////////////////////////////// + case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + break; + } + //////////////////////// + case DCACHE_MISS_SELECT: // Try to select a slot in associative set, + // Waiting in this state if no slot available. + // If a victim slot has been choosen and the r_icache_cc_send_req is false, + // we send the cleanup request in this state. + // If not, a r_icache_cleanup_victim_req flip-flop is + // utilized for saving this cleanup request, and it will be sent later + // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. + // The r_icache_miss_clack flip-flop is set + // when a cleanup is required + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + bool found = false; + bool cleanup = false; + size_t way = 0; + size_t set = 0; + paddr_t victim = 0; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_select( r_dcache_save_paddr.read(), + &victim, + &way, + &set, + &found, + &cleanup ); + + if ( not found ) + { + break; + } + else + { + r_dcache_miss_way = way; + r_dcache_miss_set = set; + + if ( cleanup ) + { + if ( not r_dcache_cc_send_req.read() ) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = victim; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + + } + else + { + r_dcache_cleanup_victim_req = true; + r_dcache_cleanup_victim_nline = victim; + } + + r_dcache_miss_clack = true; + r_dcache_fsm = DCACHE_MISS_CLEAN; + } + else + { + r_dcache_fsm = DCACHE_MISS_WAIT; + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); + if(cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl; + else std::cout << std::endl; +} +#endif + } // end found + break; + } + /////////////////////// + case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state + // and possibly request itlb or dtlb invalidate + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Switch to ZOMBI state" << std::dec + << " / way = " << way + << " / set = " << set << std::endl; +} +#endif + // if selective itlb & dtlb invalidate are required + // the miss response is not handled before invalidate completed + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) + { + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + + if( not r_dcache_cleanup_victim_req.read() ) + r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read(); + else + r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read(); + + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + } + else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_fsm = DCACHE_MISS_WAIT; + } + else + { + r_dcache_fsm = DCACHE_MISS_WAIT; + } + break; + } + ////////////////////// + case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM + // This state is in charge of error signaling + // There is 5 types of error depending on the requester + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + // send cleanup victim request + if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; + r_dcache_cc_send_way = r_dcache_miss_way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cleanup_victim_req = false; + } + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + switch ( r_dcache_miss_type.read() ) + { + case PROC_MISS: + { + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_save_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + case PTE1_MISS: + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + break; + } + case PTE2_MISS: + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + break; + } + } // end switch type + r_vci_rsp_data_error = false; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available + { + r_dcache_miss_word = 0; + r_dcache_fsm = DCACHE_MISS_DATA_UPDT; + } + break; + } + ////////////////////////// + case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + if ( r_vci_rsp_fifo_dcache.rok() ) // one word available + { +#ifdef INSTRUMENTATION +m_cpt_dcache_data_write++; +#endif + r_dcache.write( r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + r_dcache_miss_word.read(), + r_vci_rsp_fifo_dcache.read() ); +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Write one word:" + << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() + << " / WORD = " << r_dcache_miss_word.read() << std::endl; +} +#endif + vci_rsp_fifo_dcache_get = true; + r_dcache_miss_word = r_dcache_miss_word.read() + 1; + + if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word + { + r_dcache_fsm = DCACHE_MISS_DIR_UPDT; + } + } + break; + } + ////////////////////////// + case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted + // and the cleanup ack has not been received, + // as indicated by the r_dcache_miss clack. + // - If no matching coherence request (r_dcache_inval_miss) + // switch directory slot to VALID state. + // - If matching coherence request, switch directory slot + // to ZOMBI state, and send a cleanup request. + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + // send cleanup victim request + if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; + r_dcache_cc_send_way = r_dcache_miss_way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cleanup_victim_req = false; + } + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge + { + if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup + { + if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent + { + r_dcache_miss_inval = false; + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); + r_dcache_cc_send_way = r_dcache_miss_way.read(); + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI ); +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " Switch slot to ZOMBI state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; +#endif + } + else + break; + } + else // switch slot to VALID state + { + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_VALID ); + +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " Switch slot to VALID state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; +#endif + // reset directory extension + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + } + if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; + else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; + else r_dcache_fsm = DCACHE_IDLE; + } + break; + } + ///////////////////// + case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + if(r_dcache_vci_unc_write.read()) + r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; + else + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + + r_mmu_dbvar = m_dreq.addr; + r_vci_rsp_data_error = false; + m_drsp.error = true; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + { + // consume data + vci_rsp_fifo_dcache_get = true; + r_dcache_fsm = DCACHE_IDLE; + + // acknowledge the processor request if it has not been modified + if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + } + } + break; + } + ///////////////////// + case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = m_dreq.addr; + r_vci_rsp_data_error = false; + m_drsp.error = true; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + { + // consume data + vci_rsp_fifo_dcache_get = true; + + if(r_dcache_ll_rsp_count.read() == 0) // first flit + { + // set key value in llsc reservation buffer + r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read(); + r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ; + } + else // last flit + { + // acknowledge the processor request if it has not been modified + if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + } + r_dcache_fsm = DCACHE_IDLE; + } + } + break; + } + //////////////////// + case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = m_dreq.addr; + r_vci_rsp_data_error = false; + m_drsp.error = true; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + { + // consume response + vci_rsp_fifo_dcache_get = true; + m_drsp.valid = true; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + r_dcache_fsm = DCACHE_IDLE; + } + break; + } + ////////////////////////// + case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory + // before handling a processor WRITE or SC request + // Input argument is r_dcache_dirty_paddr + // In this first state, we get PTE value in dcache + // and post a CAS request to CMD FSM + { + // get PTE in dcache + uint32_t pte; + size_t way; + size_t set; + size_t word; // unused + int state; + +#ifdef INSTRUMENTATION +m_cpt_dcache_data_read++; +m_cpt_dcache_dir_read++; +#endif + r_dcache.read( r_dcache_dirty_paddr.read(), + &pte, + &way, + &set, + &word, + &state ); + + assert( (state == CACHE_SLOT_STATE_VALID) and + "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" ); + + // request CAS transaction to CMD_FSM + r_dcache_dirty_way = way; + r_dcache_dirty_set = set; + + // check llsc reservation buffer + if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() ) + r_dcache_llsc_valid = false; + + // request a CAS CMD and go to DCACHE_DIRTY_WAIT state + r_dcache_vci_cas_req = true; + r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_D_MASK; + r_dcache_fsm = DCACHE_DIRTY_WAIT; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " CAS request" << std::hex + << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() + << " / PTE_VALUE = " << pte << std::dec + << " / SET = " << set + << " / WAY = " << way << std::endl; +} +#endif + break; + } + /////////////////////// + case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, + // and return to IDLE state when response is received. + // we don't care if the CAS is a failure: + // - if the CAS is a success, the coherence mechanism + // updates the local copy. + // - if the CAS is a failure, we just retry the write. + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; + std::cout << "This should not happen in this state" << std::endl; + exit(0); + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + { + vci_rsp_fifo_dcache_get = true; + r_dcache_fsm = DCACHE_IDLE; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " CAS completed" << std::endl; +} +#endif + } + break; + } + ///////////////////// + case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM + // handling coherence requests for DCACHE. + // If there is a matching pending miss on the modified cache + // line this is signaled in the r_dcache_miss inval flip-flop. + // If the updated (or invalidated) cache line has copies in TLBs + // these TLB copies are invalidated. + // The return state is defined in r_dcache_fsm_cc_save + { + paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4; + paddr_t mask = ~((m_dcache_words<<2)-1); + + // CLACK handler + // We switch the directory slot to EMPTY state and reset + // r_dcache_miss_clack if the cleanup ack is matching a pending miss. + if ( r_dcache_clack_req.read() ) + { + if ( m_dreq.valid ) m_cost_data_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( 0, + r_dcache_clack_way.read(), + r_dcache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and + (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) + { + r_dcache_miss_clack = false; + } + + r_dcache_clack_req = false; + + // return to cc_save state + r_dcache_fsm = r_dcache_fsm_cc_save.read() ; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " CLACK for PADDR " << paddr + << " Switch slot to EMPTY state : " + << " set = " << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; +} +#endif + break; + } + + assert ( not r_dcache_cc_send_req.read() and + "CC_SEND must be available in DCACHE_CC_CHECK" ); + + // Match between MISS address and CC address + if (r_cc_receive_dcache_req.read() and + ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and + ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching + { + // signaling matching + r_dcache_miss_inval = true; + + // in case of update, go to CC_UPDT + // JUST TO POP THE FIFO + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_dcache_cc_need_write = false; + } + // the request is dealt with + else + { + r_cc_receive_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + + // CC request handler + + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir( paddr, + &state, + &way, + &set, + &word ); // unused + + r_dcache_cc_way = way; + r_dcache_cc_set = set; + + if ( state == CACHE_SLOT_STATE_VALID) // hit + { + // need to update the cache state + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update + { + r_dcache_cc_need_write = true; + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + } + else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval + { + r_dcache_fsm = DCACHE_CC_INVAL; + } + } + else // miss + { + // multicast acknowledgement required in case of update + if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_dcache_cc_need_write = false; + } + else // No response needed + { + r_cc_receive_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + } + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Coherence request received:" + << " PADDR = " << std::hex << paddr + << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() + << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl; +} +#endif + + break; + } + ///////////////////// + case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a + // CLEANUP after possible invalidation of copies in + // TLBs + { + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval + { + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + break; + } + + if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Flush DTLB & ITLB" << std::endl; +} +#endif + } + + assert (not r_dcache_cc_send_req.read() && + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); + + // Switch slot state to ZOMBI and send CLEANUP command + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + // coherence request completed + r_cc_receive_dcache_req = false; + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); + r_dcache_cc_send_way = r_dcache_cc_way.read(); + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Switch slot to EMPTY state:" << std::dec + << " / WAY = " << way + << " / SET = " << set << std::endl; +} +#endif + break; + } + /////////////////// + case DCACHE_CC_UPDT: // hit update: write one word per cycle, + // after possible invalidation of copies in TLBs + { + size_t word = r_dcache_cc_word.read(); + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval + { + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + + break; + } + + if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Flush DTLB & ITLB" << std::endl; +} +#endif + } + + assert (not r_dcache_cc_send_req.read() && + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); + + if ( not r_cc_receive_updt_fifo_be.rok() ) break; + + if (r_dcache_cc_need_write.read()) + { + +#ifdef INSTRUMENTATION +m_cpt_dcache_data_write++; +#endif + r_dcache.write( way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read() ); + + r_dcache_cc_word = word + 1; + +#if DEBUG_DCACHE +if ( m_debug_activated ) +{ + std::cout << " Write one word" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / WORD = " << word + << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl; +} +#endif + } + + if ( r_cc_receive_updt_fifo_eop.read() ) // last word + { + // no need to write in the cache anymore + r_dcache_cc_need_write = false; + + // coherence request completed + r_cc_receive_dcache_req = false; + + // request multicast acknowledgement + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); + r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); + r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; + + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + + //consume fifo if not eop + cc_receive_updt_fifo_get = true; + + break; + } + /////////////////////////// + case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB + // It makes assumption: m_itlb_sets == m_dtlb_sets + // All ways are handled in parallel. + // We enter this state when a DCACHE line is modified, + // and there is a copy in itlb or dtlb. + // It can be caused by: + // - a coherence inval or updt transaction, + // - a line inval caused by a cache miss + // - a processor XTN inval request, + // - a WRITE hit, + // - a Dirty bit update + // Input arguments are: + // - r_dcache_tlb_inval_line + // - r_dcache_tlb_inval_set + // - r_dcache_fsm_scan_save + { + paddr_t line = r_dcache_tlb_inval_line.read(); + size_t set = r_dcache_tlb_inval_set.read(); + size_t way; + bool ok; + + for ( way = 0 ; way < m_itlb_ways ; way++ ) + { + ok = r_itlb.inval( line, way, set ); + +#if DEBUG_DCACHE +if ( m_debug_activated and ok ) +{ + std::cout << " Invalidate ITLB entry:" << std::hex + << " line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; +} +#endif + } + + for ( way = 0 ; way < m_dtlb_ways ; way++ ) + { + ok = r_dtlb.inval( line, way, set ); + +#if DEBUG_DCACHE +if ( m_debug_activated and ok ) +std::cout << " " + << " Invalidate DTLB entry" << std::hex + << " / line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; +#endif + } + + // return to the calling state when TLB inval completed + if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) ) + { + r_dcache_fsm = r_dcache_fsm_scan_save.read(); + } + r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1; + break; + } + } // end switch r_dcache_fsm + + ///////////////// wbuf update /////////////////////////////////////////////////////// + r_wbuf.update(); + + ///////////////// llsc update /////////////////////////////////////////////////////// + if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1; + if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false; + + //////////////// test processor frozen ////////////////////////////////////////////// + // The simulation exit if the number of consecutive frozen cycles + // is larger than the m_max_frozen_cycles (constructor parameter) + if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) ) + { + m_cpt_frz_cycles++; // used for instrumentation + m_cpt_stop_simulation++; // used for debug + if ( m_cpt_stop_simulation > m_max_frozen_cycles ) + { + std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl + << " stop at cycle " << m_cpt_total_cycles << std::endl + << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles + << std::endl; + r_iss.dump(); + exit(1); + } + } + else + { + m_cpt_stop_simulation = 0; + } + + /////////// execute one iss cycle ///////////////////////////////// + { + uint32_t it = 0; + for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<" + << " / dmiss_req = " << dcache_miss_req + << " / imiss_req = " << icache_miss_req + << std::endl; +} +#endif + break; + } + //////////////////// + case CMD_DATA_WRITE: + { + if ( p_vci.cmdack.read() ) + { + r_vci_cmd_cpt = r_vci_cmd_cpt + 1; + if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent + { + r_vci_cmd_fsm = CMD_IDLE ; + r_wbuf.sent() ; + } + } + break; + } + ///////////////// + case CMD_DATA_SC: + case CMD_DATA_CAS: + { + // The CAS and SC VCI commands contain two flits + if ( p_vci.cmdack.read() ) + { + r_vci_cmd_cpt = r_vci_cmd_cpt + 1; + if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ; + } + break; + } + ////////////////// + case CMD_INS_MISS: + case CMD_INS_UNC: + case CMD_DATA_MISS: + case CMD_DATA_UNC_READ: + case CMD_DATA_UNC_WRITE: + case CMD_DATA_LL: + { + // all read VCI commands contain one single flit + if ( p_vci.cmdack.read() ) { + r_vci_cmd_fsm = CMD_IDLE; + } + break; + } + + } // end switch r_vci_cmd_fsm + + ////////////////////////////////////////////////////////////////////////// + // The VCI_RSP FSM controls the following ressources: + // - r_vci_rsp_fsm: + // - r_vci_rsp_fifo_icache (push) + // - r_vci_rsp_fifo_dcache (push) + // - r_vci_rsp_data_error (set) + // - r_vci_rsp_ins_error (set) + // - r_vci_rsp_cpt + // - r_dcache_vci_sc_req (reset when SC response recieved) + // + // As the VCI_RSP and VCI_CMD are fully desynchronized to support several + // simultaneous VCI transactions, this FSM uses the VCI RPKTID field + // to identify the transactions. + // + // VCI vormat: + // This component checks the response packet length and accepts only + // single word packets for write response packets. + // + // Error handling: + // This FSM analyzes the VCI error code and signals directly the Write Bus Error. + // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error + // flip_flop and the error is signaled by the DCACHE FSM. + // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error + // flip_flop and the error is signaled by the ICACHE FSM. + // In case of Cleanup Error, the simulation stops with an error message... + ////////////////////////////////////////////////////////////////////////// + + switch ( r_vci_rsp_fsm.read() ) + { + ////////////// + case RSP_IDLE: + { + if ( p_vci.rspval.read() ) + { + r_vci_rsp_cpt = 0; + + if ( (p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC ) + { + r_vci_rsp_fsm = RSP_DATA_UNC; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS ) + { + r_vci_rsp_fsm = RSP_DATA_MISS; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC ) + { + r_vci_rsp_fsm = RSP_INS_UNC; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS ) + { + r_vci_rsp_fsm = RSP_INS_MISS; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE ) + { + r_vci_rsp_fsm = RSP_DATA_WRITE; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS ) + { + r_vci_rsp_fsm = RSP_DATA_UNC; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL ) + { + r_vci_rsp_fsm = RSP_DATA_LL; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC ) + { + r_vci_rsp_fsm = RSP_DATA_UNC; + } + else + { + assert(false and "Unexpected VCI response"); + } + } + break; + } + ////////////////// + case RSP_INS_MISS: + { + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_ins_error = true; + if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_icache.wok() ) + { + if ( r_vci_rsp_cpt.read() >= m_icache_words ) + { + std::cout << "ERROR in VCI_CC_VCACHE " << name() + << " VCI response packet too long " + << " for instruction miss" << std::endl; + exit(0); + } + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_icache_put = true, + vci_rsp_fifo_icache_data = p_vci.rdata.read(); + if ( p_vci.reop.read() ) + { + if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) ) + { + std::cout << "ERROR in VCI_CC_VCACHE " << name() + << " VCI response packet too short" + << " for instruction miss" << std::endl; + exit(0); + } + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + } + break; + } + ///////////////// + case RSP_INS_UNC: + { + if (p_vci.rspval.read() ) + { + assert( p_vci.reop.read() and + "illegal VCI response packet for uncachable instruction"); + + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_ins_error = true; + r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_icache.wok()) + { + vci_rsp_fifo_icache_put = true; + vci_rsp_fifo_icache_data = p_vci.rdata.read(); + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + break; + } + /////////////////// + case RSP_DATA_MISS: + { + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_data_error = true; + if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_dcache.wok() ) + { + assert( (r_vci_rsp_cpt.read() < m_dcache_words) and + "The VCI response packet for data miss is too long"); + + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_dcache_put = true, + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + if ( p_vci.reop.read() ) + { + assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and + "The VCI response packet for data miss is too short"); + + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + } + break; + } + ////////////////// + case RSP_DATA_UNC: + { + if (p_vci.rspval.read() ) + { + assert( p_vci.reop.read() and + "illegal VCI response packet for uncachable read data"); + + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_data_error = true; + r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_dcache.wok()) + { + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + break; + } + ///////////////// + case RSP_DATA_LL: + { + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_data_error = true; + r_vci_rsp_fsm = RSP_IDLE; + break; + } + if (r_vci_rsp_cpt.read() == 0) //first flit + { + if(r_vci_rsp_fifo_dcache.wok()) + { + assert(!p_vci.reop.read() && + "illegal VCI response packet for LL"); + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + } + break; + } + else // last flit + { + if(r_vci_rsp_fifo_dcache.wok()) + { + assert(p_vci.reop.read() && + "illegal VCI response packet for LL"); + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + r_vci_rsp_fsm = RSP_IDLE; + } + break; + } + } + break; + } + //////////////////// + case RSP_DATA_WRITE: + { + if (p_vci.rspval.read()) + { + assert( p_vci.reop.read() and + "a VCI response packet must contain one flit for a write transaction"); + + r_vci_rsp_fsm = RSP_IDLE; + uint32_t wbuf_index = p_vci.rtrdid.read(); + r_wbuf.completed(wbuf_index); + if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); + } + break; + } + } // end switch r_vci_rsp_fsm + + ///////////////////////////////////////////////////////////////////////////////////// + // The CC_SEND FSM is in charge of sending cleanups and the multicast + // acknowledgements on the coherence network. It has two clients (DCACHE FSM + // and ICACHE FSM) that are served with a round-robin priority. + // The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as + // soon as the request has been sent. + ///////////////////////////////////////////////////////////////////////////////////// + switch ( r_cc_send_fsm.read() ) + { + /////////////////////////// + case CC_SEND_IDLE: + { + /////////////////////////////////////////////////////// + // handling round robin between icache and dcache : // + // we first check for the last client and listen for // + // a request of the other, then update the client // + // r_cc_send_last_client : 0 dcache / 1 icache + /////////////////////////////////////////////////////// + bool update_last_client = r_cc_send_last_client.read(); + if ( r_cc_send_last_client.read() == 0 ) // last client was dcache + { + if (r_icache_cc_send_req.read()) // request from icache + update_last_client = 1; // update last client to icache + } + else // last client was icache + { + if (r_dcache_cc_send_req.read()) // request from dcache + update_last_client = 0; // update last client to dcache + } + r_cc_send_last_client = update_last_client; + + // if there is an actual request + if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read()) + { + // the new client is dcache and has a cleanup request + if ( (update_last_client == 0) and + (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) + r_cc_send_fsm = CC_SEND_CLEANUP_1; + // the new client is dcache and has a multi acknowledgement request + else if ( (update_last_client == 0) and + (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) + r_cc_send_fsm = CC_SEND_MULTI_ACK; + // the new client is icache and has a cleanup request + else if ( (update_last_client == 1) and + (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) + r_cc_send_fsm = CC_SEND_CLEANUP_1; + // the new client is icache and has a multi acknowledgement request + else if ( (update_last_client == 1) and + (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) + r_cc_send_fsm = CC_SEND_MULTI_ACK; + } + break; + } + /////////////////////////// + case CC_SEND_CLEANUP_1: + { + // wait for the first flit to be consumed + if (p_dspin_p2m.read.read()) + r_cc_send_fsm = CC_SEND_CLEANUP_2; + + break; + } + /////////////////////////// + case CC_SEND_CLEANUP_2: + { + // wait for the second flit to be consumed + if (p_dspin_p2m.read.read()) + { + if (r_cc_send_last_client.read() == 0) // dcache active request + r_dcache_cc_send_req = false; // reset dcache request + else // icache active request + r_icache_cc_send_req = false; // reset icache request + + // go back to idle state + r_cc_send_fsm = CC_SEND_IDLE; + } + break; + } + /////////////////////////// + case CC_SEND_MULTI_ACK: + { + // wait for the flit to be consumed + if(p_dspin_p2m.read.read()) + { + if(r_cc_send_last_client.read() == 0) // dcache active request + r_dcache_cc_send_req = false; // reset dcache request + else // icache active request + r_icache_cc_send_req = false; // reset icache request + // go back to idle state + r_cc_send_fsm = CC_SEND_IDLE; + } + break; + } + } // end switch CC_SEND FSM + + /////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE FSM + // This FSM receive all coherence packets on a DSPIN40 port. + // There is 5 packet types: + // - CC_DATA_INVAL : DCACHE invalidate request + // - CC_DATA_UPDT : DCACHE update request (multi-words) + // - CC_INST_INVAL : ICACHE invalidate request + // - CC_INST_UPDT : ICACHE update request (multi-words) + // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) + ////////////////////////////////////////////////////////////////////////////// + switch( r_cc_receive_fsm.read() ) + { + ///////////////////// + case CC_RECEIVE_IDLE: + { + // a coherence request has arrived + if (p_dspin_m2p.write.read()) + { + // initialize dspin received data + uint64_t receive_data = p_dspin_m2p.data.read(); + // initialize coherence packet type + uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, + DspinDhccpParam::M2P_TYPE); + // test for a broadcast + if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC)) + { + r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; + } + // test for a multi updt + else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) + { + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; + } + else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST) + { + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER; + } + // test for a multi inval + else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA) + { + r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER; + } + else + { + r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER; + } + } + break; + } + /////////////////////////////// + case CC_RECEIVE_BRDCAST_HEADER: + { + // no actual data in the HEADER, just skip to second flit + r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE; + break; + } + ////////////////////////////// + case CC_RECEIVE_BRDCAST_NLINE: + { + // initialize dspin received data + uint64_t receive_data = p_dspin_m2p.data.read(); + // wait for both dcache and icache to take the request + // TODO maybe we need to wait for both only to leave the state, but + // not to actually post a request to an available cache => need a + // flip_flop to check that ? + if (not (r_cc_receive_icache_req.read()) and + not (r_cc_receive_dcache_req.read()) and + (p_dspin_m2p.write.read())) + { + // request dcache to handle the BROADCAST + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, + DspinDhccpParam::BROADCAST_NLINE); + r_cc_receive_dcache_type = CC_TYPE_INVAL; + // request icache to handle the BROADCAST + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, + DspinDhccpParam::BROADCAST_NLINE); + r_cc_receive_icache_type = CC_TYPE_INVAL; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + // keep waiting for the caches to accept the request + break; + } + ///////////////////////////// + case CC_RECEIVE_DATA_INVAL_HEADER: + { + // sample updt tab index in the HEADER, then skip to second flit + r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE; + break; + } + ///////////////////////////// + case CC_RECEIVE_INS_INVAL_HEADER: + { + // sample updt tab index in the HEADER, then skip to second flit + r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE; + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_INVAL_NLINE: + { + // sample nline in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for data INVAL, wait for dcache to take the request + if (p_dspin_m2p.write.read() and + not r_cc_receive_dcache_req.read() ) + { + // request dcache to handle the INVAL + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); + r_cc_receive_dcache_type = CC_TYPE_INVAL; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + break; + } + ////////////////////////////// + case CC_RECEIVE_INS_INVAL_NLINE: + { + // sample nline in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for ins INVAL, wait for icache to take the request + if (p_dspin_m2p.write.read() and + not r_cc_receive_icache_req.read() ) + { + // request icache to handle the INVAL + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); + r_cc_receive_icache_type = CC_TYPE_INVAL; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_UPDT_HEADER: + { + // sample updt tab index in the HEADER, than skip to second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for data INVAL, wait for dcache to take the request and fifo to + // be empty + if (not r_cc_receive_dcache_req.read()) + { + r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; + break; + } + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_HEADER: + { + // sample updt tab index in the HEADER, than skip to second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for ins INVAL, wait for icache to take the request and fifo to be + // empty + if (not r_cc_receive_icache_req.read()) + { + r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; + break; + } + // keep waiting for the correct cache to accept the request + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_NLINE: + { + // sample nline and word index in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for data INVAL, wait for dcache to take the request and fifo to + // be empty + if ( r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read() ) + { + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_dcache_type = CC_TYPE_UPDT; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA; + break; + } + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_NLINE: + { + // sample nline and word index in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for ins INVAL, wait for icache to take the request and fifo to be + // empty + if ( r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read() ) + { + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_icache_type = CC_TYPE_UPDT; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA; + break; + } + break; + } + ////////////////////////// + case CC_RECEIVE_DATA_UPDT_DATA: + { + // wait for the fifo + if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) + { + uint64_t receive_data = p_dspin_m2p.data.read(); + bool receive_eop = p_dspin_m2p.eop.read(); + cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); + cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); + cc_receive_updt_fifo_eop = receive_eop; + cc_receive_updt_fifo_put = true; + if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + } + break; + } + ////////////////////////// + case CC_RECEIVE_INS_UPDT_DATA: + { + // wait for the fifo + if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) + { + uint64_t receive_data = p_dspin_m2p.data.read(); + bool receive_eop = p_dspin_m2p.eop.read(); + cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); + cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); + cc_receive_updt_fifo_eop = receive_eop; + cc_receive_updt_fifo_put = true; + if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + } + break; + } + + } // end switch CC_RECEIVE FSM + + ///////////////// DSPIN CLACK interface /////////////// + + uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_WAY); + + size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_SET); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: Send request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()){ + r_dcache_clack_req = true; + r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); + dspin_clack_get = true; + } + + // CLACK INST: Send request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()){ + r_icache_clack_req = true; + r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1); + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + if (dspin_clack_get) + { + r_dspin_clack_req = p_dspin_clack.write.read(); + r_dspin_clack_flit = p_dspin_clack.data.read(); + } + + ///////////////// Response FIFOs update ////////////////////// + r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, + vci_rsp_fifo_icache_put, + vci_rsp_fifo_icache_data); + + r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get, + vci_rsp_fifo_dcache_put, + vci_rsp_fifo_dcache_data); + + ///////////////// updt FIFO update ////////////////////// + //TODO check this + r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get, + cc_receive_updt_fifo_put, + cc_receive_updt_fifo_be); + r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get, + cc_receive_updt_fifo_put, + cc_receive_updt_fifo_data); + r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get, + cc_receive_updt_fifo_put, + cc_receive_updt_fifo_eop); + +} // end transition() + +/////////////////////// +tmpl(void)::genMoore() +/////////////////////// +{ + + // VCI initiator command on the direct network + // it depends on the CMD FSM state + + bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or + (r_vci_cmd_fsm.read() == CMD_DATA_SC ); + + p_vci.pktid = 0; + p_vci.srcid = m_srcid; + p_vci.cons = is_sc_or_cas; + p_vci.contig = not is_sc_or_cas; + p_vci.wrap = false; + p_vci.clen = 0; + p_vci.cfixed = false; + + if ( m_monitor_ok ) { + if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) { + if (((p_vci.address.read()) >= m_monitor_base) and + ((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) { + std::cout << "CC_VCACHE Monitor " << name() << std::hex + << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] + << " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()] + << " : address = " << p_vci.address.read() + << " / be = " << p_vci.be.read(); + if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) { + std::cout << " / data = " << p_vci.wdata.read(); + } + std::cout << std::dec << std::endl; + } + } + } + + switch ( r_vci_cmd_fsm.read() ) { + + case CMD_IDLE: + p_vci.cmdval = false; + p_vci.address = 0; + p_vci.wdata = 0; + p_vci.be = 0; + p_vci.trdid = 0; + p_vci.pktid = 0; + p_vci.plen = 0; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = false; + break; + + case CMD_INS_MISS: + p_vci.cmdval = true; + p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_INS_MISS; + p_vci.plen = m_icache_words<<2; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_INS_UNC: + p_vci.cmdval = true; + p_vci.address = r_icache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_INS_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_DATA_MISS: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_DATA_MISS; + p_vci.plen = m_dcache_words << 2; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_DATA_UNC_READ: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = r_dcache_vci_unc_be.read(); + p_vci.trdid = 0; + p_vci.pktid = TYPE_DATA_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_DATA_UNC_WRITE: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = r_dcache_vci_wdata.read(); + p_vci.be = r_dcache_vci_unc_be.read(); + p_vci.trdid = 0; + p_vci.pktid = TYPE_DATA_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_WRITE; + p_vci.eop = true; + break; + + case CMD_DATA_WRITE: + p_vci.cmdval = true; + p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; + p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); + p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); + p_vci.trdid = r_wbuf.getIndex(); + p_vci.pktid = TYPE_WRITE; + p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; + p_vci.cmd = vci_param::CMD_WRITE; + p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); + break; + + case CMD_DATA_LL: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_LL; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_LOCKED_READ; + p_vci.eop = true; + break; + + case CMD_DATA_SC: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read(); + else p_vci.wdata = r_dcache_vci_sc_data.read(); + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_SC; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = (r_vci_cmd_cpt.read() == 1); + break; + + case CMD_DATA_CAS: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read(); + else p_vci.wdata = r_dcache_vci_cas_new.read(); + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_CAS; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = (r_vci_cmd_cpt.read() == 1); + break; + } // end switch r_vci_cmd_fsm + + // VCI initiator response on the direct network + // it depends on the VCI_RSP FSM + + switch (r_vci_rsp_fsm.read() ) + { + case RSP_DATA_WRITE : p_vci.rspack = true; break; + case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; + case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; + case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_IDLE : p_vci.rspack = false; break; + } // end switch r_vci_rsp_fsm + + + // Send coherence packets on DSPIN P2M + // it depends on the CC_SEND FSM + + uint64_t dspin_send_data = 0; + switch ( r_cc_send_fsm.read() ) + { + ////////////////// + case CC_SEND_IDLE: + { + p_dspin_p2m.write = false; + break; + } + /////////////////////// + case CC_SEND_CLEANUP_1: + { + // initialize dspin send data +// DspinDhccpParam::dspin_set(dspin_send_data, +// 0, +// DspinDhccpParam::P2M_EOP); + DspinDhccpParam::dspin_set(dspin_send_data, + m_cc_global_id, + DspinDhccpParam::CLEANUP_SRCID); + DspinDhccpParam::dspin_set(dspin_send_data, + 0, + DspinDhccpParam::P2M_BC); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::CLEANUP_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32, + DspinDhccpParam::CLEANUP_NLINE_MSB); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_dcache_cc_send_way.read(), + DspinDhccpParam::CLEANUP_WAY_INDEX); + + DspinDhccpParam::dspin_set(dspin_send_data, + DspinDhccpParam::TYPE_CLEANUP_DATA, + DspinDhccpParam::P2M_TYPE); + } + else // icache active request + { + uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::CLEANUP_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32, + DspinDhccpParam::CLEANUP_NLINE_MSB); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_icache_cc_send_way.read(), + DspinDhccpParam::CLEANUP_WAY_INDEX); + + DspinDhccpParam::dspin_set(dspin_send_data, + DspinDhccpParam::TYPE_CLEANUP_INST, + DspinDhccpParam::P2M_TYPE); + } + // send flit + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = false; + break; + } + /////////////////////// + case CC_SEND_CLEANUP_2: + { + // initialize dspin send data +// DspinDhccpParam::dspin_set(dspin_send_data, +// 1, +// DspinDhccpParam::P2M_EOP); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + DspinDhccpParam::dspin_set(dspin_send_data, + r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinDhccpParam::CLEANUP_NLINE_LSB); + } + else // icache active request + { + DspinDhccpParam::dspin_set(dspin_send_data, + r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinDhccpParam::CLEANUP_NLINE_LSB); + } + // send flit + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = true; + break; + } + /////////////////////// + case CC_SEND_MULTI_ACK: + { + // initialize dspin send data +// DspinDhccpParam::dspin_set(dspin_send_data, +// 1, +// DspinDhccpParam::P2M_EOP); + DspinDhccpParam::dspin_set(dspin_send_data, + 0, + DspinDhccpParam::P2M_BC); + DspinDhccpParam::dspin_set(dspin_send_data, + DspinDhccpParam::TYPE_MULTI_ACK, + DspinDhccpParam::P2M_TYPE); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::MULTI_ACK_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_dcache_cc_send_updt_tab_idx.read(), + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + } + else // icache active request + { + uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::MULTI_ACK_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_icache_cc_send_updt_tab_idx.read(), + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + } + // send flit + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = true; + + break; + } + } // end switch CC_SEND FSM + + // Receive coherence packets + // It depends on the CC_RECEIVE FSM + switch( r_cc_receive_fsm.read() ) + { + ///////////////////// + case CC_RECEIVE_IDLE: + { + p_dspin_m2p.read = false; + break; + } + /////////////////////////////// + case CC_RECEIVE_BRDCAST_HEADER: + { + p_dspin_m2p.read = true; + break; + } + ////////////////////////////// + case CC_RECEIVE_BRDCAST_NLINE: + { + // TODO maybe we need to wait for both only to leave the state, but + // not to actually post a request to an available cache => need a + // flip_flop to check that ? + if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read())) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + ///////////////////////////// + case CC_RECEIVE_DATA_INVAL_HEADER: + case CC_RECEIVE_INS_INVAL_HEADER: + { + p_dspin_m2p.read = true; + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_INVAL_NLINE: + { + p_dspin_m2p.read = not r_cc_receive_dcache_req.read(); + break; + } + case CC_RECEIVE_INS_INVAL_NLINE: + { + p_dspin_m2p.read = not r_cc_receive_icache_req.read(); + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_HEADER: + { + if (not r_cc_receive_dcache_req.read()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_HEADER: + { + if ( not r_cc_receive_icache_req.read()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_NLINE: + case CC_RECEIVE_INS_UPDT_NLINE: + { + if(r_cc_receive_updt_fifo_be.empty()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_DATA: + case CC_RECEIVE_INS_UPDT_DATA: + { + if (r_cc_receive_updt_fifo_be.wok()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + } // end switch CC_RECEIVE FSM + + + int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: wait if pending request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()) + { + dspin_clack_get = true; + } + + // CLACK INST: wait if pending request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()) + { + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + p_dspin_clack.read = dspin_clack_get; +} // end genMoore + +tmpl(void)::start_monitor(paddr_t base, paddr_t length) +// This version of monitor print both Read and Write request +{ + m_monitor_ok = true; + m_monitor_base = base; + m_monitor_length = length; +} + +tmpl(void)::stop_monitor() +{ + m_monitor_ok = false; +} + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 647) @@ -0,0 +1,77 @@ + +# -*- python -*- + +__id__ = "$Id: vci_mem_cache.sd 295 2013-02-14 15:05:05Z cfuguet $" +__version__ = "$Revision: 295 $" + +Module('caba:vci_mem_cache', + classname = 'soclib::caba::VciMemCache', + + tmpl_parameters = [ + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('memc_cell_size_int') + ), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('memc_cell_size_ext') + ), + parameter.Int('dspin_in_width'), + parameter.Int('dspin_out_width'), + ], + + header_files = [ + '../source/include/vci_mem_cache.h', + '../source/include/xram_transaction.h', + '../source/include/mem_cache_directory.h', + '../source/include/update_tab.h' + ], + + interface_files = [ + '../../include/soclib/mem_cache.h', + ], + + implementation_files = [ + '../source/src/vci_mem_cache.cpp' + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:loader'), + Uses('common:mapping_table'), + Uses('caba:generic_fifo'), + Uses('caba:generic_llsc_global_table'), + Uses('caba:dspin_dhccp_param') + ], + + ports = [ + Port('caba:clock_in' , 'p_clk' , auto = 'clock' ), + Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), + Port('caba:vci_target' , 'p_vci_tgt'), + Port('caba:vci_initiator', 'p_vci_ixr'), + Port('caba:dspin_input', + 'p_dspin_p2m', + dspin_data_size = parameter.Reference('dspin_in_width') + ), + Port('caba:dspin_output', + 'p_dspin_m2p', + dspin_data_size = parameter.Reference('dspin_out_width') + ), + Port('caba:dspin_output', + 'p_dspin_clack', + dspin_data_size = parameter.Reference('dspin_out_width') + ), + ], + + instance_parameters = [ + parameter.Module('mtp', 'common:mapping_table'), + parameter.Module('mtc', 'common:mapping_table'), + parameter.Module('mtx', 'common:mapping_table'), + parameter.IntTab('vci_ixr_index'), + parameter.IntTab('vci_ini_index'), + parameter.IntTab('vci_tgt_index'), + parameter.IntTab('vci_tgt_index_cleanup'), + parameter.Int ('nways'), + parameter.Int ('nsets'), + parameter.Int ('nwords'), + parameter.Int ('heap_size'), + ], +) Index: branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 647) @@ -0,0 +1,737 @@ +#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_H +#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_H + +#include +#include +#include +#include "arithmetics.h" + +//#define RANDOM_EVICTION + +namespace soclib { namespace caba { + + using namespace sc_core; + + //////////////////////////////////////////////////////////////////////// + // A LRU entry + //////////////////////////////////////////////////////////////////////// + class LruEntry { + + public: + + bool recent; + + void init() + { + recent=false; + } + + }; // end class LruEntry + + //////////////////////////////////////////////////////////////////////// + // An Owner + //////////////////////////////////////////////////////////////////////// + class Owner{ + + public: + // Fields + bool inst; // Is the owner an ICache ? + size_t srcid; // The SRCID of the owner + + //////////////////////// + // Constructors + //////////////////////// + Owner(bool i_inst, + size_t i_srcid) + { + inst = i_inst; + srcid = i_srcid; + } + + Owner(const Owner &a) + { + inst = a.inst; + srcid = a.srcid; + } + + Owner() + { + inst = false; + srcid = 0; + } + // end constructors + + }; // end class Owner + + + //////////////////////////////////////////////////////////////////////// + // A directory entry + //////////////////////////////////////////////////////////////////////// + class DirectoryEntry { + + typedef uint32_t tag_t; + + public: + + bool valid; // entry valid + bool is_cnt; // directory entry is in counter mode + bool dirty; // entry dirty + bool lock; // entry locked + tag_t tag; // tag of the entry + size_t count; // number of copies + Owner owner; // an owner of the line + size_t ptr; // pointer to the next owner + + DirectoryEntry() + { + valid = false; + is_cnt = false; + dirty = false; + lock = false; + tag = 0; + count = 0; + owner.inst = 0; + owner.srcid = 0; + ptr = 0; + } + + DirectoryEntry(const DirectoryEntry &source) + { + valid = source.valid; + is_cnt = source.is_cnt; + dirty = source.dirty; + lock = source.lock; + tag = source.tag; + count = source.count; + owner = source.owner; + ptr = source.ptr; + } + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the entry + ///////////////////////////////////////////////////////////////////// + void init() + { + valid = false; + is_cnt = false; + dirty = false; + lock = false; + count = 0; + } + + ///////////////////////////////////////////////////////////////////// + // The copy() function copies an existing source entry to a target + ///////////////////////////////////////////////////////////////////// + void copy(const DirectoryEntry &source) + { + valid = source.valid; + is_cnt = source.is_cnt; + dirty = source.dirty; + lock = source.lock; + tag = source.tag; + count = source.count; + owner = source.owner; + ptr = source.ptr; + } + + //////////////////////////////////////////////////////////////////// + // The print() function prints the entry + //////////////////////////////////////////////////////////////////// + void print() + { + std::cout << "Valid = " << valid + << " ; IS COUNT = " << is_cnt + << " ; Dirty = " << dirty + << " ; Lock = " << lock + << " ; Tag = " << std::hex << tag << std::dec + << " ; Count = " << count + << " ; Owner = " << owner.srcid + << " " << owner.inst + << " ; Pointer = " << ptr << std::endl; + } + + }; // end class DirectoryEntry + + //////////////////////////////////////////////////////////////////////// + // The directory + //////////////////////////////////////////////////////////////////////// + class CacheDirectory { + + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t tag_t; + + private: + + // Directory constants + size_t m_ways; + size_t m_sets; + size_t m_words; + size_t m_width; + uint32_t lfsr; + + // the directory & lru tables + DirectoryEntry **m_dir_tab; + LruEntry **m_lru_tab; + + public: + + //////////////////////// + // Constructor + //////////////////////// + CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width) + { + m_ways = ways; + m_sets = sets; + m_words = words; + m_width = address_width; + lfsr = -1; + + m_dir_tab = new DirectoryEntry*[sets]; + for ( size_t i=0; i> (L2(m_words) + 2)) & (m_sets - 1); + const tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); +#undef L2 + + bool hit = false; + for ( size_t i=0 ; i> (L2(m_words) + 2)) & (m_sets - 1); + tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); +#undef L2 + + for ( size_t way = 0 ; way < m_ways ; way++ ) + { + bool equal = ( m_dir_tab[set][way].tag == tag ); + bool valid = m_dir_tab[set][way].valid; + if ( equal and valid ) + { + *ret_set = set; + *ret_way = way; + return DirectoryEntry(m_dir_tab[set][way]); + } + } + return DirectoryEntry(); + } // end read_neutral() + + ///////////////////////////////////////////////////////////////////// + // The write function writes a new entry, + // and updates the LRU bits if necessary. + // Arguments : + // - set : the set of the entry + // - way : the way of the entry + // - entry : the entry value + ///////////////////////////////////////////////////////////////////// + void write( const size_t &set, + const size_t &way, + const DirectoryEntry &entry) + { + assert( (set> 1) ^ ((-(lfsr & 1)) & 0xd0000001); + way = lfsr % m_ways; + return DirectoryEntry(m_dir_tab[set][way]); +#endif + + // looking for a not locked and not recently used entry + for(size_t i=0; i0 && "Memory Cache, HeapDirectory constructor : invalid size"); + ptr_free = 0; + full = false; + m_heap_tab = new HeapEntry[size]; + tab_size = size; + } // end constructor + + ///////////////// + // Destructor + ///////////////// + ~HeapDirectory(){ + delete [] m_heap_tab; + } // end destructor + + ///////////////////////////////////////////////////////////////////// + // Global initialisation function + ///////////////////////////////////////////////////////////////////// + void init(){ + ptr_free=0; + full=false; + for(size_t i=0; i< tab_size-1;i++){ + m_heap_tab[i].next = i+1; + } + m_heap_tab[tab_size-1].next = tab_size-1; + return; + } + + ///////////////////////////////////////////////////////////////////// + // The print() function prints a selected directory entry + // Arguments : + // - ptr : the pointer to the entry to print + ///////////////////////////////////////////////////////////////////// + void print(const size_t &ptr){ + std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl; + m_heap_tab[ptr].print(); + } // end print() + + ///////////////////////////////////////////////////////////////////// + // The print_list() function prints a list from selected directory entry + // Arguments : + // - ptr : the pointer to the first entry to print + ///////////////////////////////////////////////////////////////////// + void print_list(const size_t &ptr){ + bool end = false; + size_t ptr_temp = ptr; + std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl; + while(!end){ + m_heap_tab[ptr_temp].print(); + if(ptr_temp == m_heap_tab[ptr_temp].next) end = true; + ptr_temp = m_heap_tab[ptr_temp].next; + } + } // end print_list() + + ///////////////////////////////////////////////////////////////////// + // The is_full() function return true if the heap is full. + ///////////////////////////////////////////////////////////////////// + bool is_full(){ + return full; + } // end is_full() + + ///////////////////////////////////////////////////////////////////// + // The next_free_ptr() function returns the pointer + // to the next free entry. + ///////////////////////////////////////////////////////////////////// + size_t next_free_ptr(){ + return ptr_free; + } // end next_free_ptr() + + ///////////////////////////////////////////////////////////////////// + // The next_free_entry() function returns + // a copy of the next free entry. + ///////////////////////////////////////////////////////////////////// + HeapEntry next_free_entry(){ + return HeapEntry(m_heap_tab[ptr_free]); + } // end next_free_entry() + + ///////////////////////////////////////////////////////////////////// + // The write_free_entry() function modify the next free entry. + // Arguments : + // - entry : the entry to write + ///////////////////////////////////////////////////////////////////// + void write_free_entry(const HeapEntry &entry){ + m_heap_tab[ptr_free].copy(entry); + } // end write_free_entry() + + ///////////////////////////////////////////////////////////////////// + // The write_free_ptr() function writes the pointer + // to the next free entry + ///////////////////////////////////////////////////////////////////// + void write_free_ptr(const size_t &ptr){ + assert( (ptr * cache_line) + { + assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); + assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); + + for (uint32_t word=0; word +#include +#include +#include "arithmetics.h" + +//////////////////////////////////////////////////////////////////////// +// An update tab entry +//////////////////////////////////////////////////////////////////////// +class UpdateTabEntry { + + typedef uint32_t size_t; + typedef sc_dt::sc_uint<40> addr_t; + + public: + + bool valid; // It is a valid pending transaction + bool update; // It is an update transaction + bool brdcast; // It is a broadcast invalidate + bool rsp; // Response to the initiator required + bool ack; // Acknowledge to the CONFIG FSM required + size_t srcid; // The srcid of the initiator which wrote the data + size_t trdid; // The trdid of the initiator which wrote the data + size_t pktid; // The pktid of the initiator which wrote the data + addr_t nline; // The identifier of the cache line + size_t count; // The number of acknowledge responses to receive + + UpdateTabEntry() + { + valid = false; + update = false; + brdcast = false; + rsp = false; + ack = false; + srcid = 0; + trdid = 0; + pktid = 0; + nline = 0; + count = 0; + } + + UpdateTabEntry(bool i_valid, + bool i_update, + bool i_brdcast, + bool i_rsp, + bool i_ack, + size_t i_srcid, + size_t i_trdid, + size_t i_pktid, + addr_t i_nline, + size_t i_count) + { + valid = i_valid; + update = i_update; + brdcast = i_brdcast; + rsp = i_rsp; + ack = i_ack; + srcid = i_srcid; + trdid = i_trdid; + pktid = i_pktid; + nline = i_nline; + count = i_count; + } + + UpdateTabEntry(const UpdateTabEntry &source) + { + valid = source.valid; + update = source.update; + brdcast = source.brdcast; + rsp = source.rsp; + ack = source.ack; + srcid = source.srcid; + trdid = source.trdid; + pktid = source.pktid; + nline = source.nline; + count = source.count; + } + + //////////////////////////////////////////////////// + // The init() function initializes the entry + /////////////////////////////////////////////////// + void init() + { + valid = false; + update = false; + brdcast= false; + rsp = false; + ack = false; + srcid = 0; + trdid = 0; + pktid = 0; + nline = 0; + count = 0; + } + + //////////////////////////////////////////////////////////////////// + // The copy() function copies an existing entry + // Its arguments are : + // - source : the update tab entry to copy + //////////////////////////////////////////////////////////////////// + void copy(const UpdateTabEntry &source) + { + valid = source.valid; + update = source.update; + brdcast= source.brdcast; + rsp = source.rsp; + ack = source.ack ; + srcid = source.srcid; + trdid = source.trdid; + pktid = source.pktid; + nline = source.nline; + count = source.count; + } + + //////////////////////////////////////////////////////////////////// + // The print() function prints the entry + //////////////////////////////////////////////////////////////////// + void print() + { + std::cout << " val = " << std::dec << valid + << " / updt = " << update + << " / bc = " << brdcast + << " / rsp = " << rsp + << " / ack = " << ack + << " / count = " << count + << " / srcid = " << std::hex << srcid + << " / trdid = " << trdid + << " / pktid = " << pktid + << " / nline = " << nline << std::endl; + } +}; + +//////////////////////////////////////////////////////////////////////// +// The update tab +//////////////////////////////////////////////////////////////////////// +class UpdateTab{ + + typedef uint64_t addr_t; + + private: + size_t size_tab; + std::vector tab; + + public: + + UpdateTab() + : tab(0) + { + size_tab=0; + } + + UpdateTab(size_t size_tab_i) + : tab(size_tab_i) + { + size_tab=size_tab_i; + } + + //////////////////////////////////////////////////////////////////// + // The size() function returns the size of the tab + //////////////////////////////////////////////////////////////////// + const size_t size() + { + return size_tab; + } + + //////////////////////////////////////////////////////////////////// + // The print() function diplays the tab content + //////////////////////////////////////////////////////////////////// + void print() + { + std::cout << "UPDATE TABLE Content" << std::endl; + for(size_t i=0; i +#include +#include +#include +#include "arithmetics.h" +#include "alloc_elems.h" +#include "caba_base_module.h" +#include "vci_target.h" +#include "vci_initiator.h" +#include "generic_fifo.h" +#include "mapping_table.h" +#include "int_tab.h" +#include "generic_llsc_global_table.h" +#include "mem_cache_directory.h" +#include "xram_transaction.h" +#include "update_tab.h" +#include "dspin_interface.h" +#include "dspin_dhccp_param.h" + +#define TRT_ENTRIES 4 // Number of entries in TRT +#define UPT_ENTRIES 4 // Number of entries in UPT +#define IVT_ENTRIES 4 // Number of entries in IVT +#define HEAP_ENTRIES 1024 // Number of entries in HEAP + +namespace soclib { namespace caba { + + using namespace sc_core; + + template + class VciMemCache + : public soclib::caba::BaseModule + { + typedef typename vci_param_int::fast_addr_t addr_t; + typedef typename sc_dt::sc_uint<64> wide_data_t; + typedef uint32_t data_t; + typedef uint32_t tag_t; + typedef uint32_t be_t; + typedef uint32_t copy_t; + + /* States of the TGT_CMD fsm */ + enum tgt_cmd_fsm_state_e + { + TGT_CMD_IDLE, + TGT_CMD_READ, + TGT_CMD_WRITE, + TGT_CMD_CAS, + TGT_CMD_CONFIG, + TGT_CMD_ERROR + }; + + /* States of the TGT_RSP fsm */ + enum tgt_rsp_fsm_state_e + { + TGT_RSP_READ_IDLE, + TGT_RSP_WRITE_IDLE, + TGT_RSP_CAS_IDLE, + TGT_RSP_XRAM_IDLE, + TGT_RSP_MULTI_ACK_IDLE, + TGT_RSP_CLEANUP_IDLE, + TGT_RSP_TGT_CMD_IDLE, + TGT_RSP_CONFIG_IDLE, + TGT_RSP_READ, + TGT_RSP_WRITE, + TGT_RSP_CAS, + TGT_RSP_XRAM, + TGT_RSP_MULTI_ACK, + TGT_RSP_CLEANUP, + TGT_RSP_TGT_CMD, + TGT_RSP_CONFIG + }; + + /* States of the DSPIN_TGT fsm */ + enum cc_receive_fsm_state_e + { + CC_RECEIVE_IDLE, + CC_RECEIVE_CLEANUP, + CC_RECEIVE_CLEANUP_EOP, + CC_RECEIVE_MULTI_ACK + }; + + /* States of the CC_SEND fsm */ + enum cc_send_fsm_state_e + { + CC_SEND_XRAM_RSP_IDLE, + CC_SEND_WRITE_IDLE, + CC_SEND_CAS_IDLE, + CC_SEND_CONFIG_IDLE, + CC_SEND_XRAM_RSP_BRDCAST_HEADER, + CC_SEND_XRAM_RSP_BRDCAST_NLINE, + CC_SEND_XRAM_RSP_INVAL_HEADER, + CC_SEND_XRAM_RSP_INVAL_NLINE, + CC_SEND_WRITE_BRDCAST_HEADER, + CC_SEND_WRITE_BRDCAST_NLINE, + CC_SEND_WRITE_UPDT_HEADER, + CC_SEND_WRITE_UPDT_NLINE, + CC_SEND_WRITE_UPDT_DATA, + CC_SEND_CAS_BRDCAST_HEADER, + CC_SEND_CAS_BRDCAST_NLINE, + CC_SEND_CAS_UPDT_HEADER, + CC_SEND_CAS_UPDT_NLINE, + CC_SEND_CAS_UPDT_DATA, + CC_SEND_CAS_UPDT_DATA_HIGH, + CC_SEND_CONFIG_INVAL_HEADER, + CC_SEND_CONFIG_INVAL_NLINE, + CC_SEND_CONFIG_BRDCAST_HEADER, + CC_SEND_CONFIG_BRDCAST_NLINE + }; + + /* States of the MULTI_ACK fsm */ + enum multi_ack_fsm_state_e + { + MULTI_ACK_IDLE, + MULTI_ACK_UPT_LOCK, + MULTI_ACK_UPT_CLEAR, + MULTI_ACK_WRITE_RSP + }; + + /* States of the CONFIG fsm */ + enum config_fsm_state_e + { + CONFIG_IDLE, + CONFIG_LOOP, + CONFIG_WAIT, + CONFIG_RSP, + CONFIG_DIR_REQ, + CONFIG_DIR_ACCESS, + CONFIG_IVT_LOCK, + CONFIG_BC_SEND, + CONFIG_INVAL_SEND, + CONFIG_HEAP_REQ, + CONFIG_HEAP_SCAN, + CONFIG_HEAP_LAST, + CONFIG_TRT_LOCK, + CONFIG_TRT_SET, + CONFIG_PUT_REQ + }; + + /* States of the READ fsm */ + enum read_fsm_state_e + { + READ_IDLE, + READ_DIR_REQ, + READ_DIR_LOCK, + READ_DIR_HIT, + READ_HEAP_REQ, + READ_HEAP_LOCK, + READ_HEAP_WRITE, + READ_HEAP_ERASE, + READ_HEAP_LAST, + READ_RSP, + READ_TRT_LOCK, + READ_TRT_SET, + READ_TRT_REQ + }; + + /* States of the WRITE fsm */ + enum write_fsm_state_e + { + WRITE_IDLE, + WRITE_NEXT, + WRITE_DIR_REQ, + WRITE_DIR_LOCK, + WRITE_DIR_HIT, + WRITE_UPT_LOCK, + WRITE_UPT_HEAP_LOCK, + WRITE_UPT_REQ, + WRITE_UPT_NEXT, + WRITE_UPT_DEC, + WRITE_RSP, + WRITE_MISS_TRT_LOCK, + WRITE_MISS_TRT_DATA, + WRITE_MISS_TRT_SET, + WRITE_MISS_XRAM_REQ, + WRITE_BC_DIR_READ, + WRITE_BC_TRT_LOCK, + WRITE_BC_IVT_LOCK, + WRITE_BC_DIR_INVAL, + WRITE_BC_CC_SEND, + WRITE_BC_XRAM_REQ, + WRITE_WAIT + }; + + /* States of the IXR_RSP fsm */ + enum ixr_rsp_fsm_state_e + { + IXR_RSP_IDLE, + IXR_RSP_TRT_ERASE, + IXR_RSP_TRT_READ + }; + + /* States of the XRAM_RSP fsm */ + enum xram_rsp_fsm_state_e + { + XRAM_RSP_IDLE, + XRAM_RSP_TRT_COPY, + XRAM_RSP_TRT_DIRTY, + XRAM_RSP_DIR_LOCK, + XRAM_RSP_DIR_UPDT, + XRAM_RSP_DIR_RSP, + XRAM_RSP_IVT_LOCK, + XRAM_RSP_INVAL_WAIT, + XRAM_RSP_INVAL, + XRAM_RSP_WRITE_DIRTY, + XRAM_RSP_HEAP_REQ, + XRAM_RSP_HEAP_ERASE, + XRAM_RSP_HEAP_LAST, + XRAM_RSP_ERROR_ERASE, + XRAM_RSP_ERROR_RSP + }; + + /* States of the IXR_CMD fsm */ + enum ixr_cmd_fsm_state_e + { + IXR_CMD_READ_IDLE, + IXR_CMD_WRITE_IDLE, + IXR_CMD_CAS_IDLE, + IXR_CMD_XRAM_IDLE, + IXR_CMD_CONFIG_IDLE, + IXR_CMD_READ_TRT, + IXR_CMD_WRITE_TRT, + IXR_CMD_CAS_TRT, + IXR_CMD_XRAM_TRT, + IXR_CMD_CONFIG_TRT, + IXR_CMD_READ_SEND, + IXR_CMD_WRITE_SEND, + IXR_CMD_CAS_SEND, + IXR_CMD_XRAM_SEND, + IXR_CMD_CONFIG_SEND + }; + + /* States of the CAS fsm */ + enum cas_fsm_state_e + { + CAS_IDLE, + CAS_DIR_REQ, + CAS_DIR_LOCK, + CAS_DIR_HIT_READ, + CAS_DIR_HIT_COMPARE, + CAS_DIR_HIT_WRITE, + CAS_UPT_LOCK, + CAS_UPT_HEAP_LOCK, + CAS_UPT_REQ, + CAS_UPT_NEXT, + CAS_BC_TRT_LOCK, + CAS_BC_IVT_LOCK, + CAS_BC_DIR_INVAL, + CAS_BC_CC_SEND, + CAS_BC_XRAM_REQ, + CAS_RSP_FAIL, + CAS_RSP_SUCCESS, + CAS_MISS_TRT_LOCK, + CAS_MISS_TRT_SET, + CAS_MISS_XRAM_REQ, + CAS_WAIT + }; + + /* States of the CLEANUP fsm */ + enum cleanup_fsm_state_e + { + CLEANUP_IDLE, + CLEANUP_GET_NLINE, + CLEANUP_DIR_REQ, + CLEANUP_DIR_LOCK, + CLEANUP_DIR_WRITE, + CLEANUP_HEAP_REQ, + CLEANUP_HEAP_LOCK, + CLEANUP_HEAP_SEARCH, + CLEANUP_HEAP_CLEAN, + CLEANUP_HEAP_FREE, + CLEANUP_IVT_LOCK, + CLEANUP_IVT_DECREMENT, + CLEANUP_IVT_CLEAR, + CLEANUP_WRITE_RSP, + CLEANUP_SEND_CLACK + }; + + /* States of the ALLOC_DIR fsm */ + enum alloc_dir_fsm_state_e + { + ALLOC_DIR_RESET, + ALLOC_DIR_READ, + ALLOC_DIR_WRITE, + ALLOC_DIR_CAS, + ALLOC_DIR_CLEANUP, + ALLOC_DIR_XRAM_RSP, + ALLOC_DIR_CONFIG + }; + + /* States of the ALLOC_TRT fsm */ + enum alloc_trt_fsm_state_e + { + ALLOC_TRT_READ, + ALLOC_TRT_WRITE, + ALLOC_TRT_CAS, + ALLOC_TRT_XRAM_RSP, + ALLOC_TRT_IXR_RSP, + ALLOC_TRT_IXR_CMD, + ALLOC_TRT_CONFIG + }; + + /* States of the ALLOC_UPT fsm */ + enum alloc_upt_fsm_state_e + { + ALLOC_UPT_WRITE, + ALLOC_UPT_CAS, + ALLOC_UPT_MULTI_ACK + }; + + /* States of the ALLOC_IVT fsm */ + enum alloc_ivt_fsm_state_e + { + ALLOC_IVT_WRITE, + ALLOC_IVT_XRAM_RSP, + ALLOC_IVT_CLEANUP, + ALLOC_IVT_CAS, + ALLOC_IVT_CONFIG + }; + + /* States of the ALLOC_HEAP fsm */ + enum alloc_heap_fsm_state_e + { + ALLOC_HEAP_RESET, + ALLOC_HEAP_READ, + ALLOC_HEAP_WRITE, + ALLOC_HEAP_CAS, + ALLOC_HEAP_CLEANUP, + ALLOC_HEAP_XRAM_RSP, + ALLOC_HEAP_CONFIG + }; + + /* transaction type, pktid field */ + enum transaction_type_e + { + // b3 unused + // b2 READ / NOT READ + // Si READ + // b1 DATA / INS + // b0 UNC / MISS + // Si NOT READ + // b1 accÚs table llsc type SW / other + // b2 WRITE/CAS/LL/SC + TYPE_READ_DATA_UNC = 0x0, + TYPE_READ_DATA_MISS = 0x1, + TYPE_READ_INS_UNC = 0x2, + TYPE_READ_INS_MISS = 0x3, + TYPE_WRITE = 0x4, + TYPE_CAS = 0x5, + TYPE_LL = 0x6, + TYPE_SC = 0x7 + }; + + /* SC return values */ + enum sc_status_type_e + { + SC_SUCCESS = 0x00000000, + SC_FAIL = 0x00000001 + }; + + // debug variables + bool m_debug; + bool m_debug_previous_valid; + size_t m_debug_previous_count; + bool m_debug_previous_dirty; + data_t * m_debug_previous_data; + data_t * m_debug_data; + + // instrumentation counters + uint32_t m_cpt_cycles; // Counter of cycles + + // Counters accessible in software (not yet but eventually) + uint32_t m_cpt_read_local; // Number of local READ transactions + uint32_t m_cpt_read_remote; // number of remote READ transactions + uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs + + uint32_t m_cpt_write_local; // Number of local WRITE transactions + uint32_t m_cpt_write_remote; // number of remote WRITE transactions + uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs + uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs + uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs + + uint32_t m_cpt_ll_local; // Number of local LL transactions + uint32_t m_cpt_ll_remote; // number of remote LL transactions + uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs + + uint32_t m_cpt_sc_local; // Number of local SC transactions + uint32_t m_cpt_sc_remote; // number of remote SC transactions + uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs + + uint32_t m_cpt_cas_local; // Number of local SC transactions + uint32_t m_cpt_cas_remote; // number of remote SC transactions + uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs + + uint32_t m_cpt_update; // Number of requests causing an UPDATE + uint32_t m_cpt_update_local; // Number of local UPDATE transactions + uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions + uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT + + uint32_t m_cpt_minval; // Number of requests causing M_INV + uint32_t m_cpt_minval_local; // Number of local M_INV transactions + uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions + uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV + + uint32_t m_cpt_binval; // Number of BROADCAST INVAL + + uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions + uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions + uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs + + // Counters not accessible by software + uint32_t m_cpt_read_miss; // Number of MISS READ + uint32_t m_cpt_write_miss; // Number of MISS WRITE + uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions + uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write + + uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt + uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt + + uint32_t m_cpt_get; + uint32_t m_cpt_put; + + size_t m_prev_count; + + protected: + + SC_HAS_PROCESS(VciMemCache); + + public: + sc_in p_clk; + sc_in p_resetn; + sc_out p_irq; + soclib::caba::VciTarget p_vci_tgt; + soclib::caba::VciInitiator p_vci_ixr; + soclib::caba::DspinInput p_dspin_p2m; + soclib::caba::DspinOutput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_clack; + +#if MONITOR_MEMCACHE_FSM == 1 + sc_out p_read_fsm; + sc_out p_write_fsm; + sc_out p_xram_rsp_fsm; + sc_out p_cas_fsm; + sc_out p_cleanup_fsm; + sc_out p_config_fsm; + sc_out p_alloc_heap_fsm; + sc_out p_alloc_dir_fsm; + sc_out p_alloc_trt_fsm; + sc_out p_alloc_upt_fsm; + sc_out p_alloc_ivt_fsm; + sc_out p_tgt_cmd_fsm; + sc_out p_tgt_rsp_fsm; + sc_out p_ixr_cmd_fsm; + sc_out p_ixr_rsp_fsm; + sc_out p_cc_send_fsm; + sc_out p_cc_receive_fsm; + sc_out p_multi_ack_fsm; +#endif + + VciMemCache( + sc_module_name name, // Instance Name + const soclib::common::MappingTable &mtp, // Mapping table INT network + const soclib::common::MappingTable &mtx, // Mapping table RAM network + const soclib::common::IntTab &srcid_x, // global index RAM network + const soclib::common::IntTab &tgtid_d, // global index INT network + const size_t x_width, // X width in platform + const size_t y_width, // Y width in platform + const size_t nways, // Number of ways per set + const size_t nsets, // Number of sets + const size_t nwords, // Number of words per line + const size_t max_copies, // max number of copies + const size_t heap_size=HEAP_ENTRIES, + const size_t trt_lines=TRT_ENTRIES, + const size_t upt_lines=UPT_ENTRIES, + const size_t ivt_lines=IVT_ENTRIES, + const size_t debug_start_cycle=0, + const bool debug_ok=false ); + + ~VciMemCache(); + + void print_stats(bool activity_counters, bool stats); + void print_trace( size_t detailed = 0 ); + void cache_monitor(addr_t addr); + void start_monitor(addr_t addr, addr_t length); + void stop_monitor(); + + private: + + void transition(); + void genMoore(); + void check_monitor(addr_t addr, data_t data, bool read); + + uint32_t req_distance(uint32_t req_srcid); + bool is_local_req(uint32_t req_srcid); + int read_instrumentation(uint32_t regr, uint32_t & rdata); + + // Component attributes + std::list m_seglist; // segments allocated + size_t m_nseg; // number of segments + soclib::common::Segment **m_seg; // array of segments pointers + size_t m_seg_config; // config segment index + const size_t m_srcid_x; // global index on RAM network + const size_t m_initiators; // Number of initiators + const size_t m_heap_size; // Size of the heap + const size_t m_ways; // Number of ways in a set + const size_t m_sets; // Number of cache sets + const size_t m_words; // Number of words in a line + size_t m_x_self; // X self coordinate + size_t m_y_self; // Y self coordinate + const size_t m_x_width; // number of x bits in platform + const size_t m_y_width; // number of y bits in platform + size_t m_debug_start_cycle; + bool m_debug_ok; + uint32_t m_trt_lines; + TransactionTab m_trt; // xram transaction table + uint32_t m_upt_lines; + UpdateTab m_upt; // pending update + UpdateTab m_ivt; // pending invalidate + CacheDirectory m_cache_directory; // data cache directory + CacheData m_cache_data; // data array[set][way][word] + HeapDirectory m_heap; // heap for copies + size_t m_max_copies; // max number of copies in heap + GenericLLSCGlobalTable + < 32 , // number of slots + 4096, // number of processors in the system + 8000, // registration life (# of LL operations) + addr_t > m_llsc_table; // ll/sc registration table + + // adress masks + const soclib::common::AddressMaskingTable m_x; + const soclib::common::AddressMaskingTable m_y; + const soclib::common::AddressMaskingTable m_z; + const soclib::common::AddressMaskingTable m_nline; + + // broadcast address + uint32_t m_broadcast_boundaries; + + // configuration interface constants + const uint32_t m_config_addr_mask; + const uint32_t m_config_regr_width; + const uint32_t m_config_func_width; + const uint32_t m_config_regr_idx_mask; + const uint32_t m_config_func_idx_mask; + + // Fifo between TGT_CMD fsm and READ fsm + GenericFifo m_cmd_read_addr_fifo; + GenericFifo m_cmd_read_length_fifo; + GenericFifo m_cmd_read_srcid_fifo; + GenericFifo m_cmd_read_trdid_fifo; + GenericFifo m_cmd_read_pktid_fifo; + + // Fifo between TGT_CMD fsm and WRITE fsm + GenericFifo m_cmd_write_addr_fifo; + GenericFifo m_cmd_write_eop_fifo; + GenericFifo m_cmd_write_srcid_fifo; + GenericFifo m_cmd_write_trdid_fifo; + GenericFifo m_cmd_write_pktid_fifo; + GenericFifo m_cmd_write_data_fifo; + GenericFifo m_cmd_write_be_fifo; + + // Fifo between TGT_CMD fsm and CAS fsm + GenericFifo m_cmd_cas_addr_fifo; + GenericFifo m_cmd_cas_eop_fifo; + GenericFifo m_cmd_cas_srcid_fifo; + GenericFifo m_cmd_cas_trdid_fifo; + GenericFifo m_cmd_cas_pktid_fifo; + GenericFifo m_cmd_cas_wdata_fifo; + + // Fifo between CC_RECEIVE fsm and CLEANUP fsm + GenericFifo m_cc_receive_to_cleanup_fifo; + + // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm + GenericFifo m_cc_receive_to_multi_ack_fifo; + + // Buffer between TGT_CMD fsm and TGT_RSP fsm + // (segmentation violation response request) + sc_signal r_tgt_cmd_to_tgt_rsp_req; + + sc_signal r_tgt_cmd_to_tgt_rsp_rdata; + sc_signal r_tgt_cmd_to_tgt_rsp_error; + sc_signal r_tgt_cmd_to_tgt_rsp_srcid; + sc_signal r_tgt_cmd_to_tgt_rsp_trdid; + sc_signal r_tgt_cmd_to_tgt_rsp_pktid; + + sc_signal r_tgt_cmd_config_addr; + sc_signal r_tgt_cmd_config_cmd; + + ////////////////////////////////////////////////// + // Registers controlled by the TGT_CMD fsm + ////////////////////////////////////////////////// + + sc_signal r_tgt_cmd_fsm; + + /////////////////////////////////////////////////////// + // Registers controlled by the CONFIG fsm + /////////////////////////////////////////////////////// + + sc_signal r_config_fsm; // FSM state + sc_signal r_config_lock; // lock protecting exclusive access + sc_signal r_config_cmd; // config request type + sc_signal r_config_address; // target buffer physical address + sc_signal r_config_srcid; // config request srcid + sc_signal r_config_trdid; // config request trdid + sc_signal r_config_pktid; // config request pktid + sc_signal r_config_cmd_lines; // number of lines to be handled + sc_signal r_config_rsp_lines; // number of lines not completed + sc_signal r_config_dir_way; // DIR: selected way + sc_signal r_config_dir_lock; // DIR: locked entry + sc_signal r_config_dir_count; // DIR: number of copies + sc_signal r_config_dir_is_cnt; // DIR: counter mode (broadcast) + sc_signal r_config_dir_copy_srcid; // DIR: first copy SRCID + sc_signal r_config_dir_copy_inst; // DIR: first copy L1 type + sc_signal r_config_dir_ptr; // DIR: index of next copy in HEAP + sc_signal r_config_heap_next; // current pointer to scan HEAP + sc_signal r_config_trt_index; // selected entry in TRT + sc_signal r_config_ivt_index; // selected entry in IVT + + // Buffer between CONFIG fsm and IXR_CMD fsm + sc_signal r_config_to_ixr_cmd_req; // valid request + sc_signal r_config_to_ixr_cmd_index; // TRT index + + // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) + sc_signal r_config_to_tgt_rsp_req; // valid request + sc_signal r_config_to_tgt_rsp_error; // error response + sc_signal r_config_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_config_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_config_to_tgt_rsp_pktid; // Transaction pktid + + // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) + sc_signal r_config_to_cc_send_multi_req; // multi-inval request + sc_signal r_config_to_cc_send_brdcast_req; // broadcast-inval request + sc_signal r_config_to_cc_send_nline; // line index + sc_signal r_config_to_cc_send_trdid; // UPT index + GenericFifo m_config_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_config_to_cc_send_srcid_fifo; // fifo for owners srcid + + /////////////////////////////////////////////////////// + // Registers controlled by the READ fsm + /////////////////////////////////////////////////////// + + sc_signal r_read_fsm; // FSM state + sc_signal r_read_copy; // Srcid of the first copy + sc_signal r_read_copy_cache; // Srcid of the first copy + sc_signal r_read_copy_inst; // Type of the first copy + sc_signal r_read_tag; // cache line tag (in directory) + sc_signal r_read_is_cnt; // is_cnt bit (in directory) + sc_signal r_read_lock; // lock bit (in directory) + sc_signal r_read_dirty; // dirty bit (in directory) + sc_signal r_read_count; // number of copies + sc_signal r_read_ptr; // pointer to the heap + sc_signal * r_read_data; // data (one cache line) + sc_signal r_read_way; // associative way (in cache) + sc_signal r_read_trt_index; // Transaction Table index + sc_signal r_read_next_ptr; // Next entry to point to + sc_signal r_read_last_free; // Last free entry + sc_signal r_read_ll_key; // LL key from llsc_global_table + + // Buffer between READ fsm and IXR_CMD fsm + sc_signal r_read_to_ixr_cmd_req; // valid request + sc_signal r_read_to_ixr_cmd_index; // TRT index + + // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) + sc_signal r_read_to_tgt_rsp_req; // valid request + sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_read_to_tgt_rsp_data; // data (one cache line) + sc_signal r_read_to_tgt_rsp_word; // first word of the response + sc_signal r_read_to_tgt_rsp_length; // length of the response + sc_signal r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table + + /////////////////////////////////////////////////////////////// + // Registers controlled by the WRITE fsm + /////////////////////////////////////////////////////////////// + + sc_signal r_write_fsm; // FSM state + sc_signal r_write_address; // first word address + sc_signal r_write_word_index; // first word index in line + sc_signal r_write_word_count; // number of words in line + sc_signal r_write_srcid; // transaction srcid + sc_signal r_write_trdid; // transaction trdid + sc_signal r_write_pktid; // transaction pktid + sc_signal * r_write_data; // data (one cache line) + sc_signal * r_write_be; // one byte enable per word + sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) + sc_signal r_write_is_cnt; // is_cnt bit (in directory) + sc_signal r_write_lock; // lock bit (in directory) + sc_signal r_write_tag; // cache line tag (in directory) + sc_signal r_write_copy; // first owner of the line + sc_signal r_write_copy_cache; // first owner of the line + sc_signal r_write_copy_inst; // is this owner a ICache ? + sc_signal r_write_count; // number of copies + sc_signal r_write_ptr; // pointer to the heap + sc_signal r_write_next_ptr; // next pointer to the heap + sc_signal r_write_to_dec; // need to decrement update counter + sc_signal r_write_way; // way of the line + sc_signal r_write_trt_index; // index in Transaction Table + sc_signal r_write_upt_index; // index in Update Table + sc_signal r_write_sc_fail; // sc command failed + sc_signal r_write_sc_key; // sc command key + sc_signal r_write_bc_data_we; // Write enable for data buffer + + // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) + sc_signal r_write_to_tgt_rsp_req; // valid request + sc_signal r_write_to_tgt_rsp_srcid; // transaction srcid + sc_signal r_write_to_tgt_rsp_trdid; // transaction trdid + sc_signal r_write_to_tgt_rsp_pktid; // transaction pktid + sc_signal r_write_to_tgt_rsp_sc_fail; // sc command failed + + // Buffer between WRITE fsm and IXR_CMD fsm + sc_signal r_write_to_ixr_cmd_req; // valid request + sc_signal r_write_to_ixr_cmd_index; // TRT index + + // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) + sc_signal r_write_to_cc_send_multi_req; // valid multicast request + sc_signal r_write_to_cc_send_brdcast_req; // valid brdcast request + sc_signal r_write_to_cc_send_nline; // cache line index + sc_signal r_write_to_cc_send_trdid; // index in Update Table + sc_signal * r_write_to_cc_send_data; // data (one cache line) + sc_signal * r_write_to_cc_send_be; // word enable + sc_signal r_write_to_cc_send_count; // number of words in line + sc_signal r_write_to_cc_send_index; // index of first word in line + GenericFifo m_write_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_write_to_cc_send_srcid_fifo; // fifo for srcids + + // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) + sc_signal r_write_to_multi_ack_req; // valid request + sc_signal r_write_to_multi_ack_upt_index; // index in update table + + ///////////////////////////////////////////////////////// + // Registers controlled by MULTI_ACK fsm + ////////////////////////////////////////////////////////// + + sc_signal r_multi_ack_fsm; // FSM state + sc_signal r_multi_ack_upt_index; // index in the Update Table + sc_signal r_multi_ack_srcid; // pending write srcid + sc_signal r_multi_ack_trdid; // pending write trdid + sc_signal r_multi_ack_pktid; // pending write pktid + sc_signal r_multi_ack_nline; // pending write nline + + // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) + sc_signal r_multi_ack_to_tgt_rsp_req; // valid request + sc_signal r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid + + /////////////////////////////////////////////////////// + // Registers controlled by CLEANUP fsm + /////////////////////////////////////////////////////// + + sc_signal r_cleanup_fsm; // FSM state + sc_signal r_cleanup_srcid; // transaction srcid + sc_signal r_cleanup_inst; // Instruction or Data ? + sc_signal r_cleanup_way_index; // L1 Cache Way index + sc_signal r_cleanup_nline; // cache line index + + + sc_signal r_cleanup_copy; // first copy + sc_signal r_cleanup_copy_cache; // first copy + sc_signal r_cleanup_copy_inst; // type of the first copy + sc_signal r_cleanup_count; // number of copies + sc_signal r_cleanup_ptr; // pointer to the heap + sc_signal r_cleanup_prev_ptr; // previous pointer to the heap + sc_signal r_cleanup_prev_srcid; // srcid of previous heap entry + sc_signal r_cleanup_prev_cache_id; // srcid of previous heap entry + sc_signal r_cleanup_prev_inst; // inst bit of previous heap entry + sc_signal r_cleanup_next_ptr; // next pointer to the heap + sc_signal r_cleanup_tag; // cache line tag (in directory) + sc_signal r_cleanup_is_cnt; // inst bit (in directory) + sc_signal r_cleanup_lock; // lock bit (in directory) + sc_signal r_cleanup_dirty; // dirty bit (in directory) + sc_signal r_cleanup_way; // associative way (in cache) + + sc_signal r_cleanup_write_srcid; // srcid of write rsp + sc_signal r_cleanup_write_trdid; // trdid of write rsp + sc_signal r_cleanup_write_pktid; // pktid of write rsp + + sc_signal r_cleanup_need_rsp; // write response required + sc_signal r_cleanup_need_ack; // config acknowledge required + + sc_signal r_cleanup_index; // index of the INVAL line (in the UPT) + + // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) + sc_signal r_cleanup_to_tgt_rsp_req; // valid request + sc_signal r_cleanup_to_tgt_rsp_srcid; // transaction srcid + sc_signal r_cleanup_to_tgt_rsp_trdid; // transaction trdid + sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid + + /////////////////////////////////////////////////////// + // Registers controlled by CAS fsm + /////////////////////////////////////////////////////// + + sc_signal r_cas_fsm; // FSM state + sc_signal r_cas_wdata; // write data word + sc_signal * r_cas_rdata; // read data word + sc_signal r_cas_lfsr; // lfsr for random introducing + sc_signal r_cas_cpt; // size of command + sc_signal r_cas_copy; // Srcid of the first copy + sc_signal r_cas_copy_cache; // Srcid of the first copy + sc_signal r_cas_copy_inst; // Type of the first copy + sc_signal r_cas_count; // number of copies + sc_signal r_cas_ptr; // pointer to the heap + sc_signal r_cas_next_ptr; // next pointer to the heap + sc_signal r_cas_is_cnt; // is_cnt bit (in directory) + sc_signal r_cas_dirty; // dirty bit (in directory) + sc_signal r_cas_way; // way in directory + sc_signal r_cas_set; // set in directory + sc_signal r_cas_tag; // cache line tag (in directory) + sc_signal r_cas_trt_index; // Transaction Table index + sc_signal r_cas_upt_index; // Update Table index + sc_signal * r_cas_data; // cache line data + + // Buffer between CAS fsm and IXR_CMD fsm + sc_signal r_cas_to_ixr_cmd_req; // valid request + sc_signal r_cas_to_ixr_cmd_index; // TRT index + + // Buffer between CAS fsm and TGT_RSP fsm + sc_signal r_cas_to_tgt_rsp_req; // valid request + sc_signal r_cas_to_tgt_rsp_data; // read data word + sc_signal r_cas_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_cas_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_cas_to_tgt_rsp_pktid; // Transaction pktid + + // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) + sc_signal r_cas_to_cc_send_multi_req; // valid request + sc_signal r_cas_to_cc_send_brdcast_req; // brdcast request + sc_signal r_cas_to_cc_send_nline; // cache line index + sc_signal r_cas_to_cc_send_trdid; // index in Update Table + sc_signal r_cas_to_cc_send_wdata; // data (one word) + sc_signal r_cas_to_cc_send_is_long; // it is a 64 bits CAS + sc_signal r_cas_to_cc_send_wdata_high; // data high (one word) + sc_signal r_cas_to_cc_send_index; // index of the word in line + GenericFifo m_cas_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_cas_to_cc_send_srcid_fifo; // fifo for srcids + + //////////////////////////////////////////////////// + // Registers controlled by the IXR_RSP fsm + //////////////////////////////////////////////////// + + sc_signal r_ixr_rsp_fsm; // FSM state + sc_signal r_ixr_rsp_trt_index; // TRT entry index + sc_signal r_ixr_rsp_cpt; // word counter + + // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) + sc_signal r_ixr_rsp_to_config_ack; // one single bit + + // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) + sc_signal * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry + + //////////////////////////////////////////////////// + // Registers controlled by the XRAM_RSP fsm + //////////////////////////////////////////////////// + + sc_signal r_xram_rsp_fsm; // FSM state + sc_signal r_xram_rsp_trt_index; // TRT entry index + TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer + sc_signal r_xram_rsp_victim_inval; // victim line invalidate + sc_signal r_xram_rsp_victim_is_cnt; // victim line inst bit + sc_signal r_xram_rsp_victim_dirty; // victim line dirty bit + sc_signal r_xram_rsp_victim_way; // victim line way + sc_signal r_xram_rsp_victim_set; // victim line set + sc_signal r_xram_rsp_victim_nline; // victim line index + sc_signal r_xram_rsp_victim_copy; // victim line first copy + sc_signal r_xram_rsp_victim_copy_cache; // victim line first copy + sc_signal r_xram_rsp_victim_copy_inst; // victim line type of first copy + sc_signal r_xram_rsp_victim_count; // victim line number of copies + sc_signal r_xram_rsp_victim_ptr; // victim line pointer to the heap + sc_signal * r_xram_rsp_victim_data; // victim line data + sc_signal r_xram_rsp_ivt_index; // IVT entry index + sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap + sc_signal r_xram_rsp_rerror_irq; // WRITE MISS rerror irq + sc_signal r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable + sc_signal r_xram_rsp_rerror_address; // WRITE MISS rerror address + sc_signal r_xram_rsp_rerror_rsrcid; // WRITE MISS rerror srcid + + // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) + sc_signal r_xram_rsp_to_tgt_rsp_req; // Valid request + sc_signal r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) + sc_signal r_xram_rsp_to_tgt_rsp_word; // first word index + sc_signal r_xram_rsp_to_tgt_rsp_length; // length of the response + sc_signal r_xram_rsp_to_tgt_rsp_rerror; // send error to requester + sc_signal r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table + + // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) + sc_signal r_xram_rsp_to_cc_send_multi_req; // Valid request + sc_signal r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request + sc_signal r_xram_rsp_to_cc_send_nline; // cache line index; + sc_signal r_xram_rsp_to_cc_send_trdid; // index of UPT entry + GenericFifo m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids + + // Buffer between XRAM_RSP fsm and IXR_CMD fsm + sc_signal r_xram_rsp_to_ixr_cmd_req; // Valid request + sc_signal r_xram_rsp_to_ixr_cmd_index; // TRT index + + //////////////////////////////////////////////////// + // Registers controlled by the IXR_CMD fsm + //////////////////////////////////////////////////// + + sc_signal r_ixr_cmd_fsm; + sc_signal r_ixr_cmd_word; // word index for a put + sc_signal r_ixr_cmd_trdid; // TRT index value + sc_signal r_ixr_cmd_address; // address to XRAM + sc_signal * r_ixr_cmd_wdata; // cache line buffer + sc_signal r_ixr_cmd_get; // transaction type (PUT/GET) + + //////////////////////////////////////////////////// + // Registers controlled by TGT_RSP fsm + //////////////////////////////////////////////////// + + sc_signal r_tgt_rsp_fsm; + sc_signal r_tgt_rsp_cpt; + sc_signal r_tgt_rsp_key_sent; + + //////////////////////////////////////////////////// + // Registers controlled by CC_SEND fsm + //////////////////////////////////////////////////// + + sc_signal r_cc_send_fsm; + sc_signal r_cc_send_cpt; + sc_signal r_cc_send_inst; + + //////////////////////////////////////////////////// + // Registers controlled by CC_RECEIVE fsm + //////////////////////////////////////////////////// + + sc_signal r_cc_receive_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_DIR fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_dir_fsm; + sc_signal r_alloc_dir_reset_cpt; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_TRT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_trt_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_UPT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_upt_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_IVT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_ivt_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_HEAP fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_heap_fsm; + sc_signal r_alloc_heap_reset_cpt; + }; // end class VciMemCache + +}} + +#endif + +// Local Variables: +// tab-width: 2 +// c-basic-offset: 2 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 + Index: branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/include/xram_transaction.h (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/include/xram_transaction.h (revision 647) @@ -0,0 +1,474 @@ +#ifndef XRAM_TRANSACTION_H_ +#define XRAM_TRANSACTION_H_ + +#include +#include +#include +#include "arithmetics.h" + +#define DEBUG_XRAM_TRANSACTION 0 + +//////////////////////////////////////////////////////////////////////// +// A transaction tab entry +//////////////////////////////////////////////////////////////////////// + +class TransactionTabEntry +{ + typedef sc_dt::sc_uint<64> wide_data_t; + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t be_t; + + public: + bool valid; // entry valid + bool xram_read; // read request to XRAM + addr_t nline; // index (zy) of the requested line + size_t srcid; // processor requesting the transaction + size_t trdid; // processor requesting the transaction + size_t pktid; // processor requesting the transaction + bool proc_read; // read request from processor + size_t read_length; // length of the read (for the response) + size_t word_index; // index of the first read word (for response) + std::vector wdata; // write buffer (one cache line) + std::vector wdata_be; // be for each data in the write buffer + bool rerror; // error returned by xram + data_t ll_key; // LL key returned by the llsc_global_table + bool config; // transaction required by CONFIG FSM + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the entry + ///////////////////////////////////////////////////////////////////// + void init() + { + valid = false; + rerror = false; + config = false; + } + + ///////////////////////////////////////////////////////////////////// + // The alloc() function initializes the vectors of an entry + // The "n_words" argument is the number of words in a cache line. + ///////////////////////////////////////////////////////////////////// + void alloc(size_t n_words) + { + wdata_be.reserve( (int)n_words ); + wdata.reserve( (int)n_words ); + for(size_t i=0; i wide_data_t; + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t be_t; + + private: + const std::string tab_name; // the name for logs + size_t size_tab; // the size of the tab + + data_t be_to_mask(be_t be) + { + data_t ret = 0; + if ( be&0x1 ) { + ret = ret | 0x000000FF; + } + if ( be&0x2 ) { + ret = ret | 0x0000FF00; + } + if ( be&0x4 ) { + ret = ret | 0x00FF0000; + } + if ( be&0x8 ) { + ret = ret | 0xFF000000; + } + return ret; + } + + public: + TransactionTabEntry *tab; // The transaction tab + + //////////////////////////////////////////////////////////////////// + // Constructors + //////////////////////////////////////////////////////////////////// + TransactionTab() + { + size_tab=0; + tab=NULL; + } + + TransactionTab(const std::string &name, + size_t n_entries, + size_t n_words ) + : tab_name( name ), + size_tab( n_entries ) + { + tab = new TransactionTabEntry[size_tab]; + for ( size_t i=0; i" << std::endl; + for ( size_t id = 0 ; id < size_tab ; id++ ) + { + tab[id].print( id , detailed ); + } + } + ///////////////////////////////////////////////////////////////////// + // The read() function returns a transaction tab entry. + // Arguments : + // - index : the index of the entry to read + ///////////////////////////////////////////////////////////////////// + TransactionTabEntry read(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: Invalid Transaction Tab Entry"); + + return tab[index]; + } + ///////////////////////////////////////////////////////////////////// + // The full() function returns the state of the transaction tab + // Arguments : + // - index : (return argument) the index of an empty entry + // The function returns true if the transaction tab is full + ///////////////////////////////////////////////////////////////////// + bool full(size_t &index) + { + for(size_t i=0; i &be, + const std::vector &data) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()"); + + assert( (be.size()==tab[index].wdata_be.size()) and + "MEMC ERROR: Bad be size in TRT write_data_mask()"); + + assert( (data.size()==tab[index].wdata.size()) and + "MEMC ERROR: Bad data size in TRT write_data_mask()"); + + for(size_t i=0; i &data_be, + const std::vector &data, + const data_t ll_key = 0, + const bool config = false) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT set()"); + + assert( (data_be.size()==tab[index].wdata_be.size()) and + "MEMC ERROR: Bad data_be argument in TRT set()"); + + assert( (data.size()==tab[index].wdata.size()) and + "MEMC ERROR: Bad data argument in TRT set()"); + + tab[index].valid = true; + tab[index].xram_read = xram_read; + tab[index].nline = nline; + tab[index].srcid = srcid; + tab[index].trdid = trdid; + tab[index].pktid = pktid; + tab[index].proc_read = proc_read; + tab[index].read_length = read_length; + tab[index].word_index = word_index; + tab[index].ll_key = ll_key; + tab[index].config = config; + for(size_t i=0; i>32); + mask = be_to_mask(tab[index].wdata_be[word+1]); + tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask); + } + ///////////////////////////////////////////////////////////////////// + // The erase() function erases an entry in the transaction tab. + // Arguments : + // - index : the index of the request in the transaction tab + ///////////////////////////////////////////////////////////////////// + void erase(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT erase()"); + + tab[index].valid = false; + tab[index].rerror = false; + } + ///////////////////////////////////////////////////////////////////// + // The is_config() function returns the config flag value. + // Arguments : + // - index : the index of the entry in the transaction tab + ///////////////////////////////////////////////////////////////////// + bool is_config(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT is_config()"); + + return tab[index].config; + } +}; // end class TransactionTab + +#endif + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 647) @@ -0,0 +1,9000 @@ +/* -*- c++ -*- + * + * File : vci_mem_cache.cpp + * Date : 30/10/2008 + * Copyright : UPMC / LIP6 + * Authors : Alain Greiner / Eric Guthmuller + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Maintainers: alain.greiner@lip6.fr + * eric.guthmuller@polytechnique.edu + * cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr + */ + +#include "../include/vci_mem_cache.h" +#include "mem_cache.h" + +////// debug services ///////////////////////////////////////////////////////////// +// All debug messages are conditionned by two variables: +// - compile time : DEBUG_MEMC_*** : defined below +// - execution time : m_debug = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) +/////////////////////////////////////////////////////////////////////////////////////// + +#define DEBUG_MEMC_GLOBAL 0 // synthetic trace of all FSMs +#define DEBUG_MEMC_CONFIG 1 // detailed trace of CONFIG FSM +#define DEBUG_MEMC_READ 1 // detailed trace of READ FSM +#define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM +#define DEBUG_MEMC_CAS 1 // detailed trace of CAS FSM +#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_CMD FSM +#define DEBUG_MEMC_IXR_RSP 1 // detailed trace of IXR_RSP FSM +#define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM +#define DEBUG_MEMC_CC_SEND 1 // detailed trace of CC_SEND FSM +#define DEBUG_MEMC_MULTI_ACK 1 // detailed trace of MULTI_ACK FSM +#define DEBUG_MEMC_TGT_CMD 1 // detailed trace of TGT_CMD FSM +#define DEBUG_MEMC_TGT_RSP 1 // detailed trace of TGT_RSP FSM +#define DEBUG_MEMC_CLEANUP 1 // detailed trace of CLEANUP FSM + +#define RANDOMIZE_CAS 1 + +namespace soclib { namespace caba { + + const char *tgt_cmd_fsm_str[] = + { + "TGT_CMD_IDLE", + "TGT_CMD_READ", + "TGT_CMD_WRITE", + "TGT_CMD_CAS", + "TGT_CMD_CONFIG", + "TGT_CMD_ERROR" + }; + const char *tgt_rsp_fsm_str[] = + { + "TGT_RSP_READ_IDLE", + "TGT_RSP_WRITE_IDLE", + "TGT_RSP_CAS_IDLE", + "TGT_RSP_XRAM_IDLE", + "TGT_RSP_MULTI_ACK_IDLE", + "TGT_RSP_CLEANUP_IDLE", + "TGT_RSP_TGT_CMD_IDLE", + "TGT_RSP_CONFIG_IDLE", + "TGT_RSP_READ", + "TGT_RSP_WRITE", + "TGT_RSP_CAS", + "TGT_RSP_XRAM", + "TGT_RSP_MULTI_ACK", + "TGT_RSP_CLEANUP", + "TGT_RSP_TGT_CMD", + "TGT_RSP_CONFIG" + }; + const char *cc_receive_fsm_str[] = + { + "CC_RECEIVE_IDLE", + "CC_RECEIVE_CLEANUP", + "CC_RECEIVE_CLEANUP_EOP", + "CC_RECEIVE_MULTI_ACK" + }; + const char *cc_send_fsm_str[] = + { + "CC_SEND_XRAM_RSP_IDLE", + "CC_SEND_WRITE_IDLE", + "CC_SEND_CAS_IDLE", + "CC_SEND_CONFIG_IDLE", + "CC_SEND_XRAM_RSP_BRDCAST_HEADER", + "CC_SEND_XRAM_RSP_BRDCAST_NLINE", + "CC_SEND_XRAM_RSP_INVAL_HEADER", + "CC_SEND_XRAM_RSP_INVAL_NLINE", + "CC_SEND_WRITE_BRDCAST_HEADER", + "CC_SEND_WRITE_BRDCAST_NLINE", + "CC_SEND_WRITE_UPDT_HEADER", + "CC_SEND_WRITE_UPDT_NLINE", + "CC_SEND_WRITE_UPDT_DATA", + "CC_SEND_CAS_BRDCAST_HEADER", + "CC_SEND_CAS_BRDCAST_NLINE", + "CC_SEND_CAS_UPDT_HEADER", + "CC_SEND_CAS_UPDT_NLINE", + "CC_SEND_CAS_UPDT_DATA", + "CC_SEND_CAS_UPDT_DATA_HIGH", + "CC_SEND_CONFIG_INVAL_HEADER", + "CC_SEND_CONFIG_INVAL_NLINE", + "CC_SEND_CONFIG_BRDCAST_HEADER", + "CC_SEND_CONFIG_BRDCAST_NLINE" + }; + const char *multi_ack_fsm_str[] = + { + "MULTI_ACK_IDLE", + "MULTI_ACK_UPT_LOCK", + "MULTI_ACK_UPT_CLEAR", + "MULTI_ACK_WRITE_RSP" + }; + const char *config_fsm_str[] = + { + "CONFIG_IDLE", + "CONFIG_LOOP", + "CONFIG_WAIT", + "CONFIG_RSP", + "CONFIG_DIR_REQ", + "CONFIG_DIR_ACCESS", + "CONFIG_IVT_LOCK", + "CONFIG_BC_SEND", + "CONFIG_INVAL_SEND", + "CONFIG_HEAP_REQ", + "CONFIG_HEAP_SCAN", + "CONFIG_HEAP_LAST", + "CONFIG_TRT_LOCK", + "CONFIG_TRT_SET", + "CONFIG_PUT_REQ" + }; + const char *read_fsm_str[] = + { + "READ_IDLE", + "READ_DIR_REQ", + "READ_DIR_LOCK", + "READ_DIR_HIT", + "READ_HEAP_REQ", + "READ_HEAP_LOCK", + "READ_HEAP_WRITE", + "READ_HEAP_ERASE", + "READ_HEAP_LAST", + "READ_RSP", + "READ_TRT_LOCK", + "READ_TRT_SET", + "READ_TRT_REQ" + }; + const char *write_fsm_str[] = + { + "WRITE_IDLE", + "WRITE_NEXT", + "WRITE_DIR_REQ", + "WRITE_DIR_LOCK", + "WRITE_DIR_HIT", + "WRITE_UPT_LOCK", + "WRITE_UPT_HEAP_LOCK", + "WRITE_UPT_REQ", + "WRITE_UPT_NEXT", + "WRITE_UPT_DEC", + "WRITE_RSP", + "WRITE_MISS_TRT_LOCK", + "WRITE_MISS_TRT_DATA", + "WRITE_MISS_TRT_SET", + "WRITE_MISS_XRAM_REQ", + "WRITE_BC_DIR_READ", + "WRITE_BC_TRT_LOCK", + "WRITE_BC_IVT_LOCK", + "WRITE_BC_DIR_INVAL", + "WRITE_BC_CC_SEND", + "WRITE_BC_XRAM_REQ", + "WRITE_WAIT" + }; + const char *ixr_rsp_fsm_str[] = + { + "IXR_RSP_IDLE", + "IXR_RSP_TRT_ERASE", + "IXR_RSP_TRT_READ" + }; + const char *xram_rsp_fsm_str[] = + { + "XRAM_RSP_IDLE", + "XRAM_RSP_TRT_COPY", + "XRAM_RSP_TRT_DIRTY", + "XRAM_RSP_DIR_LOCK", + "XRAM_RSP_DIR_UPDT", + "XRAM_RSP_DIR_RSP", + "XRAM_RSP_IVT_LOCK", + "XRAM_RSP_INVAL_WAIT", + "XRAM_RSP_INVAL", + "XRAM_RSP_WRITE_DIRTY", + "XRAM_RSP_HEAP_REQ", + "XRAM_RSP_HEAP_ERASE", + "XRAM_RSP_HEAP_LAST", + "XRAM_RSP_ERROR_ERASE", + "XRAM_RSP_ERROR_RSP" + }; + const char *ixr_cmd_fsm_str[] = + { + "IXR_CMD_READ_IDLE", + "IXR_CMD_WRITE_IDLE", + "IXR_CMD_CAS_IDLE", + "IXR_CMD_XRAM_IDLE", + "IXR_CMD_CONFIG_IDLE", + "IXR_CMD_READ_TRT", + "IXR_CMD_WRITE_TRT", + "IXR_CMD_CAS_TRT", + "IXR_CMD_XRAM_TRT", + "IXR_CMD_CONFIG_TRT", + "IXR_CMD_READ_SEND", + "IXR_CMD_WRITE_SEND", + "IXR_CMD_CAS_SEND", + "IXR_CMD_XRAM_SEND", + "IXR_CMD_CONFIG_SEND" + }; + const char *cas_fsm_str[] = + { + "CAS_IDLE", + "CAS_DIR_REQ", + "CAS_DIR_LOCK", + "CAS_DIR_HIT_READ", + "CAS_DIR_HIT_COMPARE", + "CAS_DIR_HIT_WRITE", + "CAS_UPT_LOCK", + "CAS_UPT_HEAP_LOCK", + "CAS_UPT_REQ", + "CAS_UPT_NEXT", + "CAS_BC_TRT_LOCK", + "CAS_BC_IVT_LOCK", + "CAS_BC_DIR_INVAL", + "CAS_BC_CC_SEND", + "CAS_BC_XRAM_REQ", + "CAS_RSP_FAIL", + "CAS_RSP_SUCCESS", + "CAS_MISS_TRT_LOCK", + "CAS_MISS_TRT_SET", + "CAS_MISS_XRAM_REQ", + "CAS_WAIT" + }; + const char *cleanup_fsm_str[] = + { + "CLEANUP_IDLE", + "CLEANUP_GET_NLINE", + "CLEANUP_DIR_REQ", + "CLEANUP_DIR_LOCK", + "CLEANUP_DIR_WRITE", + "CLEANUP_HEAP_REQ", + "CLEANUP_HEAP_LOCK", + "CLEANUP_HEAP_SEARCH", + "CLEANUP_HEAP_CLEAN", + "CLEANUP_HEAP_FREE", + "CLEANUP_IVT_LOCK", + "CLEANUP_IVT_DECREMENT", + "CLEANUP_IVT_CLEAR", + "CLEANUP_WRITE_RSP", + "CLEANUP_SEND_CLACK" + }; + const char *alloc_dir_fsm_str[] = + { + "ALLOC_DIR_RESET", + "ALLOC_DIR_READ", + "ALLOC_DIR_WRITE", + "ALLOC_DIR_CAS", + "ALLOC_DIR_CLEANUP", + "ALLOC_DIR_XRAM_RSP", + "ALLOC_DIR_CONFIG" + }; + const char *alloc_trt_fsm_str[] = + { + "ALLOC_TRT_READ", + "ALLOC_TRT_WRITE", + "ALLOC_TRT_CAS", + "ALLOC_TRT_XRAM_RSP", + "ALLOC_TRT_IXR_RSP", + "ALLOC_TRT_IXR_CMD", + "ALLOC_TRT_CONFIG" + }; + const char *alloc_upt_fsm_str[] = + { + "ALLOC_UPT_WRITE", + "ALLOC_UPT_CAS", + "ALLOC_UPT_MULTI_ACK" + }; + const char *alloc_ivt_fsm_str[] = + { + "ALLOC_IVT_WRITE", + "ALLOC_IVT_XRAM_RSP", + "ALLOC_IVT_CLEANUP", + "ALLOC_IVT_CAS", + "ALLOC_IVT_CONFIG" + }; + const char *alloc_heap_fsm_str[] = + { + "ALLOC_HEAP_RESET", + "ALLOC_HEAP_READ", + "ALLOC_HEAP_WRITE", + "ALLOC_HEAP_CAS", + "ALLOC_HEAP_CLEANUP", + "ALLOC_HEAP_XRAM_RSP", + "ALLOC_HEAP_CONFIG" + }; + +#define tmpl(x) \ + template x \ + VciMemCache + + using namespace soclib::common; + + //////////////////////////////// + // Constructor + //////////////////////////////// + + tmpl(/**/)::VciMemCache( + sc_module_name name, + const MappingTable &mtp, // mapping table for direct network + const MappingTable &mtx, // mapping table for external network + const IntTab &srcid_x, // global index on external network + const IntTab &tgtid_d, // global index on direct network + const size_t x_width, // number of x bits in platform + const size_t y_width, // number of x bits in platform + const size_t nways, // number of ways per set + const size_t nsets, // number of associative sets + const size_t nwords, // number of words in cache line + const size_t max_copies, // max number of copies in heap + const size_t heap_size, // number of heap entries + const size_t trt_lines, // number of TRT entries + const size_t upt_lines, // number of UPT entries + const size_t ivt_lines, // number of IVT entries + const size_t debug_start_cycle, + const bool debug_ok) + + : soclib::caba::BaseModule(name), + + p_clk( "p_clk" ), + p_resetn( "p_resetn" ), + p_vci_tgt( "p_vci_tgt" ), + p_vci_ixr( "p_vci_ixr" ), + p_dspin_p2m( "p_dspin_p2m" ), + p_dspin_m2p( "p_dspin_m2p" ), + p_dspin_clack( "p_dspin_clack" ), + + m_seglist(mtp.getSegmentList(tgtid_d)), + m_nseg(0), + m_srcid_x( mtx.indexForId(srcid_x)), + m_initiators(1 << vci_param_int::S), + m_heap_size(heap_size), + m_ways(nways), + m_sets(nsets), + m_words(nwords), + m_x_width(x_width), + m_y_width(y_width), + m_debug_start_cycle(debug_start_cycle), + m_debug_ok(debug_ok), + m_trt_lines(trt_lines), + m_trt(this->name(), trt_lines, nwords), + m_upt_lines(upt_lines), + m_upt(upt_lines), + m_ivt(ivt_lines), + m_cache_directory(nways, nsets, nwords, vci_param_int::N), + m_cache_data(nways, nsets, nwords), + m_heap(m_heap_size), + m_max_copies(max_copies), + m_llsc_table(), + +#define L2 soclib::common::uint32_log2 + m_x(L2(m_words), 2), + m_y(L2(m_sets), L2(m_words) + 2), + m_z(vci_param_int::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2), + m_nline(vci_param_int::N - L2(m_words) - 2, L2(m_words) + 2), +#undef L2 + + // XMIN(5 bits) / XMAX(5 bits) / YMIN(5 bits) / YMAX(5 bits) + // 0b00000 / 0b11111 / 0b00000 / 0b11111 + m_broadcast_boundaries(0x7C1F), + + // CONFIG interface + m_config_addr_mask((1<<12)-1), + + m_config_regr_width(7), + m_config_func_width(3), + m_config_regr_idx_mask((1<::iterator seg; + size_t i = 0; + + for (seg = m_seglist.begin(); seg != m_seglist.end(); seg++) + { + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; + m_nseg++; + } + + assert( (m_nseg > 0) and + "MEMC ERROR : At least one segment must be mapped to this component"); + + m_seg = new soclib::common::Segment*[m_nseg]; + + for (seg = m_seglist.begin(); seg != m_seglist.end(); seg++) + { + if (seg->special() ) m_seg_config = i; + m_seg[i] = & (*seg); + i++; + } + + addr_t gid = m_seg[0]->baseAddress() >> (vci_param_int::N - x_width - y_width); + m_x_self = (gid >> m_y_width) & ((1 << m_x_width) - 1); + m_y_self = gid & ((1 << m_y_width) - 1); + + // Allocation for IXR_RSP FSM + r_ixr_rsp_to_xram_rsp_rok = new sc_signal[m_trt_lines]; + + // Allocation for XRAM_RSP FSM + r_xram_rsp_victim_data = new sc_signal[nwords]; + r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; + + // Allocation for READ FSM + r_read_data = new sc_signal[nwords]; + r_read_to_tgt_rsp_data = new sc_signal[nwords]; + + // Allocation for WRITE FSM + r_write_data = new sc_signal[nwords]; + r_write_be = new sc_signal[nwords]; + r_write_to_cc_send_data = new sc_signal[nwords]; + r_write_to_cc_send_be = new sc_signal[nwords]; + + // Allocation for CAS FSM + r_cas_data = new sc_signal[nwords]; + r_cas_rdata = new sc_signal[2]; + + // Allocation for IXR_CMD FSM + r_ixr_cmd_wdata = new sc_signal[nwords]; + + // Allocation for debug + m_debug_previous_data = new data_t[nwords]; + m_debug_data = new data_t[nwords]; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + } // end constructor + + + ///////////////////////////////////////////////////// + tmpl(void)::cache_monitor(addr_t addr) + ///////////////////////////////////////////////////// + { + size_t way = 0; + size_t set = 0; + DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set); + + // read data and compute data_change + bool data_change = false; + if (entry.valid) + { + for (size_t word = 0; word> (srcid_width - m_x_width)); + uint8_t req_y = (req_srcid >> (srcid_width - m_x_width - m_y_width)) & ((1 << m_y_width) - 1); + + return abs(m_x_self - req_x) + abs(m_y_self - req_y); + } + + + ///////////////////////////////////////////////////// + tmpl(bool)::is_local_req(uint32_t req_srcid) + ///////////////////////////////////////////////////// + { + return req_distance(req_srcid) == 0; + } + + ///////////////////////////////////////////////////// + tmpl(int)::read_instrumentation(uint32_t regr, uint32_t & rdata) + ///////////////////////////////////////////////////// + { + int error = 0; + + switch(regr) + { + /////////////////////////////////////////////////////// + // DIRECT instrumentation registers // + // Registers of 32 bits and therefore only LO is // + // implemented. // + // // + // The HI may be used in future implementations // + /////////////////////////////////////////////////////// + + // LOCAL + + case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_local ; break; + case MEMC_LOCAL_WRITE_LO : rdata = m_cpt_write_flits_local ; break; + case MEMC_LOCAL_LL_LO : rdata = m_cpt_ll_local ; break; + case MEMC_LOCAL_SC_LO : rdata = m_cpt_sc_local ; break; + case MEMC_LOCAL_CAS_LO : rdata = m_cpt_cas_local ; break; + case MEMC_LOCAL_READ_HI : + case MEMC_LOCAL_WRITE_HI : + case MEMC_LOCAL_LL_HI : + case MEMC_LOCAL_SC_HI : + case MEMC_LOCAL_CAS_HI : rdata = 0; break; + + // REMOTE + + case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_remote ; break; + case MEMC_REMOTE_WRITE_LO : rdata = m_cpt_write_flits_remote ; break; + case MEMC_REMOTE_LL_LO : rdata = m_cpt_ll_remote ; break; + case MEMC_REMOTE_SC_LO : rdata = m_cpt_sc_remote ; break; + case MEMC_REMOTE_CAS_LO : rdata = m_cpt_cas_remote ; break; + case MEMC_REMOTE_READ_HI : + case MEMC_REMOTE_WRITE_HI : + case MEMC_REMOTE_LL_HI : + case MEMC_REMOTE_SC_HI : + case MEMC_REMOTE_CAS_HI : rdata = 0; break; + + // COST + + case MEMC_COST_READ_LO : rdata = m_cpt_read_cost ; break; + case MEMC_COST_WRITE_LO : rdata = m_cpt_write_cost; break; + case MEMC_COST_LL_LO : rdata = m_cpt_ll_cost ; break; + case MEMC_COST_SC_LO : rdata = m_cpt_sc_cost ; break; + case MEMC_COST_CAS_LO : rdata = m_cpt_cas_cost ; break; + case MEMC_COST_READ_HI : + case MEMC_COST_WRITE_HI : + case MEMC_COST_LL_HI : + case MEMC_COST_SC_HI : + case MEMC_COST_CAS_HI : rdata = 0; break; + + /////////////////////////////////////////////////////// + // COHERENCE instrumentation registers // + // Registers of 32 bits and therefore only LO is // + // implemented. // + // // + // The HI may be used in future implementations // + /////////////////////////////////////////////////////// + + // LOCAL + + case MEMC_LOCAL_MUPDATE_LO : rdata = m_cpt_update_local ; break; + case MEMC_LOCAL_MINVAL_LO : rdata = m_cpt_minval_local ; break; + case MEMC_LOCAL_CLEANUP_LO : rdata = m_cpt_cleanup_local; break; + case MEMC_LOCAL_MUPDATE_HI : + case MEMC_LOCAL_MINVAL_HI : + case MEMC_LOCAL_CLEANUP_HI : rdata = 0; break; + + // REMOTE + + case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_update_remote ; break; + case MEMC_REMOTE_MINVAL_LO : rdata = m_cpt_minval_remote ; break; + case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break; + case MEMC_REMOTE_MUPDATE_HI : + case MEMC_REMOTE_MINVAL_HI : + case MEMC_REMOTE_CLEANUP_HI : rdata = 0; break; + + // COST + + case MEMC_COST_MUPDATE_LO : rdata = m_cpt_update_cost ; break; + case MEMC_COST_MINVAL_LO : rdata = m_cpt_minval_cost ; break; + case MEMC_COST_CLEANUP_LO : rdata = m_cpt_cleanup_cost ; break; + case MEMC_COST_MUPDATE_HI : + case MEMC_COST_MINVAL_HI : + case MEMC_COST_CLEANUP_HI : rdata = 0; break; + + // TOTAL + + case MEMC_TOTAL_MUPDATE_LO : rdata = m_cpt_update ; break; + case MEMC_TOTAL_MINVAL_LO : rdata = m_cpt_minval ; break; + case MEMC_TOTAL_BINVAL_LO : rdata = m_cpt_binval ; break; + case MEMC_TOTAL_MUPDATE_HI : + case MEMC_TOTAL_MINVAL_HI : + case MEMC_TOTAL_BINVAL_HI : rdata = 0; break; + + // unknown register + + default : error = 1; + } + + return error; + } + + ////////////////////////////////////////////////// + tmpl(void)::print_trace( size_t detailed ) + ////////////////////////////////////////////////// + { + std::cout << "MEMC " << name() << std::endl; + std::cout << " " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()] + << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()] + << " | " << read_fsm_str[r_read_fsm.read()] + << " | " << write_fsm_str[r_write_fsm.read()] + << " | " << cas_fsm_str[r_cas_fsm.read()] + << " | " << config_fsm_str[r_config_fsm.read()] + << " | " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl; + std::cout << " " << cc_send_fsm_str[r_cc_send_fsm.read()] + << " | " << cc_receive_fsm_str[r_cc_receive_fsm.read()] + << " | " << multi_ack_fsm_str[r_multi_ack_fsm.read()] + << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] + << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] + << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl; + std::cout << " " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] + << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] + << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] + << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()] + << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; + + if ( detailed ) m_trt.print(0); + } + + + ///////////////////////////////////////// + tmpl(void)::print_stats(bool activity_counters = true, bool stats = true) + ///////////////////////////////////////// + { + std::cout << "**********************************" << std::dec << std::endl; + std::cout << "*** MEM_CACHE " << name() << std::endl; + std::cout << "**********************************" << std::dec << std::endl; + if (activity_counters) { + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout << "--- Activity Counters ---" << std::dec << std::endl; + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout + << "[001] NUMBER OF CYCLES = " << m_cpt_cycles << std::endl + << std::endl + << "[002] LOCAL READ = " << m_cpt_read_local << std::endl + << "[003] REMOTE READ = " << m_cpt_read_remote << std::endl + << "[004] READ COST (FLITS * DIST) = " << m_cpt_read_cost << std::endl + << std::endl + << "[005] LOCAL WRITE = " << m_cpt_write_local << std::endl + << "[006] REMOTE WRITE = " << m_cpt_write_remote << std::endl + << "[007] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl + << "[008] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl + << "[009] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl + << std::endl + << "[010] LOCAL LL = " << m_cpt_ll_local << std::endl + << "[011] REMOTE LL = " << m_cpt_ll_remote << std::endl + << "[012] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl + << std::endl + << "[013] LOCAL SC = " << m_cpt_sc_local << std::endl + << "[014] REMOTE SC = " << m_cpt_sc_remote << std::endl + << "[015] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl + << std::endl + << "[016] LOCAL CAS = " << m_cpt_cas_local << std::endl + << "[017] REMOTE CAS = " << m_cpt_cas_remote << std::endl + << "[018] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl + << std::endl + << "[019] REQUESTS TRIG. UPDATE = " << m_cpt_update << std::endl + << "[020] LOCAL UPDATE = " << m_cpt_update_local << std::endl + << "[021] REMOTE UPDATE = " << m_cpt_update_remote << std::endl + << "[022] UPDT COST (FLITS * DIST) = " << m_cpt_update_cost << std::endl + << std::endl + << "[023] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl + << "[024] LOCAL M_INV = " << m_cpt_minval_local << std::endl + << "[025] REMOTE M_INV = " << m_cpt_minval_remote << std::endl + << "[026] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl + << std::endl + << "[027] BROADCAT INVAL = " << m_cpt_binval << std::endl + << std::endl + << "[028] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl + << "[029] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl + << "[030] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl + << std::endl + << std::endl + << "[031] READ MISS = " << m_cpt_read_miss << std::endl + << "[032] WRITE MISS = " << m_cpt_write_miss << std::endl + << "[033] WRITE DIRTY = " << m_cpt_write_dirty << std::endl + << "[034] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl + << "[035] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl + << "[036] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl + << "[037] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl + << "[038] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl + << std::endl; + } + + if (stats) { + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout << "--- Calculated Stats ---" << std::dec << std::endl; + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout + << "[100] READ TOTAL = " << m_cpt_read_local + m_cpt_read_remote << std::endl + << "[101] READ RATE = " << (double) (m_cpt_read_local + m_cpt_read_remote) / m_cpt_cycles << std::endl + << "[102] LOCAL READ RATE = " << (double) m_cpt_read_local / m_cpt_cycles << std::endl + << "[103] REMOTE READ RATE = " << (double) m_cpt_read_remote / m_cpt_cycles << std::endl + << "[104] READ MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_read_local + m_cpt_read_remote) << std::endl + << std::endl + << "[105] WRITE TOTAL = " << m_cpt_write_local + m_cpt_write_remote << std::endl + << "[106] WRITE RATE = " << (double) (m_cpt_write_local + m_cpt_write_remote) / m_cpt_cycles << std::endl + << "[107] LOCAL WRITE RATE = " << (double) m_cpt_write_local / m_cpt_cycles << std::endl + << "[108] REMOTE WRITE RATE = " << (double) m_cpt_write_remote / m_cpt_cycles << std::endl + << "[109] WRITE MISS RATE = " << (double) m_cpt_write_miss / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << "[110] WRITE BURST TOTAL = " << m_cpt_write_flits_local + m_cpt_write_flits_remote << std::endl + << "[111] WRITE BURST AVERAGE = " << (double) (m_cpt_write_flits_local + m_cpt_write_flits_remote) / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << "[112] LOCAL WRITE BURST AV. = " << (double) m_cpt_write_flits_local / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << "[113] REMOTE WRITE BURST AV = " << (double) m_cpt_write_flits_remote / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << std::endl + << "[114] UPDATE RATE = " << (double) m_cpt_update / m_cpt_cycles << std::endl + << "[115] AV. UPDATE PER UP REQ = " << (double) (m_cpt_update_local + m_cpt_update_remote) / m_cpt_update << std::endl + << "[116] AV. LOC UPDT PER UP REQ = " << (double) m_cpt_update_local / m_cpt_update << std::endl + << "[117] AV. REMOTE UPDT PER UP REQ = " << (double) m_cpt_update_remote / m_cpt_update << std::endl + << std::endl + << "[118] INVAL MULTICAST RATE = " << (double) m_cpt_minval / m_cpt_cycles << std::endl + << "[119] AVE. INVAL PER M_INV = " << (double) (m_cpt_minval_local + m_cpt_minval_remote) / m_cpt_minval << std::endl + << "[120] AV. LOC INV PER M_INV = " << (double) m_cpt_minval_local / m_cpt_minval << std::endl + << "[121] AV. REM INV PER M_INV = " << (double) m_cpt_minval_remote / m_cpt_minval << std::endl + << std::endl + << "[122] INVAL BROADCAST RATE = " << (double) m_cpt_binval / m_cpt_cycles << std::endl + << "[123] WRITE DIRTY RATE = " << (double) m_cpt_write_dirty / m_cpt_cycles << std::endl + << std::endl + << "[124] CLEANUP RATE = " << (double) (m_cpt_cleanup_local + m_cpt_cleanup_remote) / m_cpt_cycles << std::endl + << "[125] LOCAL CLEANUP RATE = " << (double) m_cpt_cleanup_local / m_cpt_cycles << std::endl + << "[126] REMOTE CLEANUP RATE = " << (double) m_cpt_cleanup_remote / m_cpt_cycles << std::endl + << "[127] LL RATE = " << (double) (m_cpt_ll_local + m_cpt_ll_remote) / m_cpt_cycles << std::endl + << "[128] LOCAL LL RATE = " << (double) m_cpt_ll_local / m_cpt_cycles << std::endl + << "[129] REMOTE LL RATE = " << (double) m_cpt_ll_remote / m_cpt_cycles << std::endl + << "[130] SC RATE = " << (double) (m_cpt_sc_local + m_cpt_sc_remote) / m_cpt_cycles << std::endl + << "[131] LOCAL SC RATE = " << (double) m_cpt_sc_local / m_cpt_cycles << std::endl + << "[132] REMOTE SC RATE = " << (double) m_cpt_sc_remote / m_cpt_cycles << std::endl + << "[133] CAS RATE = " << (double) (m_cpt_cas_local + m_cpt_cas_remote) / m_cpt_cycles << std::endl + << "[134] LOCAL CAS RATE = " << (double) m_cpt_cas_local / m_cpt_cycles << std::endl + << "[135] REMOTE CAS RATE = " << (double) m_cpt_cas_remote / m_cpt_cycles << std::endl + << std::endl + << std::endl; + } + } + + + ///////////////////////////////// + tmpl(/**/)::~VciMemCache() + ///////////////////////////////// + { + delete [] m_seg; + + delete [] r_ixr_rsp_to_xram_rsp_rok; + delete [] r_xram_rsp_victim_data; + delete [] r_xram_rsp_to_tgt_rsp_data; + + delete [] r_read_data; + delete [] r_read_to_tgt_rsp_data; + + delete [] r_write_data; + delete [] r_write_be; + delete [] r_write_to_cc_send_data; + delete [] r_write_to_cc_send_be; + + delete [] r_cas_data; + delete [] r_cas_rdata; + + delete [] r_ixr_cmd_wdata; + delete [] m_debug_previous_data; + delete [] m_debug_data; + + print_stats(); + } + + ////////////////////////////////// + tmpl(void) ::transition() + ////////////////////////////////// + { + using soclib::common::uint32_log2; + + // RESET + if (! p_resetn.read()) + { + + // Initializing FSMs + r_tgt_cmd_fsm = TGT_CMD_IDLE; + r_config_fsm = CONFIG_IDLE; + r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + r_multi_ack_fsm = MULTI_ACK_IDLE; + r_read_fsm = READ_IDLE; + r_write_fsm = WRITE_IDLE; + r_cas_fsm = CAS_IDLE; + r_cleanup_fsm = CLEANUP_IDLE; + r_alloc_dir_fsm = ALLOC_DIR_RESET; + r_alloc_heap_fsm = ALLOC_HEAP_RESET; + r_alloc_trt_fsm = ALLOC_TRT_READ; + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + r_ixr_rsp_fsm = IXR_RSP_IDLE; + r_xram_rsp_fsm = XRAM_RSP_IDLE; + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + + m_debug = false; + m_debug_previous_valid = false; + m_debug_previous_dirty = false; + m_debug_previous_count = 0; + + // Initializing Tables + m_trt.init(); + m_upt.init(); + m_ivt.init(); + m_llsc_table.init(); + + // initializing FIFOs and communication Buffers + + m_cmd_read_addr_fifo.init(); + m_cmd_read_length_fifo.init(); + m_cmd_read_srcid_fifo.init(); + m_cmd_read_trdid_fifo.init(); + m_cmd_read_pktid_fifo.init(); + + m_cmd_write_addr_fifo.init(); + m_cmd_write_eop_fifo.init(); + m_cmd_write_srcid_fifo.init(); + m_cmd_write_trdid_fifo.init(); + m_cmd_write_pktid_fifo.init(); + m_cmd_write_data_fifo.init(); + + m_cmd_cas_addr_fifo.init() ; + m_cmd_cas_srcid_fifo.init() ; + m_cmd_cas_trdid_fifo.init() ; + m_cmd_cas_pktid_fifo.init() ; + m_cmd_cas_wdata_fifo.init() ; + m_cmd_cas_eop_fifo.init() ; + + r_config_cmd = MEMC_CMD_NOP; + r_config_lock = false; + + m_config_to_cc_send_inst_fifo.init(); + m_config_to_cc_send_srcid_fifo.init(); + + r_tgt_cmd_to_tgt_rsp_req = false; + + r_read_to_tgt_rsp_req = false; + r_read_to_ixr_cmd_req = false; + + r_write_to_tgt_rsp_req = false; + r_write_to_ixr_cmd_req = false; + r_write_to_cc_send_multi_req = false; + r_write_to_cc_send_brdcast_req = false; + r_write_to_multi_ack_req = false; + + m_write_to_cc_send_inst_fifo.init(); + m_write_to_cc_send_srcid_fifo.init(); + + r_cleanup_to_tgt_rsp_req = false; + + m_cc_receive_to_cleanup_fifo.init(); + + r_multi_ack_to_tgt_rsp_req = false; + + m_cc_receive_to_multi_ack_fifo.init(); + + r_cas_to_tgt_rsp_req = false; + r_cas_cpt = 0 ; + r_cas_lfsr = -1 ; + r_cas_to_ixr_cmd_req = false; + r_cas_to_cc_send_multi_req = false; + r_cas_to_cc_send_brdcast_req = false; + + m_cas_to_cc_send_inst_fifo.init(); + m_cas_to_cc_send_srcid_fifo.init(); + + for (size_t i = 0; i < m_trt_lines ; i++) + { + r_ixr_rsp_to_xram_rsp_rok[i] = false; + } + + r_xram_rsp_to_tgt_rsp_req = false; + r_xram_rsp_to_cc_send_multi_req = false; + r_xram_rsp_to_cc_send_brdcast_req = false; + r_xram_rsp_to_ixr_cmd_req = false; + r_xram_rsp_trt_index = 0; + r_xram_rsp_rerror_irq = false; + r_xram_rsp_rerror_irq_enable = false; + + m_xram_rsp_to_cc_send_inst_fifo.init(); + m_xram_rsp_to_cc_send_srcid_fifo.init(); + + r_alloc_dir_reset_cpt = 0; + r_alloc_heap_reset_cpt = 0; + + r_tgt_rsp_key_sent = false; + + // Activity counters + m_cpt_cycles = 0; + m_cpt_read_local = 0; + m_cpt_read_remote = 0; + m_cpt_read_cost = 0; + m_cpt_write_local = 0; + m_cpt_write_remote = 0; + m_cpt_write_flits_local = 0; + m_cpt_write_flits_remote = 0; + m_cpt_write_cost = 0; + m_cpt_ll_local = 0; + m_cpt_ll_remote = 0; + m_cpt_ll_cost = 0; + m_cpt_sc_local = 0; + m_cpt_sc_remote = 0; + m_cpt_sc_cost = 0; + m_cpt_cas_local = 0; + m_cpt_cas_remote = 0; + m_cpt_cas_cost = 0; + m_cpt_update = 0; + m_cpt_update_local = 0; + m_cpt_update_remote = 0; + m_cpt_update_cost = 0; + m_cpt_minval = 0; + m_cpt_minval_local = 0; + m_cpt_minval_remote = 0; + m_cpt_minval_cost = 0; + m_cpt_binval = 0; + m_cpt_cleanup_local = 0; + m_cpt_cleanup_remote = 0; + m_cpt_cleanup_cost = 0; + + m_cpt_read_miss = 0; + m_cpt_write_miss = 0; + m_cpt_write_dirty = 0; + m_cpt_write_broadcast = 0; + m_cpt_trt_rb = 0; + m_cpt_trt_full = 0; + m_cpt_get = 0; + m_cpt_put = 0; + + return; + } + + bool cmd_read_fifo_put = false; + bool cmd_read_fifo_get = false; + + bool cmd_write_fifo_put = false; + bool cmd_write_fifo_get = false; + + bool cmd_cas_fifo_put = false; + bool cmd_cas_fifo_get = false; + + bool cc_receive_to_cleanup_fifo_get = false; + bool cc_receive_to_cleanup_fifo_put = false; + + bool cc_receive_to_multi_ack_fifo_get = false; + bool cc_receive_to_multi_ack_fifo_put = false; + + bool write_to_cc_send_fifo_put = false; + bool write_to_cc_send_fifo_get = false; + bool write_to_cc_send_fifo_inst = false; + size_t write_to_cc_send_fifo_srcid = 0; + + bool xram_rsp_to_cc_send_fifo_put = false; + bool xram_rsp_to_cc_send_fifo_get = false; + bool xram_rsp_to_cc_send_fifo_inst = false; + size_t xram_rsp_to_cc_send_fifo_srcid = 0; + + bool config_rsp_lines_incr = false; + bool config_rsp_lines_cleanup_decr = false; + bool config_rsp_lines_ixr_rsp_decr = false; + + bool config_to_cc_send_fifo_put = false; + bool config_to_cc_send_fifo_get = false; + bool config_to_cc_send_fifo_inst = false; + size_t config_to_cc_send_fifo_srcid = 0; + + bool cas_to_cc_send_fifo_put = false; + bool cas_to_cc_send_fifo_get = false; + bool cas_to_cc_send_fifo_inst = false; + size_t cas_to_cc_send_fifo_srcid = 0; + + m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + +#if DEBUG_MEMC_GLOBAL + if (m_debug) + { + std::cout + << "---------------------------------------------" << std::dec << std::endl + << "MEM_CACHE " << name() + << " ; Time = " << m_cpt_cycles << std::endl + << " - TGT_CMD FSM = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()] << std::endl + << " - TGT_RSP FSM = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()] << std::endl + << " - CC_SEND FSM = " << cc_send_fsm_str[r_cc_send_fsm.read()] << std::endl + << " - CC_RECEIVE FSM = " << cc_receive_fsm_str[r_cc_receive_fsm.read()] << std::endl + << " - MULTI_ACK FSM = " << multi_ack_fsm_str[r_multi_ack_fsm.read()] << std::endl + << " - READ FSM = " << read_fsm_str[r_read_fsm.read()] << std::endl + << " - WRITE FSM = " << write_fsm_str[r_write_fsm.read()] << std::endl + << " - CAS FSM = " << cas_fsm_str[r_cas_fsm.read()] << std::endl + << " - CLEANUP FSM = " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl + << " - IXR_CMD FSM = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] << std::endl + << " - IXR_RSP FSM = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] << std::endl + << " - XRAM_RSP FSM = " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl + << " - ALLOC_DIR FSM = " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] << std::endl + << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] << std::endl + << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] << std::endl + << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; + } +#endif + + //////////////////////////////////////////////////////////////////////////////////// + // TGT_CMD FSM + //////////////////////////////////////////////////////////////////////////////////// + // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors, + // and dispatch these commands to the proper FSM through dedicated FIFOs. + // + // There are 5 types of commands accepted in the XRAM segment: + // - READ : A READ request has a length of 1 VCI flit. It can be a single word + // or an entire cache line, depending on the PLEN value => READ FSM + // - WRITE : A WRITE request has a maximum length of 16 flits, and can only + // concern words in a same line => WRITE FSM + // - CAS : A CAS request has a length of 2 flits or 4 flits => CAS FSM + // - LL : An LL request has a length of 1 flit => READ FSM + // - SC : An SC request has a length of 2 flits. First flit contains the + // acces key, second flit the data to write => WRITE FSM. + // + // The READ/WRITE commands accepted in the configuration segment are targeting + // configuration or status registers. They must contain one single flit. + // - For almost all addressable registers, the response is returned immediately. + // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed. + //////////////////////////////////////////////////////////////////////////////////// + + + switch (r_tgt_cmd_fsm.read()) + { + ////////////////// + case TGT_CMD_IDLE: // waiting a VCI command (RAM or CONFIG) + if (p_vci_tgt.cmdval) + { + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Receive command from srcid " + << std::hex << p_vci_tgt.srcid.read() + << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; +#endif + // checking segmentation violation + addr_t address = p_vci_tgt.address.read(); + uint32_t plen = p_vci_tgt.plen.read(); + bool config = false; + + for (size_t seg_id = 0; (seg_id < m_nseg) ; seg_id++) + { + if (m_seg[seg_id]->contains(address) && + m_seg[seg_id]->contains(address + plen - vci_param_int::B)) + { + if (m_seg[seg_id]->special()) config = true; + } + } + + if (config) /////////// configuration command + { + if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR; + else r_tgt_cmd_fsm = TGT_CMD_CONFIG; + } + else //////////// memory access + { + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + // check that the pktid is either : + // TYPE_READ_DATA_UNC + // TYPE_READ_DATA_MISS + // TYPE_READ_INS_UNC + // TYPE_READ_INS_MISS + // ==> bit2 must be zero with the TSAR encoding + // ==> mask = 0b0100 = 0x4 + assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) and + "The type specified in the pktid field is incompatible with the READ CMD"); + r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + { + // check that the pktid is TYPE_WRITE + // ==> TYPE_WRITE = X100 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert((((p_vci_tgt.pktid.read() & 0x7) == 0x4) or ((p_vci_tgt.pktid.read() & 0x7) == 0x0)) and + "The type specified in the pktid field is incompatible with the WRITE CMD"); + r_tgt_cmd_fsm = TGT_CMD_WRITE; + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) + { + // check that the pktid is TYPE_LL + // ==> TYPE_LL = X110 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) and + "The type specified in the pktid field is incompatible with the LL CMD"); + r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) + { + // check that the pktid is either : + // TYPE_CAS + // TYPE_SC + // ==> TYPE_CAS = X101 with the TSAR encoding + // ==> TYPE_SC = X111 with the TSAR encoding + // ==> mask = 0b0101 = 0x5 + assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) and + "The type specified in the pktid field is incompatible with the NOP CMD"); + + if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; + else r_tgt_cmd_fsm = TGT_CMD_WRITE; + } + else + { + r_tgt_cmd_fsm = TGT_CMD_ERROR; + } + } + } + break; + + /////////////////// + case TGT_CMD_ERROR: // response error must be sent + + // wait if pending request + if (r_tgt_cmd_to_tgt_rsp_req.read()) break; + + // consume all the command packet flits before sending response error + if (p_vci_tgt.cmdval and p_vci_tgt.eop) + { + r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); + r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); + r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); + r_tgt_cmd_to_tgt_rsp_req = true; + r_tgt_cmd_to_tgt_rsp_error = 1; + r_tgt_cmd_fsm = TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Segmentation violation:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + + } + break; + + //////////////////// + case TGT_CMD_CONFIG: // execute config request and return response + { + /////////////////////////////////////////////////////////// + // Decoding CONFIG interface commands // + // // + // VCI ADDRESS // + // ================================================ // + // GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // + // IDX | IDX | | (3 bits) | (7 bits) | // + // ================================================ // + // // + // For instrumentation : FUNC_IDX = 0b001 // + // // + // REGS_IDX // + // ============================================ // + // Z | Y | X | W // + // (1 bit) | (2 bits) | (3 bits) | (1 bit) // + // ============================================ // + // // + // Z : DIRECT / COHERENCE // + // Y : SUBTYPE ( LOCAL, REMOTE, OTHER ) // + // X : REGISTER INDEX // + // W : HI / LO // + // // + // For configuration: FUNC_IDX = 0b000 // + // // + // REGS_IDX // + // ============================================ // + // RESERVED | X | // + // (4 bits) | (3 bits) | // + // ============================================ // + // // + // X : REGISTER INDEX // + // // + // For WRITE MISS error signaling: FUNC = 0x010 // + // // + // REGS_IDX // + // ============================================ // + // RESERVED | X | // + // (4 bits) | (3 bits) | // + // ============================================ // + // // + // X : REGISTER INDEX // + // // + /////////////////////////////////////////////////////////// + + addr_t addr_lsb = p_vci_tgt.address.read() & + m_config_addr_mask; + + addr_t cell = (addr_lsb / vci_param_int::B); + + size_t regr = cell & + m_config_regr_idx_mask; + + size_t func = (cell >> m_config_regr_width) & + m_config_func_idx_mask; + + bool need_rsp; + int error; + uint32_t rdata = 0; // default value + uint32_t wdata = p_vci_tgt.wdata.read(); + + switch(func) + { + // memory operation + case MEMC_CONFIG: + { + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock + and (regr == MEMC_LOCK)) + { + rdata = (uint32_t) r_config_lock.read(); + need_rsp = true; + error = 0; + r_config_lock = true; + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock + and (regr == MEMC_LOCK)) + { + need_rsp = true; + error = 0; + r_config_lock = false; + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo + and (regr == MEMC_ADDR_LO)) + { + assert( ((wdata % (m_words * vci_param_int::B)) == 0) and + "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); + + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | + ((addr_t)wdata); + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi + and (regr == MEMC_ADDR_HI)) + + { + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | + (((addr_t) wdata) << 32); + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines + and (regr == MEMC_BUF_LENGTH)) + { + need_rsp = true; + error = 0; + size_t lines = wdata / (m_words << 2); + if (wdata % (m_words << 2)) lines++; + r_config_cmd_lines = lines; + r_config_rsp_lines = 0; + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type + and (regr == MEMC_CMD_TYPE)) + { + need_rsp = false; + error = 0; + r_config_cmd = wdata; + + // prepare delayed response from CONFIG FSM + r_config_srcid = p_vci_tgt.srcid.read(); + r_config_trdid = p_vci_tgt.trdid.read(); + r_config_pktid = p_vci_tgt.pktid.read(); + } + else + { + need_rsp = true; + error = 1; + } + + break; + } + + // instrumentation registers + case MEMC_INSTRM: + { + need_rsp = true; + + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + error = read_instrumentation(regr, rdata); + } + else + { + error = 1; + } + + break; + } + + // xram GET bus error registers + case MEMC_RERROR: + { + need_rsp = true; + error = 0; + + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + { + switch (regr) + { + case MEMC_RERROR_IRQ_ENABLE: + r_xram_rsp_rerror_irq_enable = + (p_vci_tgt.wdata.read() != 0); + + break; + + default: + error = 1; + break; + } + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + switch (regr) + { + case MEMC_RERROR_SRCID: + rdata = (uint32_t) + r_xram_rsp_rerror_rsrcid.read(); + + break; + + case MEMC_RERROR_ADDR_LO: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read()) & + ((1ULL<<32)-1); + + break; + + case MEMC_RERROR_ADDR_HI: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read() >> 32) & + ((1ULL<<32)-1); + + break; + + case MEMC_RERROR_IRQ_RESET: + if (not r_xram_rsp_rerror_irq.read()) break; + + r_xram_rsp_rerror_irq = false; + + break; + + case MEMC_RERROR_IRQ_ENABLE: + rdata = (uint32_t) + (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0; + + break; + + default: + error = 1; + break; + } + } + else + { + error = 1; + } + + break; + } + + //unknown function + default: + { + need_rsp = true; + error = 1; + + break; + } + } + + if (need_rsp) + { + // blocked if previous pending request to TGT_RSP FSM + if (r_tgt_cmd_to_tgt_rsp_req.read()) break; + + r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); + r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); + r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); + r_tgt_cmd_to_tgt_rsp_req = true; + r_tgt_cmd_to_tgt_rsp_error = error; + r_tgt_cmd_to_tgt_rsp_rdata = rdata; + } + + r_tgt_cmd_fsm = TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Configuration request:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / func = " << func + << " / regr = " << regr + << " / rdata = " << rdata + << " / wdata = " << p_vci_tgt.wdata.read() + << " / need_rsp = " << need_rsp + << " / error = " << error << std::endl; +#endif + break; + } + ////////////////// + case TGT_CMD_READ: // Push a read request into read fifo + + // check that the read does not cross a cache line limit. + if (((m_x[(addr_t) p_vci_tgt.address.read()] + (p_vci_tgt.plen.read() >> 2)) > 16) and + (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ)) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " illegal address/plen for VCI read command" << std::endl; + exit(0); + } + // check single flit + if (!p_vci_tgt.eop.read()) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " read command packet must contain one single flit" << std::endl; + exit(0); + } + // check plen for LL + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and + (p_vci_tgt.plen.read() != 8)) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " ll command packets must have a plen of 8" << std::endl; + exit(0); + } + + if (p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok()) + { + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Push into read_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + cmd_read_fifo_put = true; + // + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_ll_local++; + else m_cpt_ll_remote++; + m_cpt_ll_cost += req_distance(p_vci_tgt.srcid.read()); // LL on a single word + } + else { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_local++; + else m_cpt_read_remote++; + m_cpt_read_cost += req_distance(p_vci_tgt.srcid.read()); + } + // + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + break; + + /////////////////// + case TGT_CMD_WRITE: + if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok()) + { + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Push into write_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / wdata = " << p_vci_tgt.wdata.read() + << " / be = " << p_vci_tgt.be.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + cmd_write_fifo_put = true; + // + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { + m_cpt_sc_cost += req_distance(p_vci_tgt.srcid.read()); + } + else { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_flits_local++; + else m_cpt_write_flits_remote++; + m_cpt_write_cost += req_distance(p_vci_tgt.srcid.read()); + } + // + + if (p_vci_tgt.eop) { + // + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_sc_local++; + else m_cpt_sc_remote++; + + } + else { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_local++; + else m_cpt_write_remote++; + } + // + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + } + break; + + ///////////////// + case TGT_CMD_CAS: + if ((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16)) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" + << "illegal format for CAS command " << std::endl; + exit(0); + } + + if (p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok()) + { + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Pushing command into cmd_cas_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " srcid = " << p_vci_tgt.srcid.read() + << " trdid = " << p_vci_tgt.trdid.read() + << " pktid = " << p_vci_tgt.pktid.read() + << " wdata = " << p_vci_tgt.wdata.read() + << " be = " << p_vci_tgt.be.read() + << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + cmd_cas_fifo_put = true; + if (p_vci_tgt.eop) { + // + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_cas_local++; + else m_cpt_cas_remote++; + m_cpt_cas_cost += req_distance(p_vci_tgt.srcid.read()); + // + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + } + break; + } // end switch tgt_cmd_fsm + + ///////////////////////////////////////////////////////////////////////// + // MULTI_ACK FSM + ///////////////////////////////////////////////////////////////////////// + // This FSM controls the response to the multicast update requests sent + // by the memory cache to the L1 caches and update the UPT. + // + // - The FSM decrements the proper entry in UPT, + // and clear the UPT entry when all responses have been received. + // - If required, it sends a request to the TGT_RSP FSM to complete + // a pending write transaction. + // + // All those multi-ack packets are one flit packet. + // The index in the UPT is defined in the TRDID field. + //////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "multi_ack_fsm" << std::endl; + + switch(r_multi_ack_fsm.read()) + { + //////////////////// + case MULTI_ACK_IDLE: + { + bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok(); + + // No CC_RECEIVE FSM request and no WRITE FSM request + if (not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read()) + break; + + uint8_t updt_index; + + // handling WRITE FSM request to decrement update table response + // counter if no CC_RECEIVE FSM request + if (not multi_ack_fifo_rok) + { + updt_index = r_write_to_multi_ack_upt_index.read(); + r_write_to_multi_ack_req = false; + } + // Handling CC_RECEIVE FSM request + else + { + uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); + updt_index = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + + cc_receive_to_multi_ack_fifo_get = true; + } + + assert((updt_index < m_upt.size()) and + "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : " + "index too large for UPT"); + + r_multi_ack_upt_index = updt_index; + r_multi_ack_fsm = MULTI_ACK_UPT_LOCK; + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + { + if (multi_ack_fifo_rok) + { + std::cout << " Response for UPT entry " + << (size_t)updt_index << std::endl; + } + else + { + std::cout << " Write FSM request to decrement UPT entry " + << updt_index << std::endl; + } + } +#endif + break; + } + + //////////////////////// + case MULTI_ACK_UPT_LOCK: + { + // get lock to the UPDATE table + if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; + + // decrement the number of expected responses + size_t count = 0; + bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); + + if (not valid) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_LOCK state" << std::endl + << "unsuccessful access to decrement the UPT" << std::endl; + exit(0); + } + + if (count == 0) + { + r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR; + } + else + { + r_multi_ack_fsm = MULTI_ACK_IDLE; + } + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + std::cout << " Decrement the responses counter for UPT:" + << " entry = " << r_multi_ack_upt_index.read() + << " / rsp_count = " << std::dec << count << std::endl; +#endif + break; + } + + ///////////////////////// + case MULTI_ACK_UPT_CLEAR: // Clear UPT entry / Test if rsp or ack required + { + if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_CLEAR state" + << " bad UPT allocation" << std::endl; + exit(0); + } + + r_multi_ack_srcid = m_upt.srcid(r_multi_ack_upt_index.read()); + r_multi_ack_trdid = m_upt.trdid(r_multi_ack_upt_index.read()); + r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read()); + r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); + bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); + + // clear the UPT entry + m_upt.clear(r_multi_ack_upt_index.read()); + + if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; + else r_multi_ack_fsm = MULTI_ACK_IDLE; + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + std::cout << " Clear UPT entry " + << std::dec << r_multi_ack_upt_index.read() << std::endl; +#endif + break; + } + ///////////////////////// + case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM + // Wait if pending request + { + if (r_multi_ack_to_tgt_rsp_req.read()) break; + + r_multi_ack_to_tgt_rsp_req = true; + r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); + r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); + r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); + r_multi_ack_fsm = MULTI_ACK_IDLE; + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + std::cout << " " + << " Request TGT_RSP FSM to send a response to srcid " + << std::hex << r_multi_ack_srcid.read() << std::endl; +#endif + break; + } + } // end switch r_multi_ack_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // CONFIG FSM + //////////////////////////////////////////////////////////////////////////////////// + // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC). + // The target buffer can have any size, and there is one single command for + // all cache lines covered by the target buffer. + // + // An INVAL or SYNC configuration operation is defined by the following registers: + // - bool r_config_cmd : INVAL / SYNC / NOP + // - uint64_t r_config_address : buffer base address + // - uint32_t r_config_cmd_lines : number of lines to be handled + // - uint32_t r_config_rsp_lines : number of lines not completed + // + // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling + // all cache lines covered by the buffer. The various lines of a given buffer + // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send + // the command for line (n+1). It decrements the r_config_cmd_lines counter until + // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL). + // The r_config_rsp_lines counter contains the number of expected responses from + // CLEANUP FSM (inval) or from IXR_RSP FSM (sync). This register is incremented by + // the CONFIG FSM (each time a transaction is requested), and decremented by the + // CLEANUP or IXR_RSP FSMs(each time a response is received. As this register can + // be concurently accessed by those three FSMs, it is implemented as an [incr/decr] + // counter. + // + // - INVAL request: + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // In case of hit, with no copies in L1 caches, the line is invalidated and + // a response is requested to TGT_RSP FSM. + // If there is copies, a multi-inval, or a broadcast-inval coherence transaction + // is launched and registered in UPT. The multi-inval transaction completion + // is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter. + // The CONFIG INVAL response is sent only when the last line has been invalidated. + // There is no PUT transaction to XRAM, even if the invalidated line is dirty... + // TODO : The target buffer address must be aligned on a cache line boundary. + // This constraint can be released, but it requires to make 2 PUT transactions + // for the first and the last line... + // + // - SYNC request: + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // In case of hit, a PUT transaction is registered in TRT and a request is sent + // to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter + // when a PUT response is received. + // The CONFIG SYNC response is sent only when the last PUT response is received. + // + // From the software point of view, a configuration request is a sequence + // of 6 atomic accesses in an uncached segment. A dedicated lock is used + // to handle only one configuration command at a given time: + // - Read MEMC_LOCK : Get the lock + // - Write MEMC_ADDR_LO : Set the buffer address LSB + // - Write MEMC_ADDR_HI : Set the buffer address MSB + // - Write MEMC_BUF_LENGTH : set buffer length (bytes) + // - Write MEMC_CMD_TYPE : launch the actual operation + // - WRITE MEMC_LOCK : release the lock + //////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "config_fsm" << std::endl; + + switch( r_config_fsm.read()) + { + ///////////////// + case CONFIG_IDLE: // waiting a config request + { + if (r_config_cmd.read() != MEMC_CMD_NOP ) + { + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) + std::cout << " Config Request received" + << " / address = " << std::hex << r_config_address.read() + << " / lines = " << std::dec << r_config_cmd_lines.read() + << " / type = " << r_config_cmd.read() << std::endl; +#endif + } + break; + } + ///////////////// + case CONFIG_LOOP: // test if last line to be handled + { + if (r_config_cmd_lines.read() == 0 ) + { + r_config_cmd = MEMC_CMD_NOP; + r_config_fsm = CONFIG_WAIT; + } + else + { + r_config_fsm = CONFIG_DIR_REQ; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " / address = " << std::hex << r_config_address.read() + << " / lines not handled = " << std::dec << r_config_cmd_lines.read() + << " / command = " << r_config_cmd.read() << std::endl; +#endif + break; + } + ///////////////// + case CONFIG_WAIT: // wait completion (last response) + { + if (r_config_rsp_lines.read() == 0 ) // last response received + { + r_config_fsm = CONFIG_RSP; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; +#endif + break; + } + //////////////// + case CONFIG_RSP: // request TGT_RSP FSM to return response + { + if (not r_config_to_tgt_rsp_req.read()) + { + r_config_to_tgt_rsp_srcid = r_config_srcid.read(); + r_config_to_tgt_rsp_trdid = r_config_trdid.read(); + r_config_to_tgt_rsp_pktid = r_config_pktid.read(); + r_config_to_tgt_rsp_error = false; + r_config_to_tgt_rsp_req = true; + r_config_fsm = CONFIG_IDLE; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " Request TGT_RSP FSM to send response:" + << " error = " << r_config_to_tgt_rsp_error.read() + << " / rsrcid = " << std::hex << r_config_srcid.read() + << " / rtrdid = " << std::hex << r_config_trdid.read() + << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; +#endif + } + break; + } + //////////////////// + case CONFIG_DIR_REQ: // Request directory lock + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG ) + { + r_config_fsm = CONFIG_DIR_ACCESS; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Request DIR access" << std::endl; +#endif + break; + } + /////////////////////// + case CONFIG_DIR_ACCESS: // Access directory and decode config command + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way); + + r_config_dir_way = way; + r_config_dir_copy_inst = entry.owner.inst; + r_config_dir_copy_srcid = entry.owner.srcid; + r_config_dir_is_cnt = entry.is_cnt; + r_config_dir_lock = entry.lock; + r_config_dir_count = entry.count; + r_config_dir_ptr = entry.ptr; + + if (entry.valid and // hit & inval command + (r_config_cmd.read() == MEMC_CMD_INVAL)) + { + r_config_fsm = CONFIG_IVT_LOCK; + } + else if (entry.valid and // hit & sync command + entry.dirty and + (r_config_cmd.read() == MEMC_CMD_SYNC)) + { + r_config_fsm = CONFIG_TRT_LOCK; + } + else // miss : return to LOOP + { + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " Accessing directory: " + << " address = " << std::hex << r_config_address.read() + << " / hit = " << std::dec << entry.valid + << " / dirty = " << entry.dirty + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + break; + } + ///////////////////// + case CONFIG_TRT_LOCK: // enter this state in case of SYNC command + // to a dirty cache line + // keep DIR lock, and try to get TRT lock + // return to LOOP state if TRT full + // reset dirty bit in DIR and register a PUT + // transaction in TRT if not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation"); + + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG ) + { + size_t index = 0; + bool wok = not m_trt.full(index); + + if (not wok ) + { + r_config_fsm = CONFIG_LOOP; + } + else + { + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + + // reset dirty bit in DIR + DirectoryEntry entry; + entry.valid = true; + entry.dirty = false; + entry.tag = m_z[r_config_address.read()]; + entry.is_cnt = r_config_dir_is_cnt.read(); + entry.lock = r_config_dir_lock.read(); + entry.ptr = r_config_dir_ptr.read(); + entry.count = r_config_dir_count.read(); + entry.owner.inst = r_config_dir_copy_inst.read(); + entry.owner.srcid = r_config_dir_copy_srcid.read(); + m_cache_directory.write( set, way, entry ); + + r_config_trt_index = index; + r_config_fsm = CONFIG_TRT_SET; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " Access TRT: " + << " wok = " << std::dec << wok + << " index = " << index << std::endl; +#endif + } + break; + } + //////////////////// + case CONFIG_TRT_SET: // read data in cache + // and post a PUT request in TRT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation"); + + // read data into cache + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + std::vector data_vector; + data_vector.clear(); + for(size_t word=0; word(m_words,0xF), // byte-enable: unused + data_vector, // data to be written + 0, // ll_key: unused + true ); // requested by config FSM + config_rsp_lines_incr = true; + r_config_fsm = CONFIG_PUT_REQ; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " PUT request in TRT:" + << " address = " << std::hex << r_config_address.read() + << " index = " << std::dec << r_config_trt_index.read() << std::endl; +#endif + break; + } + //////////////////// + case CONFIG_PUT_REQ: // post PUT request to IXR_CMD_FSM + { + if (not r_config_to_ixr_cmd_req.read()) + { + r_config_to_ixr_cmd_req = true; + r_config_to_ixr_cmd_index = r_config_trt_index.read(); + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " post PUT request to IXR_CMD_FSM" + << " / address = " << std::hex << r_config_address.read() << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_IVT_LOCK: // enter this state in case of INVAL command + // Keep DIR lock and Try to get IVT lock. + // Return to LOOP state if IVT full. + // Register inval in IVT, and invalidate the + // directory if IVT not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) + { + size_t set = m_y[(addr_t)(r_config_address.read())]; + size_t way = r_config_dir_way.read(); + + if (r_config_dir_count.read() == 0 ) // inval DIR and return to LOOP + { + m_cache_directory.inval( way, set ); + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " No copies in L1 : inval DIR entry" << std::endl; +#endif + } + else // try to register inval in IVT + { + bool wok = false; + size_t index = 0; + bool broadcast = r_config_dir_is_cnt.read(); + size_t srcid = r_config_srcid.read(); + size_t trdid = r_config_trdid.read(); + size_t pktid = r_config_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_config_address.read())]; + size_t nb_copies = r_config_dir_count.read(); + + wok = m_ivt.set( false, // it's an inval transaction + broadcast, + false, // no response required + true, // acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index ); + + if (wok ) // IVT success => inval DIR slot + { + m_cache_directory.inval( way, set ); + r_config_ivt_index = index; + config_rsp_lines_incr = true; + if (broadcast ) r_config_fsm = CONFIG_BC_SEND; + else r_config_fsm = CONFIG_INVAL_SEND; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Inval DIR entry and register inval in IVT" + << " / index = " << std::dec << index + << " / broadcast = " << broadcast << std::endl; +#endif + } + else // IVT full => release both DIR and IVT locks + { + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " IVT full : release DIR & IVT locks and retry" << std::endl; +#endif + } + } + } + break; + } + //////////////////// + case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM + { + if (not r_config_to_cc_send_multi_req.read() and + not r_config_to_cc_send_brdcast_req.read()) + { + // post bc inval request + r_config_to_cc_send_multi_req = false; + r_config_to_cc_send_brdcast_req = true; + r_config_to_cc_send_trdid = r_config_ivt_index.read(); + r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Post a broadcast inval request to CC_SEND FSM" + << " / address = " << r_config_address.read() <" + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << r_config_dir_copy_srcid.read() + << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_HEAP_REQ: // Try to get access to Heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG ) + { + r_config_fsm = CONFIG_HEAP_SCAN; + r_config_heap_next = r_config_dir_ptr.read(); + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Requesting HEAP lock" << std::endl; +#endif + break; + } + ////////////////////// + case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM + { + HeapEntry entry = m_heap.read( r_config_heap_next.read()); + bool last_copy = (entry.next == r_config_heap_next.read()); + + config_to_cc_send_fifo_srcid = entry.owner.srcid; + config_to_cc_send_fifo_inst = entry.owner.inst; + // config_to_cc_send_fifo_last = last_copy; + config_to_cc_send_fifo_put = true; + + if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted + { + r_config_heap_next = entry.next; + if (last_copy ) r_config_fsm = CONFIG_HEAP_LAST; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; +#endif + break; + } + ////////////////////// + case CONFIG_HEAP_LAST: // HEAP housekeeping + { + size_t free_pointer = m_heap.next_free_ptr(); + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + + if (m_heap.is_full()) + { + last_entry.next = r_config_dir_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = free_pointer; + } + + m_heap.write_free_ptr( r_config_dir_ptr.read()); + m_heap.write( r_config_heap_next.read(), last_entry ); + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Heap housekeeping" << std::endl; +#endif + break; + } + } // end switch r_config_fsm + + + + //////////////////////////////////////////////////////////////////////////////////// + // READ FSM + //////////////////////////////////////////////////////////////////////////////////// + // The READ FSM controls the VCI read and ll requests. + // It takes the lock protecting the cache directory to check the cache line status: + // - In case of HIT + // The fsm copies the data (one line, or one single word) + // in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty. + // The requesting initiator is registered in the cache directory. + // If the number of copy is larger than 1, the new copy is registered + // in the HEAP. + // If the number of copy is larger than the threshold, the HEAP is cleared, + // and the corresponding line switches to the counter mode. + // - In case of MISS + // The READ fsm takes the lock protecting the transaction tab. + // If a read transaction to the XRAM for this line already exists, + // or if the transaction tab is full, the fsm is stalled. + // If a TRT entry is free, the READ request is registered in TRT, + // it is consumed in the request FIFO, and transmited to the IXR_CMD FSM. + // The READ FSM returns in the IDLE state as the read transaction will be + // completed when the missing line will be received. + //////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "read_fsm" << std::endl; + + switch(r_read_fsm.read()) + { + /////////////// + case READ_IDLE: // waiting a read request + { + if (m_cmd_read_addr_fifo.rok()) + { + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; +#endif + r_read_fsm = READ_DIR_REQ; + } + break; + } + ////////////////// + case READ_DIR_REQ: // Get the lock to the directory + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + r_read_fsm = READ_DIR_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Requesting DIR lock " << std::endl; +#endif + break; + } + + /////////////////// + case READ_DIR_LOCK: // check directory for hit / miss + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and + "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); + + // access the global table ONLY when we have an LL cmd + if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) + { + r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); + } + r_read_is_cnt = entry.is_cnt; + r_read_dirty = entry.dirty; + r_read_lock = entry.lock; + r_read_tag = entry.tag; + r_read_way = way; + r_read_count = entry.count; + r_read_copy = entry.owner.srcid; + r_read_copy_inst = entry.owner.inst; + r_read_ptr = entry.ptr; // pointer to the heap + + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); + if (entry.valid) // hit + { + // test if we need to register a new copy in the heap + if (entry.is_cnt or (entry.count == 0) or !cached_read) + { + r_read_fsm = READ_DIR_HIT; + } + else + { + r_read_fsm = READ_HEAP_REQ; + } + } + else // miss + { + r_read_fsm = READ_TRT_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + { + std::cout << " Accessing directory: " + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " < we must update the copies + { + if (!is_cnt) // Not counter mode + { + entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + entry.owner.inst = inst_read; + entry.count = r_read_count.read() + 1; + } + else // Counter mode + { + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.count = r_read_count.read() + 1; + } + } + else // Uncached read + { + entry.owner.srcid = r_read_copy.read(); + entry.owner.inst = r_read_copy_inst.read(); + entry.count = r_read_count.read(); + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Update directory entry:" + << " addr = " << std::hex << m_cmd_read_addr_fifo.read() + << " / set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + m_cache_directory.write(set, way, entry); + r_read_fsm = READ_RSP; + break; + } + /////////////////// + case READ_HEAP_REQ: // Get the lock to the HEAP directory + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + r_read_fsm = READ_HEAP_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " " + << " Requesting HEAP lock " << std::endl; +#endif + break; + } + + //////////////////// + case READ_HEAP_LOCK: // read data in cache, update the directory + // and prepare the HEAP update + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + // enter counter mode when we reach the limit of copies or the heap is full + bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); + + // read data in the cache + size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; + size_t way = r_read_way.read(); + + m_cache_data.read_line(way, set, r_read_data); + + // update the cache directory + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = go_cnt; + entry.dirty = r_read_dirty.read(); + entry.tag = r_read_tag.read(); + entry.lock = r_read_lock.read(); + entry.count = r_read_count.read() + 1; + + if (not go_cnt) // Not entering counter mode + { + entry.owner.srcid = r_read_copy.read(); + entry.owner.inst = r_read_copy_inst.read(); + entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap + } + else // Entering Counter mode + { + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + } + + m_cache_directory.write(set, way, entry); + + // prepare the heap update (add an entry, or clear the linked list) + if (not go_cnt) // not switching to counter mode + { + // We test if the next free entry in the heap is the last + HeapEntry heap_entry = m_heap.next_free_entry(); + r_read_next_ptr = heap_entry.next; + r_read_last_free = (heap_entry.next == m_heap.next_free_ptr()); + + r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP + } + else // switching to counter mode + { + if (r_read_count.read() >1) // heap must be cleared + { + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + r_read_next_ptr = m_heap.next_free_ptr(); + m_heap.write_free_ptr(r_read_ptr.read()); + + if (next_entry.next == r_read_ptr.read()) // last entry + { + r_read_fsm = READ_HEAP_LAST; // erase the entry + } + else // not the last entry + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; // erase the list + } + } + else // the heap is not used / nothing to do + { + r_read_fsm = READ_RSP; + } + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Update directory:" + << " tag = " << std::hex << entry.tag + << " set = " << std::dec << set + << " way = " << way + << " count = " << entry.count + << " is_cnt = " << entry.is_cnt << std::endl; +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ///////////////////// + case READ_HEAP_WRITE: // add an entry in the heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry heap_entry; + heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); + + if (r_read_count.read() == 1) // creation of a new linked list + { + heap_entry.next = m_heap.next_free_ptr(); + } + else // head insertion in existing list + { + heap_entry.next = r_read_ptr.read(); + } + m_heap.write_free_entry(heap_entry); + m_heap.write_free_ptr(r_read_next_ptr.read()); + if (r_read_last_free.read()) m_heap.set_full(); + + r_read_fsm = READ_RSP; + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Add an entry in the heap:" + << " owner_id = " << std::hex << heap_entry.owner.srcid + << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ///////////////////// + case READ_HEAP_ERASE: + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + if (next_entry.next == r_read_ptr.read()) + { + r_read_fsm = READ_HEAP_LAST; + } + else + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; + } + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + + //////////////////// + case READ_HEAP_LAST: + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + + if (m_heap.is_full()) + { + last_entry.next = r_read_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = r_read_next_ptr.read(); + } + m_heap.write(r_read_ptr.read(),last_entry); + r_read_fsm = READ_RSP; + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ////////////// + case READ_RSP: // request the TGT_RSP FSM to return data + { + if (!r_read_to_tgt_rsp_req) + { + for(size_t i=0 ; i Request TGT_RSP FSM to return data:" + << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; +#endif + } + break; + } + /////////////////// + case READ_TRT_LOCK: // read miss : check the Transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) + { + size_t index = 0; + addr_t addr = (addr_t) m_cmd_read_addr_fifo.read(); + bool hit_read = m_trt.hit_read(m_nline[addr], index); + bool hit_write = m_trt.hit_write(m_nline[addr]); + bool wok = not m_trt.full(index); + + if (hit_read or !wok or hit_write) // line already requested or no space + { + if (!wok) m_cpt_trt_full++; + if (hit_read or hit_write) m_cpt_trt_rb++; + r_read_fsm = READ_IDLE; + } + else // missing line is requested to the XRAM + { + m_cpt_read_miss++; + r_read_trt_index = index; + r_read_fsm = READ_TRT_SET; + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Check TRT:" + << " hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / full = " << !wok << std::endl; +#endif + } + break; + } + ////////////////// + case READ_TRT_SET: // register get transaction in TRT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) + { + m_trt.set( r_read_trt_index.read(), + true, // GET + m_nline[(addr_t)(m_cmd_read_addr_fifo.read())], + m_cmd_read_srcid_fifo.read(), + m_cmd_read_trdid_fifo.read(), + m_cmd_read_pktid_fifo.read(), + true, // proc read + m_cmd_read_length_fifo.read(), + m_x[(addr_t)(m_cmd_read_addr_fifo.read())], + std::vector (m_words,0), + std::vector (m_words,0), + r_read_ll_key.read()); +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Set a GET in TRT:" + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; +#endif + r_read_fsm = READ_TRT_REQ; + } + break; + } + + ////////////////// + case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM + { + if (not r_read_to_ixr_cmd_req) + { + cmd_read_fifo_get = true; + r_read_to_ixr_cmd_req = true; + r_read_to_ixr_cmd_index = r_read_trt_index.read(); + r_read_fsm = READ_IDLE; + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Request GET transaction for address " + << std::hex << m_cmd_read_addr_fifo.read() << std::endl; +#endif + } + break; + } + } // end switch read_fsm + + /////////////////////////////////////////////////////////////////////////////////// + // WRITE FSM + /////////////////////////////////////////////////////////////////////////////////// + // The WRITE FSM handles the write bursts and sc requests sent by the processors. + // All addresses in a burst must be in the same cache line. + // A complete write burst is consumed in the FIFO & copied to a local buffer. + // Then the FSM takes the lock protecting the cache directory, to check + // if the line is in the cache. + // + // - In case of HIT, the cache is updated. + // If there is no other copy, an acknowledge response is immediately + // returned to the writing processor. + // If the data is cached by other processors, a coherence transaction must + // be launched (sc requests always require a coherence transaction): + // It is a multicast update if the line is not in counter mode: the processor + // takes the lock protecting the Update Table (UPT) to register this transaction. + // If the UPT is full, it releases the lock(s) and retry. Then, it sends + // a multi-update request to all owners of the line (but the writer), + // through the CC_SEND FSM. In case of coherence transaction, the WRITE FSM + // does not respond to the writing processor, as this response will be sent by + // the MULTI_ACK FSM when all update responses have been received. + // It is a broadcast invalidate if the line is in counter mode: The line + // should be erased in memory cache, and written in XRAM with a PUT transaction, + // after registration in TRT. + // + // - In case of MISS, the WRITE FSM takes the lock protecting the transaction + // table (TRT). If a read transaction to the XRAM for this line already exists, + // it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, + // the WRITE FSM register a new transaction in TRT, and sends a GET request + // to the XRAM. If the TRT is full, it releases the lock, and waits. + // Finally, the WRITE FSM returns an aknowledge response to the writing processor. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "write_fsm" << std::endl; + + switch(r_write_fsm.read()) + { + //////////////// + case WRITE_IDLE: // copy first word of a write burst in local buffer + { + if (not m_cmd_write_addr_fifo.rok()) break; + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 0; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // if SC command, get the SC key + if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) + { + assert( not m_cmd_write_eop_fifo.read() && + "MEMC ERROR in WRITE_IDLE state: " + "invalid packet format for SC command"); + + r_write_sc_key = m_cmd_write_data_fifo.read(); + } + + // initialize the be field for all words + for(size_t word=0 ; word Write request " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; +#endif + break; + } + //////////////// + case WRITE_NEXT: // copy next word of a write burst in local buffer + { + if (not m_cmd_write_addr_fifo.rok()) break; + + // check that the next word is in the same cache line + assert((m_nline[(addr_t)(r_write_address.read())] == + m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) && + "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); + + size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; + bool is_sc = ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC); + + // check that SC command has constant address + assert((not is_sc or (index == r_write_word_index)) && + "MEMC ERROR in WRITE_NEXT state: " + "the address must be constant on a SC command"); + + // check that SC command has two flits + assert((not is_sc or m_cmd_write_eop_fifo.read()) && + "MEMC ERROR in WRITE_NEXT state: " + "invalid packet format for SC command"); + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + + r_write_be[index] = m_cmd_write_be_fifo.read(); + r_write_data[index] = m_cmd_write_data_fifo.read(); + + // the first flit of a SC command is the reservation key and + // therefore it must not be counted as a data to write + if (not is_sc) + { + r_write_word_count = r_write_word_count.read() + 1; + } + + if (m_cmd_write_eop_fifo.read()) r_write_fsm = WRITE_DIR_REQ; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Write another word in local buffer" + << std::endl; +#endif + break; + } + /////////////////// + case WRITE_DIR_REQ: // Get the lock to the directory + // and access the llsc_global_table + { + if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) break; + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + // test address and key match of the SC command on the + // LL/SC table without removing reservation. The reservation + // will be erased after in this FSM. + bool sc_success = m_llsc_table.check(r_write_address.read(), + r_write_sc_key.read()); + + r_write_sc_fail = not sc_success; + + if (not sc_success) r_write_fsm = WRITE_RSP; + else r_write_fsm = WRITE_DIR_LOCK; + } + else + { + // write burst +#define L2 soclib::common::uint32_log2 + addr_t min = r_write_address.read(); + addr_t max = r_write_address.read() + + (r_write_word_count.read() << L2(vci_param_int::B)); +#undef L2 + + m_llsc_table.sw(min, max); + + r_write_fsm = WRITE_DIR_LOCK; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Requesting DIR lock " + << std::endl; +#endif + break; + } + //////////////////// + case WRITE_DIR_LOCK: // access directory to check hit/miss + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); + + if (entry.valid) // hit + { + // copy directory entry in local buffer in case of hit + r_write_is_cnt = entry.is_cnt; + r_write_lock = entry.lock; + r_write_tag = entry.tag; + r_write_copy = entry.owner.srcid; + r_write_copy_inst = entry.owner.inst; + r_write_count = entry.count; + r_write_ptr = entry.ptr; + r_write_way = way; + + if (entry.is_cnt and entry.count) r_write_fsm = WRITE_BC_DIR_READ; + else r_write_fsm = WRITE_DIR_HIT; + } + else // miss + { + r_write_fsm = WRITE_MISS_TRT_LOCK; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Check the directory: " + << " address = " << std::hex << r_write_address.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt ; + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + std::cout << " / SC access" << std::endl; + else + std::cout << " / SW access" << std::endl; + } +#endif + break; + } + /////////////////// + case WRITE_DIR_HIT: // update the cache directory with Dirty bit + // and update data cache + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation"); + + DirectoryEntry entry; + entry.valid = true; + entry.dirty = true; + entry.tag = r_write_tag.read(); + entry.is_cnt = r_write_is_cnt.read(); + entry.lock = r_write_lock.read(); + entry.owner.srcid = r_write_copy.read(); + entry.owner.inst = r_write_copy_inst.read(); + entry.count = r_write_count.read(); + entry.ptr = r_write_ptr.read(); + + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + // update directory + m_cache_directory.write(set, way, entry); + + // owner is true when the the first registered copy is the writer itself + bool owner = ( (r_write_copy.read() == r_write_srcid.read()) + and not r_write_copy_inst.read()); + + // no_update is true when there is no need for coherence transaction + bool no_update = ( (r_write_count.read() == 0) or + (owner and (r_write_count.read() == 1) and + ((r_write_pktid.read() & 0x7) != TYPE_SC))); + + // write data in the cache if no coherence transaction + if (no_update) + { + // SC command but zero copies + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + for(size_t word=0 ; word Write into cache / No coherence transaction" << std::endl; + } + else + { + std::cout << " Coherence update required:" + << " is_cnt = " << r_write_is_cnt.read() + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; + if (owner) std::cout << " ... but the first copy is the writer" << std::endl; + } + } +#endif + break; + } + //////////////////// + case WRITE_UPT_LOCK: // Try to register the update request in UPT + { + if (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + wok = m_upt.set( true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + + if (wok ) // write data in cache + { + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + for(size_t word=0 ; word Register the multicast update in UPT / " + << " nb_copies = " << r_write_count.read() << std::endl; + } +#endif + r_write_upt_index = index; + // releases the lock protecting UPT and the DIR if no entry... + if (wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; + else r_write_fsm = WRITE_WAIT; + } + break; + } + + ///////////////////////// + case WRITE_UPT_HEAP_LOCK: // get access to heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) + { + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Get acces to the HEAP" << std::endl; +#endif + r_write_fsm = WRITE_UPT_REQ; + } + break; + } + + ////////////////// + case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM + // and write the first copy in the FIFO + // send the request if only one copy + { + assert(not r_write_to_cc_send_multi_req.read() and + not r_write_to_cc_send_brdcast_req.read() and + "Error in VCI_MEM_CACHE : pending multicast or broadcast\n" + "transaction in WRITE_UPT_REQ state" + ); + + r_write_to_cc_send_brdcast_req = false; + r_write_to_cc_send_trdid = r_write_upt_index.read(); + r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; + r_write_to_cc_send_index = r_write_word_index.read(); + r_write_to_cc_send_count = r_write_word_count.read(); + + for(size_t i=0; i Post first request to CC_SEND FSM" + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + + if (r_write_count.read() == 1) + std::cout << " ... and this is the last" << std::endl; + } +#endif + break; + } + + /////////////////// + case WRITE_UPT_NEXT: + { + // continue the multi-update request to CC_SEND fsm + // when there is copies in the heap. + // if one copy in the heap is the writer itself + // the corresponding SRCID should not be written in the fifo, + // but the UPT counter must be decremented. + // As this decrement is done in the WRITE_UPT_DEC state, + // after the last copy has been found, the decrement request + // must be registered in the r_write_to_dec flip-flop. + + HeapEntry entry = m_heap.read(r_write_ptr.read()); + + bool dec_upt_counter; + + // put the next srcid in the fifo + if ((entry.owner.srcid != r_write_srcid.read()) or + ((r_write_pktid.read() & 0x7) == TYPE_SC) or + entry.owner.inst) + { + dec_upt_counter = false; + write_to_cc_send_fifo_put = true; + write_to_cc_send_fifo_inst = entry.owner.inst; + write_to_cc_send_fifo_srcid = entry.owner.srcid; + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Post another request to CC_SEND FSM" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if (entry.next == r_write_ptr.read()) + std::cout << " ... and this is the last" << std::endl; + } +#endif + } + else // the UPT counter must be decremented + { + dec_upt_counter = true; + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Skip one entry in heap matching the writer" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if (entry.next == r_write_ptr.read()) + std::cout << " ... and this is the last" << std::endl; + } +#endif + } + + // register the possible UPT decrement request + r_write_to_dec = dec_upt_counter or r_write_to_dec.read(); + + if (not m_write_to_cc_send_inst_fifo.wok()) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl + << "The write_to_cc_send_fifo should not be full" << std::endl + << "as the depth should be larger than the max number of copies" << std::endl; + exit(0); + } + + r_write_ptr = entry.next; + + if (entry.next == r_write_ptr.read()) // last copy + { + r_write_to_cc_send_multi_req = true; + if (r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; + else r_write_fsm = WRITE_IDLE; + } + break; + } + + ////////////////// + case WRITE_UPT_DEC: + { + // If the initial writer has a copy, it should not + // receive an update request, but the counter in the + // update table must be decremented by the MULTI_ACK FSM. + + if (!r_write_to_multi_ack_req.read()) + { + r_write_to_multi_ack_req = true; + r_write_to_multi_ack_upt_index = r_write_upt_index.read(); + r_write_fsm = WRITE_IDLE; + } + break; + } + + /////////////// + case WRITE_RSP: // Post a request to TGT_RSP FSM to acknowledge the write + // In order to increase the Write requests throughput, + // we don't wait to return in the IDLE state to consume + // a new request in the write FIFO + { + if (not r_write_to_tgt_rsp_req.read()) + { + // post the request to TGT_RSP_FSM + r_write_to_tgt_rsp_req = true; + r_write_to_tgt_rsp_srcid = r_write_srcid.read(); + r_write_to_tgt_rsp_trdid = r_write_trdid.read(); + r_write_to_tgt_rsp_pktid = r_write_pktid.read(); + r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read(); + + // try to get a new write request from the FIFO + if (not m_cmd_write_addr_fifo.rok()) + { + r_write_fsm = WRITE_IDLE; + } + else + { + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(addr_t) (m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t) (m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 0; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // if SC command, get the SC key + if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) + { + assert( not m_cmd_write_eop_fifo.read() && + "MEMC ERROR in WRITE_RSP state: " + "invalid packet format for SC command"); + + r_write_sc_key = m_cmd_write_data_fifo.read(); + } + + // initialize the be field for all words + for(size_t word=0 ; word Post a request to TGT_RSP FSM" + << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl; + if (m_cmd_write_addr_fifo.rok()) + { + std::cout << " New Write request: " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; + } + } +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Check the TRT" << std::endl; +#endif + size_t hit_index = 0; + size_t wok_index = 0; + addr_t addr = (addr_t) r_write_address.read(); + bool hit_read = m_trt.hit_read(m_nline[addr], hit_index); + bool hit_write = m_trt.hit_write(m_nline[addr]); + bool wok = not m_trt.full(wok_index); + + // wait an empty entry in TRT + if(not hit_read and (not wok or hit_write)) + { + r_write_fsm = WRITE_WAIT; + m_cpt_trt_full++; + + break; + } + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + // register the modified data in TRT + if (hit_read) + { + r_write_trt_index = hit_index; + r_write_fsm = WRITE_MISS_TRT_DATA; + m_cpt_write_miss++; + break; + } + + // set a new entry in TRT + if (wok and not hit_write) + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_MISS_TRT_SET; + m_cpt_write_miss++; + break; + } + + assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); + } + break; + } + + //////////////// + case WRITE_WAIT: // release the locks protecting the shared ressources + { + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Releases the locks before retry" << std::endl; +#endif + r_write_fsm = WRITE_DIR_REQ; + break; + } + + //////////////////////// + case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for(size_t i=0; i Set a new entry in TRT" << std::endl; +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for(size_t i=0; i Modify an existing entry in TRT" << std::endl; +#endif + } + break; + } + ///////////////////////// + case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM + { + if (not r_write_to_ixr_cmd_req.read()) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_index = r_write_trt_index.read(); + r_write_fsm = WRITE_RSP; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Post a GET request to the" + << " IXR_CMD FSM" << std::endl; +#endif + } + break; + } + /////////////////////// + case WRITE_BC_DIR_READ: // enter this state if a broadcast-inval is required + // the cache line must be erased in mem-cache, and written + // into XRAM. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation"); + + m_cpt_write_broadcast++; + + // write enable signal for data buffer. + r_write_bc_data_we = true; + + r_write_fsm = WRITE_BC_TRT_LOCK; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " " + << " Read the cache to complete local buffer" << std::endl; +#endif + break; + } + /////////////////////// + case WRITE_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation"); + + // We read the cache and complete the buffer. As the DATA cache uses a + // synchronous RAM, the read DATA request has been performed in the + // WRITE_BC_DIR_READ state but the data is available in this state. + if (r_write_bc_data_we.read()) + { + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + for(size_t word=0 ; word Complete data buffer" << std::endl; +#endif + } + + if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) + { + // if we loop in this state, the data does not need to be + // rewritten (for energy consuption) + r_write_bc_data_we = false; + break; + } + + size_t wok_index = 0; + bool wok = not m_trt.full(wok_index); + if (wok ) + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_BC_IVT_LOCK; + } + else // wait an empty slot in TRT + { + r_write_fsm = WRITE_WAIT; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Check TRT : wok = " << wok + << " / index = " << wok_index << std::endl; +#endif + break; + } + ////////////////////// + case WRITE_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); +#if DEBUG_MEMC_WRITE + if (m_debug and wok ) + std::cout << " Register broadcast inval in IVT" + << " / nb_copies = " << r_write_count.read() << std::endl; +#endif + r_write_upt_index = index; + + if (wok ) r_write_fsm = WRITE_BC_DIR_INVAL; + else r_write_fsm = WRITE_WAIT; + } + break; + } + //////////////////////// + case WRITE_BC_DIR_INVAL: // Register a put transaction in TRT + // and invalidate the line in directory + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation"); + + // register PUT request in TRT + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i (m_words,0), + data_vector ); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + entry.count = 0; + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + m_cache_directory.write(set, way, entry); + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Inval DIR and register in TRT:" + << " address = " << r_write_address.read() << std::endl; +#endif + r_write_fsm = WRITE_BC_CC_SEND; + break; + } + + ////////////////////// + case WRITE_BC_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM + { + if (!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) + { + r_write_to_cc_send_multi_req = false; + r_write_to_cc_send_brdcast_req = true; + r_write_to_cc_send_trdid = r_write_upt_index.read(); + r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; + r_write_to_cc_send_index = 0; + r_write_to_cc_send_count = 0; + + for(size_t i=0; i Post a broadcast request to CC_SEND FSM" << std::endl; +#endif + } + break; + } + + /////////////////////// + case WRITE_BC_XRAM_REQ: // Post a PUT request to IXR_CMD FSM + { + if (not r_write_to_ixr_cmd_req.read()) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_index = r_write_trt_index.read(); + r_write_fsm = WRITE_IDLE; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Post a put request to IXR_CMD FSM" << std::endl; +#endif + } + break; + } + } // end switch r_write_fsm + + /////////////////////////////////////////////////////////////////////// + // IXR_CMD FSM + /////////////////////////////////////////////////////////////////////// + // The IXR_CMD fsm controls the command packets to the XRAM : + // It handles requests from 5 FSMs with a round-robin priority: + // READ > WRITE > CAS > XRAM_RSP > CONFIG + // + // - It sends a single flit VCI read to the XRAM in case of + // GET request posted by the READ, WRITE or CAS FSMs. + // - It sends a multi-flit VCI write in case of PUT request posted by + // the XRAM_RSP, WRITE, CAS, or CONFIG FSMs. + // + // For each client, there is three steps: + // - IXR_CMD_*_IDLE : round-robin allocation to a client + // - IXR_CMD_*_TRT : access to TRT for address and data + // - IXR_CMD_*_SEND : send the PUT or GET VCI command + // + // The address and data to be written (for a PUT) are stored in TRT. + // The trdid field contains always the TRT entry index. + //////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "ixr_cmd_fsm" << std::endl; + + switch(r_ixr_cmd_fsm.read()) + { + /////////////////////// + case IXR_CMD_READ_IDLE: + { + if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + break; + } + //////////////////////// + case IXR_CMD_WRITE_IDLE: + { + if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + break; + } + ////////////////////// + case IXR_CMD_CAS_IDLE: + { + if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + break; + } + /////////////////////// + case IXR_CMD_XRAM_IDLE: + { + if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + break; + } + ///////////////////////// + case IXR_CMD_CONFIG_IDLE: + { + if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + break; + } + + ////////////////////// + case IXR_CMD_READ_TRT: // access TRT for a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_read_to_ixr_cmd_index.read(); + r_ixr_cmd_get = true; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_READ_SEND; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " TRT access" + << " index = " << std::dec << r_read_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + /////////////////////// + case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_write_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_WRITE_SEND; + + // Read data from TRT if PUT transaction + if (not entry.xram_read) + { + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_write_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ///////////////////// + case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_cas_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CAS_SEND; + + // Read data from TRT if PUT transaction + if (not entry.xram_read) + { + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_CMD_XRAM_TRT: // access TRT for a PUT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_xram_rsp_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + //////////////////////// + case IXR_CMD_CONFIG_TRT: // access TRT for a PUT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_config_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CONFIG_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_config_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + + /////////////////////// + case IXR_CMD_READ_SEND: // send a get from READ FSM + { + if (p_vci_ixr.cmdack) + { + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + r_read_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + //////////////////////// + case IXR_CMD_WRITE_SEND: // send a put or get from WRITE FSM + { + if (p_vci_ixr.cmdack) + { + if (not r_ixr_cmd_get.read()) // PUT + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + ////////////////////// + case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM + { + if (p_vci_ixr.cmdack) + { + if (not r_ixr_cmd_get.read()) // PUT + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + /////////////////////// + case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM + { + if (p_vci_ixr.cmdack.read()) + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; + r_xram_rsp_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + ///////////////////////// + case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM + { + if (p_vci_ixr.cmdack.read()) + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; + r_config_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + } // end switch r_ixr_cmd_fsm + + //////////////////////////////////////////////////////////////////////////// + // IXR_RSP FSM + //////////////////////////////////////////////////////////////////////////// + // The IXR_RSP FSM receives the response packets from the XRAM, + // for both PUT transaction, and GET transaction. + // + // - A response to a PUT request is a single-cell VCI packet. + // The TRT index is contained in the RTRDID field. + // The FSM takes the lock protecting the TRT, and the corresponding + // entry is erased. If an acknowledge was required (in case of software SYNC) + // the r_config_rsp_lines counter is decremented. + // + // - A response to a GET request is a multi-cell VCI packet. + // The TRT index is contained in the RTRDID field. + // The N cells contain the N words of the cache line in the RDATA field. + // The FSM takes the lock protecting the TRT to store the line in the TRT + // (taking into account the write requests already stored in the TRT). + // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] + // signal is set to inform the XRAM_RSP FSM. + /////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "ixr_rsp_fsm" << std::endl; + + switch(r_ixr_rsp_fsm.read()) + { + ////////////////// + case IXR_RSP_IDLE: // test transaction type: PUT/GET + { + if (p_vci_ixr.rspval.read()) + { + r_ixr_rsp_cpt = 0; + r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); + + if (p_vci_ixr.reop.read() and not + p_vci_ixr.rerror.read()) // PUT + { + r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Response from XRAM to a put transaction" << std::endl; +#endif + } + else // GET + { + r_ixr_rsp_fsm = IXR_RSP_TRT_READ; + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Response from XRAM to a get transaction" << std::endl; +#endif + } + } + break; + } + //////////////////////// + case IXR_RSP_TRT_ERASE: // erase the entry in the TRT + // decrease the line counter if config request + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) + { + size_t index = r_ixr_rsp_trt_index.read(); + + if (m_trt.is_config(index)) // it's a config transaction + { + config_rsp_lines_ixr_rsp_decr = true; + } + + m_trt.erase(index); + r_ixr_rsp_fsm = IXR_RSP_IDLE; + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Erase TRT entry " + << r_ixr_rsp_trt_index.read() << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT + { + if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) + { + size_t index = r_ixr_rsp_trt_index.read(); + size_t word = r_ixr_rsp_cpt.read(); + bool eop = p_vci_ixr.reop.read(); + wide_data_t data = p_vci_ixr.rdata.read(); + bool rerror = ((p_vci_ixr.rerror.read() & 0x1) == 1); + + assert(((eop == (word == (m_words-2))) or rerror) and + "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); + + m_trt.write_rsp( index, word, data, rerror ); + + r_ixr_rsp_cpt = word + 2; + + if (eop ) + { + r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()] = true; + r_ixr_rsp_fsm = IXR_RSP_IDLE; + } + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Writing 2 words in TRT : " + << " index = " << std::dec << index + << " / word = " << word + << " / data = " << std::hex << data << std::endl; +#endif + } + break; + } + } // end swich r_ixr_rsp_fsm + + //////////////////////////////////////////////////////////////////////////// + // XRAM_RSP FSM + //////////////////////////////////////////////////////////////////////////// + // The XRAM_RSP FSM handles the incoming cache lines after an XRAM GET. + // The cache line has been written in the TRT by the IXR_CMD_FSM. + // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel, + // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number + // of entries in the TRT, that are handled with a round-robin priority... + // + // The FSM takes the lock protecting TRT, and the lock protecting DIR. + // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf. + // It selects a cache slot and save the victim line in another local buffer + // r_xram_rsp_victim_***. + // It writes the line extracted from TRT in the cache. + // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP + // FSM to return the cache line to the registered processor. + // If there is no empty slot, a victim line is evicted, and + // invalidate requests are sent to the L1 caches containing copies. + // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD + // FSM to save the victim line to the XRAM, and register the write transaction + // in the TRT (using the entry previously used by the read transaction). + /////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "xram_rsp_fsm" << std::endl; + + switch(r_xram_rsp_fsm.read()) + { + /////////////////// + case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) + { + size_t old = r_xram_rsp_trt_index.read(); + size_t lines = m_trt_lines; + for(size_t i=0 ; i" + << " Available cache line in TRT:" + << " index = " << std::dec << index << std::endl; +#endif + break; + } + } + break; + } + /////////////////////// + case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock + // Copy the TRT entry in a local buffer + { + if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) + { + // copy the TRT entry in the r_xram_rsp_trt_buf local buffer + size_t index = r_xram_rsp_trt_index.read(); + r_xram_rsp_trt_buf.copy( m_trt.read(index)); + r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get access to DIR and TRT" << std::endl; +#endif + } + break; + } + /////////////////////// + case XRAM_RSP_TRT_COPY: // Select a victim cache line + // and copy it in a local buffer + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation"); + + // selects & extracts a victim line from cache + size_t way = 0; + size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)]; + + DirectoryEntry victim(m_cache_directory.select(set, way)); + + bool inval = (victim.count and victim.valid) ; + + // copy the victim line in a local buffer (both data dir) + m_cache_data.read_line(way, set, r_xram_rsp_victim_data); + + r_xram_rsp_victim_copy = victim.owner.srcid; + r_xram_rsp_victim_copy_inst = victim.owner.inst; + r_xram_rsp_victim_count = victim.count; + r_xram_rsp_victim_ptr = victim.ptr; + r_xram_rsp_victim_way = way; + r_xram_rsp_victim_set = set; + r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; + r_xram_rsp_victim_is_cnt = victim.is_cnt; + r_xram_rsp_victim_inval = inval ; + r_xram_rsp_victim_dirty = victim.dirty; + + if (not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; + else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Select a victim slot: " + << " way = " << std::dec << way + << " / set = " << set + << " / inval_required = " << inval << std::endl; +#endif + break; + } + /////////////////////// + case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock + // to check a possible pending inval + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); + + if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) + { + size_t index = 0; + if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get acces to IVT, but line invalidation registered" + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 + << " / index = " << std::dec << index << std::endl; +#endif + + } + else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get acces to IVT, but inval required and IVT full" << std::endl; +#endif + } + else + { + r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get acces to IVT / no pending inval request" << std::endl; +#endif + } + } + break; + } + ///////////////////////// + case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry + { + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Release all locks and retry" << std::endl; +#endif + r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; + break; + } + /////////////////////// + case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory), + // erases the TRT entry if victim not dirty, + // and set inval request in IVT if required + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation"); + + // check if this is an instruction read, this means pktid is either + // TYPE_READ_INS_UNC 0bX010 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; + + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; + + bool dirty = false; + + // update cache data + size_t set = r_xram_rsp_victim_set.read(); + size_t way = r_xram_rsp_victim_way.read(); + + for(size_t word=0; word" + << " Cache update: " + << " way = " << std::dec << way + << " / set = " << set + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + if (r_xram_rsp_victim_inval.read()) + std::cout << " Invalidation request for address " + << std::hex << r_xram_rsp_victim_nline.read()*m_words*4 + << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl; + } +#endif + + // If the victim is not dirty, we don't need to reuse the TRT entry for + // another PUT transaction, and we can erase the TRT entry + if (not r_xram_rsp_victim_dirty.read()) + { + m_trt.erase(r_xram_rsp_trt_index.read()); + } + + // Next state + if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; + else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + break; + } + //////////////////////// + case XRAM_RSP_TRT_DIRTY: // set the TRT entry (PUT to XRAM) if the victim is dirty + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) + { + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i(m_words,0xF), + data_vector); + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Set TRT entry for the put transaction" + << " / address = " << (r_xram_rsp_victim_nline.read()*m_words*4) << std::endl; +#endif + if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + } + break; + } + ////////////////////// + case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM + { + if (not r_xram_rsp_to_tgt_rsp_req.read()) + { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for(size_t i=0; i < m_words; i++) + { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key; + r_xram_rsp_to_tgt_rsp_rerror = false; + r_xram_rsp_to_tgt_rsp_req = true; + + if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Request the TGT_RSP FSM to return data:" + << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 + << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; +#endif + } + break; + } + //////////////////// + case XRAM_RSP_INVAL: // send invalidate request to CC_SEND FSM + { + if (!r_xram_rsp_to_cc_send_multi_req.read() and + !r_xram_rsp_to_cc_send_brdcast_req.read()) + { + bool multi_req = !r_xram_rsp_victim_is_cnt.read(); + bool last_multi_req = multi_req and (r_xram_rsp_victim_count.read() == 1); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); + + r_xram_rsp_to_cc_send_multi_req = last_multi_req; + r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); + r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); + r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; + xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); + xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); + xram_rsp_to_cc_send_fifo_put = multi_req; + r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); + + if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Send an inval request to CC_SEND FSM" + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; +#endif + } + break; + } + ////////////////////////// + case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM + { + if (not r_xram_rsp_to_ixr_cmd_req.read()) + { + r_xram_rsp_to_ixr_cmd_req = true; + r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read(); + + m_cpt_write_dirty++; + + bool multi_req = not r_xram_rsp_victim_is_cnt.read() and + r_xram_rsp_victim_inval.read(); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); + + if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Send the put request to IXR_CMD FSM" + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; +#endif + } + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_REQ: // Get the lock to the HEAP + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Requesting HEAP lock" << std::endl; +#endif + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) + { + HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read()); + + xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid; + xram_rsp_to_cc_send_fifo_inst = entry.owner.inst; + xram_rsp_to_cc_send_fifo_put = true; + if (m_xram_rsp_to_cc_send_inst_fifo.wok()) + { + r_xram_rsp_next_ptr = entry.next; + if (entry.next == r_xram_rsp_next_ptr.read()) // last copy + { + r_xram_rsp_to_cc_send_multi_req = true; + r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST; + } + else + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + } + else + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Erase copy:" + << " srcid = " << std::hex << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; +#endif + } + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_LAST: // last copy + { + if (r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST" + << " bad HEAP allocation" << std::endl; + exit(0); + } + size_t free_pointer = m_heap.next_free_ptr(); + + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + if (m_heap.is_full()) + { + last_entry.next = r_xram_rsp_next_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = free_pointer; + } + + m_heap.write_free_ptr(r_xram_rsp_victim_ptr.read()); + m_heap.write(r_xram_rsp_next_ptr.read(),last_entry); + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Heap housekeeping" << std::endl; +#endif + break; + } + ////////////////////////// + case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error + { + m_trt.erase(r_xram_rsp_trt_index.read()); + + // Next state + if (r_xram_rsp_trt_buf.proc_read) + { + r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; + } + else + { + // Trigger an interruption to signal a bus error from + // the XRAM because a processor WRITE MISS (XRAM GET + // transaction and not processor read). + // + // To avoid deadlocks we do not wait an error to be + // acknowledged before signaling another one. + // Therefore, when there is an active error, and other + // errors arrive, these are not considered + + if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read() + && r_xram_rsp_trt_buf.xram_read ) + { + r_xram_rsp_rerror_irq = true; + r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4; + r_xram_rsp_rerror_rsrcid = r_xram_rsp_trt_buf.srcid; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout + << " " + << " Triggering interrupt to signal WRITE MISS bus error" + << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read() + << " / nline = " << r_xram_rsp_trt_buf.nline + << " / rsrcid = " << r_xram_rsp_trt_buf.srcid + << std::endl; +#endif + } + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Error reported by XRAM / erase the TRT entry" << std::endl; +#endif + break; + } + //////////////////////// + case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM + { + if (!r_xram_rsp_to_tgt_rsp_req.read()) + { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for(size_t i=0; i < m_words; i++) + { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_rerror = true; + r_xram_rsp_to_tgt_rsp_req = true; + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " Request a response error to TGT_RSP FSM:" + << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; +#endif + } + break; + } + } // end swich r_xram_rsp_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // CLEANUP FSM + //////////////////////////////////////////////////////////////////////////////////// + // The CLEANUP FSM handles the cleanup request from L1 caches. + // It accesses the cache directory and the heap to update the list of copies. + //////////////////////////////////////////////////////////////////////////////////// + + switch(r_cleanup_fsm.read()) + { + ////////////////// + case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command + { + if (not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + uint32_t srcid = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_SRCID); + + uint8_t type = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::P2M_TYPE); + + r_cleanup_way_index = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_WAY_INDEX); + + r_cleanup_nline = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_NLINE_MSB) << 32; + + r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); + r_cleanup_srcid = srcid; + + assert((srcid < m_initiators) and + "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value"); + + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_fsm = CLEANUP_GET_NLINE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Cleanup request:" << std::hex + << " owner_id = " << srcid + << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_GET_NLINE: // GET second DSPIN flit of the cleanup command + { + if (not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + addr_t nline = r_cleanup_nline.read() | + DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); + + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_nline = nline; + r_cleanup_fsm = CLEANUP_DIR_REQ; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Cleanup request:" + << " address = " << std::hex << nline * m_words * 4 << std::endl; +#endif + break; + } + ///////////////////// + case CLEANUP_DIR_REQ: // Get the lock to the directory + { + if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_DIR_LOCK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Requesting DIR lock" << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_DIR_LOCK: // test directory status + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + // Read the directory + size_t way = 0; + addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; + DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); + r_cleanup_is_cnt = entry.is_cnt; + r_cleanup_dirty = entry.dirty; + r_cleanup_tag = entry.tag; + r_cleanup_lock = entry.lock; + r_cleanup_way = way; + r_cleanup_count = entry.count; + r_cleanup_ptr = entry.ptr; + r_cleanup_copy = entry.owner.srcid; + r_cleanup_copy_inst = entry.owner.inst; + + if (entry.valid) // hit : the copy must be cleared + { + assert( (entry.count > 0) and + "MEMC ERROR in CLEANUP_DIR_LOCK state, CLEANUP on valid entry with no copies"); + + if ((entry.count == 1) or (entry.is_cnt)) // no access to the heap + { + r_cleanup_fsm = CLEANUP_DIR_WRITE; + } + else // access to the heap + { + r_cleanup_fsm = CLEANUP_HEAP_REQ; + } + } + else // miss : check IVT for a pending inval + { + r_cleanup_fsm = CLEANUP_IVT_LOCK; + } + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Test directory status: " + << std::hex << " address = " << cleanup_address + << " / hit = " << entry.valid + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_DIR_WRITE: // Update the directory entry without heap access + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)]; + bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match = match_srcid and match_inst; + + assert( (r_cleanup_is_cnt.read() or match) and + "MEMC ERROR in CLEANUP_DIR_LOCK: illegal CLEANUP on valid entry"); + + // update the cache directory (for the copies) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cleanup_is_cnt.read(); + entry.dirty = r_cleanup_dirty.read(); + entry.tag = r_cleanup_tag.read(); + entry.lock = r_cleanup_lock.read(); + entry.ptr = r_cleanup_ptr.read(); + entry.count = r_cleanup_count.read() - 1; + entry.owner.srcid = 0; + entry.owner.inst = 0; + + m_cache_directory.write(set, way, entry); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Update directory:" + << std::hex << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + + break; + } + ////////////////////// + case CLEANUP_HEAP_REQ: // get the lock to the HEAP directory + { + if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_HEAP_LOCK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " HEAP lock acquired " << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_HEAP_LOCK: // two cases are handled in this state : + // 1. the matching copy is directly in the directory + // 2. the matching copy is the first copy in the heap + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)]; + + HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); + bool last = (heap_entry.next == r_cleanup_ptr.read()); + + // match_dir computation + bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_dir_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match_dir = match_dir_srcid and match_dir_inst; + + // match_heap computation + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + r_cleanup_prev_ptr = r_cleanup_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + + assert( (not last or match_dir or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found"); + + assert( (not match_dir or not match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found"); + + DirectoryEntry dir_entry; + dir_entry.valid = true; + dir_entry.is_cnt = r_cleanup_is_cnt.read(); + dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.tag = r_cleanup_tag.read(); + dir_entry.lock = r_cleanup_lock.read(); + dir_entry.count = r_cleanup_count.read()-1; + + // the matching copy is registered in the directory and + // it must be replaced by the first copy registered in + // the heap. The corresponding entry must be freed + if (match_dir) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = heap_entry.owner.srcid; + dir_entry.owner.inst = heap_entry.owner.inst; + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // the matching copy is the first copy in the heap + // It must be freed and the copy registered in directory + // must point to the next copy in heap + else if (match_heap) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // The matching copy is in the heap, but is not the first copy + // The directory entry must be modified to decrement count + else + { + dir_entry.ptr = r_cleanup_ptr.read(); + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + + m_cache_directory.write(set,way,dir_entry); + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Checks matching:" + << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << r_cleanup_copy.read() + << " / dir_ins = " << r_cleanup_copy_inst.read() + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() << std::endl; +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy + // is in the heap, but not the first in linked list + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); + + bool last = (heap_entry.next == r_cleanup_next_ptr.read()); + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + assert( (not last or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found"); + + // the matching copy must be removed + if (match_heap) + { + // re-use ressources + r_cleanup_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_CLEAN; + } + // test the next in the linked list + else + { + r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + if (not match_heap) + { + std::cout + << " Matching copy not found, search next:" + << std::endl; + } + else + { + std::cout + << " Matching copy found:" + << std::endl; + } + std::cout + << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() + << " / last = " << last + << std::endl; + } +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); + heap_entry.owner.inst = r_cleanup_prev_inst.read(); + bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); + + if (last) // this is the last entry of the list of copies + { + heap_entry.next = r_cleanup_prev_ptr.read(); + } + else // this is not the last entry + { + heap_entry.next = r_cleanup_ptr.read(); + } + + m_heap.write(r_cleanup_prev_ptr.read(), heap_entry); + + r_cleanup_fsm = CLEANUP_HEAP_FREE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Remove the copy in the linked list" << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed + // and becomes the head of the list of free entries + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = 0; + heap_entry.owner.inst = false; + + if (m_heap.is_full()) + { + heap_entry.next = r_cleanup_next_ptr.read(); + } + else + { + heap_entry.next = m_heap.next_free_ptr(); + } + + m_heap.write(r_cleanup_next_ptr.read(),heap_entry); + m_heap.write_free_ptr(r_cleanup_next_ptr.read()); + m_heap.unset_full(); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Update the list of free entries" << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending + // invalidate transaction matching the cleanup + { + if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; + + size_t index = 0; + bool match_inval; + + match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); + + if (not match_inval ) // no pending inval in IVT + { + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Unexpected cleanup with no corresponding IVT entry:" + << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl; +#endif + } + else // pending inval in IVT + { + r_cleanup_write_srcid = m_ivt.srcid(index); + r_cleanup_write_trdid = m_ivt.trdid(index); + r_cleanup_write_pktid = m_ivt.pktid(index); + r_cleanup_need_rsp = m_ivt.need_rsp(index); + r_cleanup_need_ack = m_ivt.need_ack(index); + r_cleanup_index = index; + r_cleanup_fsm = CLEANUP_IVT_DECREMENT; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Cleanup matching pending invalidate transaction on IVT:" + << " address = " << std::hex << (r_cleanup_nline.read()*m_words*4) + << " / ivt_entry = " << index << std::endl; +#endif + } + break; + } + /////////////////////////// + case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry + // and test if last + { + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation"); + + size_t count = 0; + m_ivt.decrement(r_cleanup_index.read(), count); + + if (count == 0) r_cleanup_fsm = CLEANUP_IVT_CLEAR; + else r_cleanup_fsm = CLEANUP_SEND_CLACK ; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Decrement response counter in IVT:" + << " IVT_index = " << r_cleanup_index.read() + << " / rsp_count = " << count << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_IVT_CLEAR: // Clear IVT entry + // Acknowledge CONFIG FSM if required + { + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation"); + + m_ivt.clear(r_cleanup_index.read()); + + if (r_cleanup_need_ack.read()) + { + assert( (r_config_rsp_lines.read() > 0) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state"); + + config_rsp_lines_cleanup_decr = true; + } + + if (r_cleanup_need_rsp.read()) r_cleanup_fsm = CLEANUP_WRITE_RSP; + else r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Clear entry in IVT:" + << " IVT_index = " << r_cleanup_index.read() << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_WRITE_RSP: // response to a previous write on the direct network + // wait if pending request to the TGT_RSP FSM + { + if (r_cleanup_to_tgt_rsp_req.read()) break; + + // no pending request + r_cleanup_to_tgt_rsp_req = true; + r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); + r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); + r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Send a response to a previous write request: " + << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() + << " / rtrdid = " << r_cleanup_write_trdid.read() + << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; +#endif + break; + } + //////////////////////// + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + // on the coherence CLACK network. + { + if (not p_dspin_clack.read) break; + + r_cleanup_fsm = CLEANUP_IDLE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Send the response to a cleanup request:" + << " address = " << std::hex << r_cleanup_nline.read()*m_words*4 + << " / way = " << std::dec << r_cleanup_way.read() + << " / srcid = " << std::dec << r_cleanup_srcid.read() + << std::endl; +#endif + break; + } + } // end switch cleanup fsm + + //////////////////////////////////////////////////////////////////////////////////// + // CAS FSM + //////////////////////////////////////////////////////////////////////////////////// + // The CAS FSM handles the CAS (Compare And Swap) atomic commands. + // + // This command contains two or four flits: + // - In case of 32 bits atomic access, the first flit contains the value read + // by a previous READ instruction, the second flit contains the value to be writen. + // - In case of 64 bits atomic access, the 2 first flits contains the value read + // by a previous READ instruction, the 2 next flits contains the value to be writen. + // + // The target address is cachable. If it is replicated in other L1 caches + // than the writer, a coherence operation is done. + // + // It access the directory to check hit / miss. + // - In case of miss, the CAS FSM must register a GET transaction in TRT. + // If a read transaction to the XRAM for this line already exists, + // or if the transaction table is full, it goes to the WAIT state + // to release the locks and try again. When the GET transaction has been + // launched, it goes to the WAIT state and try again. + // The CAS request is not consumed in the FIFO until a HIT is obtained. + // - In case of hit... + /////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "cas_fsm" << std::endl; + + switch(r_cas_fsm.read()) + { + //////////// + case CAS_IDLE: // fill the local rdata buffers + { + if (m_cmd_cas_addr_fifo.rok()) + { + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " CAS command: " << std::hex + << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() + << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() + << " wdata = " << m_cmd_cas_wdata_fifo.read() + << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() + << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; +#endif + if (m_cmd_cas_eop_fifo.read()) + { + r_cas_fsm = CAS_DIR_REQ; + } + else // we keep the last word in the FIFO + { + cmd_cas_fifo_get = true; + } + + // We fill the two buffers + if (r_cas_cpt.read() < 2) // 32 bits access + r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); + + if ((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + assert( (r_cas_cpt.read() <= 3) and // no more than 4 flits... + "MEMC ERROR in CAS_IDLE state: illegal CAS command"); + + if (r_cas_cpt.read() ==2) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + r_cas_cpt = r_cas_cpt.read() +1; + } + break; + } + ///////////////// + case CAS_DIR_REQ: + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) + { + r_cas_fsm = CAS_DIR_LOCK; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Requesting DIR lock " << std::endl; +#endif + break; + } + ///////////////// + case CAS_DIR_LOCK: // Read the directory + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way)); + + r_cas_is_cnt = entry.is_cnt; + r_cas_dirty = entry.dirty; + r_cas_tag = entry.tag; + r_cas_way = way; + r_cas_copy = entry.owner.srcid; + r_cas_copy_inst = entry.owner.inst; + r_cas_ptr = entry.ptr; + r_cas_count = entry.count; + + if (entry.valid) r_cas_fsm = CAS_DIR_HIT_READ; + else r_cas_fsm = CAS_MISS_TRT_LOCK; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Directory acces" + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + + break; + } + ///////////////////// + case CAS_DIR_HIT_READ: // update directory for lock and dirty bit + // and check data change in cache + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_READ: Bad DIR allocation"); + + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // update directory (lock & dirty bits) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cas_is_cnt.read(); + entry.dirty = true; + entry.lock = true; + entry.tag = r_cas_tag.read(); + entry.owner.srcid = r_cas_copy.read(); + entry.owner.inst = r_cas_copy_inst.read(); + entry.count = r_cas_count.read(); + entry.ptr = r_cas_ptr.read(); + + m_cache_directory.write(set, way, entry); + + // Store data from cache in buffer to do the comparison in next state + m_cache_data.read_line(way, set, r_cas_data); + + r_cas_fsm = CAS_DIR_HIT_COMPARE; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Read data from " + << " cache and store it in buffer" << std::endl; +#endif + break; + } + //////////////////////// + case CAS_DIR_HIT_COMPARE: + { + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // check data change + bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read()); + + if (r_cas_cpt.read() == 4) // 64 bits CAS + ok &= (r_cas_rdata[1] == r_cas_data[word+1]); + + // to avoid livelock, force the atomic access to fail pseudo-randomly + bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS); + r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); + + if (ok and not forced_fail) r_cas_fsm = CAS_DIR_HIT_WRITE; + else r_cas_fsm = CAS_RSP_FAIL; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Compare old and new data" + << " / expected value = " << std::hex << r_cas_rdata[0].read() + << " / actual value = " << std::hex << r_cas_data[word].read() + << " / forced_fail = " << std::dec << forced_fail << std::endl; +#endif + break; + } + ////////////////////// + case CAS_DIR_HIT_WRITE: // test if a CC transaction is required + // write data in cache if no CC request + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_WRITE: Bad DIR allocation"); + + // The CAS is a success => sw access to the llsc_global_table + m_llsc_table.sw(m_cmd_cas_addr_fifo.read(), m_cmd_cas_addr_fifo.read()); + + // test coherence request + if (r_cas_count.read()) // replicated line + { + if (r_cas_is_cnt.read()) + { + r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " " + << " Broacast Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + } + else if (not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_fsm = CAS_UPT_LOCK; // multi update required + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " " + << " Multi Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + } + else + { + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " " + << " CC_SEND FSM busy: release all locks and retry" << std::endl; +#endif + } + } + else // no copies + { + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // cache update + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if (r_cas_cpt.read() == 4) + m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); + + r_cas_fsm = CAS_RSP_SUCCESS; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Update cache:" + << " way = " << std::dec << way + << " / set = " << set + << " / word = " << word + << " / value = " << r_cas_wdata.read() + << " / count = " << r_cas_count.read() + << " / global_llsc_table access" << std::endl; +#endif + } + break; + } + ///////////////// + case CAS_UPT_LOCK: // try to register the transaction in UPT + // and write data in cache if successful registration + // releases locks to retry later if UPT full + { + if (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) + { + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_upt.set( true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + if (wok) // coherence transaction registered in UPT + { + // cache update + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if (r_cas_cpt.read() ==4) + m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); + + r_cas_upt_index = index; + r_cas_fsm = CAS_UPT_HEAP_LOCK; + } + else // releases the locks protecting UPT and DIR UPT full + { + r_cas_fsm = CAS_WAIT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Register multi-update transaction in UPT" + << " / wok = " << wok + << " / address = " << std::hex << nline*m_words*4 + << " / count = " << nb_copies << std::endl; +#endif + } + break; + } + ///////////// + case CAS_WAIT: // release all locks and retry from beginning + { + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Release all locks" << std::endl; +#endif + r_cas_fsm = CAS_DIR_REQ; + break; + } + ////////////////////// + case CAS_UPT_HEAP_LOCK: // lock the heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) + { + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Get access to the heap" << std::endl; + } +#endif + r_cas_fsm = CAS_UPT_REQ; + } + break; + } + //////////////// + case CAS_UPT_REQ: // send a first update request to CC_SEND FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and + "VCI_MEM_CACHE ERROR : bad HEAP allocation"); + + if (!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_to_cc_send_brdcast_req = false; + r_cas_to_cc_send_trdid = r_cas_upt_index.read(); + r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_index = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_wdata = r_cas_wdata.read(); + + if (r_cas_cpt.read() == 4) + { + r_cas_to_cc_send_is_long = true; + r_cas_to_cc_send_wdata_high = m_cmd_cas_wdata_fifo.read(); + } + else + { + r_cas_to_cc_send_is_long = false; + r_cas_to_cc_send_wdata_high = 0; + } + + // We put the first copy in the fifo + cas_to_cc_send_fifo_put = true; + cas_to_cc_send_fifo_inst = r_cas_copy_inst.read(); + cas_to_cc_send_fifo_srcid = r_cas_copy.read(); + if (r_cas_count.read() == 1) // one single copy + { + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving + // update responses + cmd_cas_fifo_get = true; + r_cas_to_cc_send_multi_req = true; + r_cas_cpt = 0; + } + else // several copies + { + r_cas_fsm = CAS_UPT_NEXT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Send the first update request to CC_SEND FSM " + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / wdata = " << std::hex << r_cas_wdata.read() + << " / srcid = " << std::dec << r_cas_copy.read() + << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl; + } +#endif + } + break; + } + ///////////////// + case CAS_UPT_NEXT: // send a multi-update request to CC_SEND FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) + and "VCI_MEM_CACHE ERROR : bad HEAP allocation"); + + HeapEntry entry = m_heap.read(r_cas_ptr.read()); + cas_to_cc_send_fifo_srcid = entry.owner.srcid; + cas_to_cc_send_fifo_inst = entry.owner.inst; + cas_to_cc_send_fifo_put = true; + + if (m_cas_to_cc_send_inst_fifo.wok()) // request accepted by CC_SEND FSM + { + r_cas_ptr = entry.next; + if (entry.next == r_cas_ptr.read()) // last copy + { + r_cas_to_cc_send_multi_req = true; + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving + // all update responses + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + } + } + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Send the next update request to CC_SEND FSM " + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / wdata = " << std::hex << r_cas_wdata.read() + << " / srcid = " << std::dec << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; + } +#endif + break; + } + ///////////////////// + case CAS_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation"); + + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) + { + size_t wok_index = 0; + bool wok = !m_trt.full(wok_index); + if (wok ) + { + r_cas_trt_index = wok_index; + r_cas_fsm = CAS_BC_IVT_LOCK; + } + else + { + r_cas_fsm = CAS_WAIT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Check TRT" + << " : wok = " << wok << " / index = " << wok_index << std::endl; +#endif + } + break; + } + ///////////////////// + case CAS_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas TRT allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS ) + { + // register broadcast inval transaction in IVT + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_ivt.set( false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); +#if DEBUG_MEMC_CAS + if (m_debug and wok ) + std::cout << " Register broadcast inval in IVT" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + r_cas_upt_index = index; + if (wok ) r_cas_fsm = CAS_BC_DIR_INVAL; + else r_cas_fsm = CAS_WAIT; + } + break; + } + ////////////////////// + case CAS_BC_DIR_INVAL: // Register PUT transaction in TRT, + // and inval the DIR entry + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation"); + + // set TRT + std::vector data_vector; + data_vector.clear(); + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + for(size_t i=0; i (m_words,0), + data_vector ); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.count = 0; + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t way = r_cas_way.read(); + + m_cache_directory.write(set, way, entry); + + r_cas_fsm = CAS_BC_CC_SEND; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Inval DIR & register in TRT:" + << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; +#endif + break; + } + /////////////////// + case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM + { + if (not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_to_cc_send_multi_req = false; + r_cas_to_cc_send_brdcast_req = true; + r_cas_to_cc_send_trdid = r_cas_upt_index.read(); + r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_index = 0; + r_cas_to_cc_send_wdata = 0; + + r_cas_fsm = CAS_BC_XRAM_REQ; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; +#endif + } + break; + } + //////////////////// + case CAS_BC_XRAM_REQ: // request the IXR FSM to start a PUT transaction + { + if (not r_cas_to_ixr_cmd_req.read()) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_IDLE; + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex + << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read() + << " / trt_index = " << r_cas_trt_index.read() << std::endl; +#endif + } + break; + } + ///////////////// + case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response + { + if (not r_cas_to_tgt_rsp_req.read()) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 1; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request TGT_RSP to send a failure response" << std::endl; +#endif + } + break; + } + //////////////////// + case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response + { + if (not r_cas_to_tgt_rsp_req.read()) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 0; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request TGT_RSP to send a success response" << std::endl; +#endif + } + break; + } + /////////////////////// + case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) + { + size_t index = 0; + bool hit_read = m_trt.hit_read( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index); + bool hit_write = m_trt.hit_write( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]); + bool wok = not m_trt.full(index); + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Check TRT state" + << " / hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / wok = " << wok + << " / index = " << index << std::endl; +#endif + + if (hit_read or !wok or hit_write) // missing line already requested or TRT full + { + r_cas_fsm = CAS_WAIT; + } + else + { + r_cas_trt_index = index; + r_cas_fsm = CAS_MISS_TRT_SET; + } + } + break; + } + ////////////////////// + case CAS_MISS_TRT_SET: // register the GET transaction in TRT + { + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation"); + + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for(size_t i=0; i(m_words,0), + std::vector(m_words,0)); + + r_cas_fsm = CAS_MISS_XRAM_REQ; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Register GET transaction in TRT" + << " / address = " << std::hex << (addr_t)m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; +#endif + break; + } + ////////////////////// + case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM a GET request + { + if (not r_cas_to_ixr_cmd_req.read()) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request a GET transaction" + << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; +#endif + } + break; + } + } // end switch r_cas_fsm + + + ////////////////////////////////////////////////////////////////////////////// + // CC_SEND FSM + ////////////////////////////////////////////////////////////////////////////// + // The CC_SEND fsm controls the DSPIN initiator port on the coherence + // network, used to update or invalidate cache lines in L1 caches. + // + // It implements a round-robin priority between the four possible client FSMs + // XRAM_RSP > CAS > WRITE > CONFIG + // + // Each FSM can request the next services: + // - r_xram_rsp_to_cc_send_multi_req : multi-inval + // r_xram_rsp_to_cc_send_brdcast_req : broadcast-inval + // - r_write_to_cc_send_multi_req : multi-update + // r_write_to_cc_send_brdcast_req : broadcast-inval + // - r_cas_to_cc_send_multi_req : multi-update + // r_cas_to_cc_send_brdcast_req : broadcast-inval + // - r_config_to_cc_send_multi_req : multi-inval + // r_config_to_cc_send_brdcast_req : broadcast-inval + // + // An inval request is a double DSPIN flit command containing: + // 1. the index of the line to be invalidated. + // + // An update request is a multi-flit DSPIN command containing: + // 1. the index of the cache line to be updated. + // 2. the index of the first modified word in the line. + // 3. the data to update + /////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "cc_send_fsm" << std::endl; + + switch(r_cc_send_fsm.read()) + { + ///////////////////////// + case CC_SEND_CONFIG_IDLE: // XRAM_RSP FSM has highest priority + { + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + break; + } + //////////////////////// + case CC_SEND_WRITE_IDLE: // CONFIG FSM has highest priority + { + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + break; + } + /////////////////////////// + case CC_SEND_XRAM_RSP_IDLE: // CAS FSM has highest priority + { + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + break; + } + ////////////////////// + case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority + { + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + break; + } + ///////////////////////////////// + case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) + { + if (m_config_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_config_to_cc_send_srcid_fifo.read())) + { + m_cpt_minval_local++; + } + else + { + m_cpt_minval_remote++; + m_cpt_minval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read()); + } + // + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; + break; + } + if (r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; + // + m_cpt_minval++; + // + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + config_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " multi-inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; + break; + } + ////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + r_config_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " BC-Inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) + { + if (m_xram_rsp_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read())) + { + m_cpt_minval_local++; + } + else + { + m_cpt_minval_remote++; + m_cpt_minval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); + } + // + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; + break; + } + if (r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; + // + m_cpt_minval++; + // + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + break; + } + ////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + xram_rsp_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Multicast-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; +#endif + break; + } + ///////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; + break; + } + //////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + r_xram_rsp_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " BC-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; +#endif + break; + } + ////////////////////////////////// + case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; + break; + } + ///////////////////////////////// + case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + + // + m_cpt_binval++; + // + + r_write_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_WRITE_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " BC-Inval for line " + << std::hex << r_write_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////// + case CC_SEND_WRITE_UPDT_HEADER: // send first flit for a multi-update (from WRITE FSM) + { + if (m_write_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_write_to_cc_send_srcid_fifo.read())) + { + m_cpt_update_local++; + } + else + { + m_cpt_update_remote++; + m_cpt_update_cost += req_distance(m_write_to_cc_send_srcid_fifo.read()); + } + // + + r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; + break; + } + + if (r_write_to_cc_send_multi_req.read()) + { + r_write_to_cc_send_multi_req = false; + } + + // + m_cpt_update++; + // + r_cc_send_fsm = CC_SEND_WRITE_IDLE; + break; + } + ////////////////////////////// + case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + + r_cc_send_cpt = 0; + r_cc_send_fsm = CC_SEND_WRITE_UPDT_DATA; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Multicast-Update for address " + << r_write_to_cc_send_nline.read()*m_words*4 << std::endl; +#endif + break; + } + ///////////////////////////// + case CC_SEND_WRITE_UPDT_DATA: // send data flits for multi-update (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + if (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()) + { + write_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + + r_cc_send_cpt = r_cc_send_cpt.read() + 1; + break; + } + //////////////////////////////// + case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; + break; + } + /////////////////////////////// + case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + + r_cas_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_CAS_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Broadcast-Inval for address: " + << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; +#endif + break; + } + ///////////////////////////// + case CC_SEND_CAS_UPDT_HEADER: // send first flit for a multi-update (from CAS FSM) + { + if (m_cas_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_cas_to_cc_send_srcid_fifo.read())) + { + m_cpt_update_local++; + } + else + { + m_cpt_update_remote++; + m_cpt_update_cost += req_distance(m_cas_to_cc_send_srcid_fifo.read()); + } + // + r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; + break; + } + + // no more packets to send for the multi-update + if (r_cas_to_cc_send_multi_req.read()) + { + r_cas_to_cc_send_multi_req = false; + } + + // + m_cpt_update++; + // + r_cc_send_fsm = CC_SEND_CAS_IDLE; + break; + } + //////////////////////////// + case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_cpt = 0; + r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Multicast-Update for address " + << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; +#endif + break; + } + /////////////////////////// + case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + + if (r_cas_to_cc_send_is_long.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH; + break; + } + + cas_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + //////////////////////////////// + case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for multi-update (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + cas_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + } + // end switch r_cc_send_fsm + + ////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE FSM + ////////////////////////////////////////////////////////////////////////////// + // The CC_RECEIVE fsm controls the DSPIN target port on the coherence + // network. + ////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "cc_receive_fsm" << std::endl; + + switch(r_cc_receive_fsm.read()) + { + ///////////////////// + case CC_RECEIVE_IDLE: + { + if (not p_dspin_p2m.write) break; + + uint8_t type = + DspinDhccpParam::dspin_get( + p_dspin_p2m.data.read(), + DspinDhccpParam::P2M_TYPE); + + if ((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or + (type == DspinDhccpParam::TYPE_CLEANUP_INST)) + { + r_cc_receive_fsm = CC_RECEIVE_CLEANUP; + break; + } + + if (type == DspinDhccpParam::TYPE_MULTI_ACK) + { + r_cc_receive_fsm = CC_RECEIVE_MULTI_ACK; + break; + } + + assert(false and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "Illegal type in coherence request"); + + break; + } + //////////////////////// + case CC_RECEIVE_CLEANUP: + { + // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) + break; + + assert(not p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); + + cc_receive_to_cleanup_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_CLEANUP_EOP; + + // + uint32_t srcid = DspinDhccpParam::dspin_get( + p_dspin_p2m.data.read(), + DspinDhccpParam::CLEANUP_SRCID); + + if (is_local_req(srcid)) { + m_cpt_cleanup_local++; + } + else { + m_cpt_cleanup_remote++; + m_cpt_cleanup_cost += req_distance(srcid); + } + // + + break; + } + //////////////////////////// + case CC_RECEIVE_CLEANUP_EOP: + { + // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) + break; + + assert(p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); + + cc_receive_to_cleanup_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + + break; + } + + ////////////////////////// + case CC_RECEIVE_MULTI_ACK: + { + // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo + + // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo + if (not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) + break; + + assert(p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "MULTI_ACK command must have one flit"); + + cc_receive_to_multi_ack_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + } + + ////////////////////////////////////////////////////////////////////////// + // TGT_RSP FSM + ////////////////////////////////////////////////////////////////////////// + // The TGT_RSP fsm sends the responses on the VCI target port + // with a round robin priority between eigth requests : + // - r_config_to_tgt_rsp_req + // - r_tgt_cmd_to_tgt_rsp_req + // - r_read_to_tgt_rsp_req + // - r_write_to_tgt_rsp_req + // - r_cas_to_tgt_rsp_req + // - r_cleanup_to_tgt_rsp_req + // - r_xram_rsp_to_tgt_rsp_req + // - r_multi_ack_to_tgt_rsp_req + // + // The ordering is : + // config >tgt_cmd > read > write > cas > xram > multi_ack > cleanup + ////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "tgt_rsp_fsm" << std::endl; + + switch(r_tgt_rsp_fsm.read()) + { + ///////////////////////// + case TGT_RSP_CONFIG_IDLE: // tgt_cmd requests have the highest priority + { + if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + break; + } + ////////////////////////// + case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority + { + if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + break; + } + /////////////////////// + case TGT_RSP_READ_IDLE: // write requests have the highest priority + { + if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + break; + } + //////////////////////// + case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority + { + if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + break; + } + /////////////////////// + case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority + { + if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + break; + } + /////////////////////// + case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority + { + + if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + break; + } + //////////////////////////// + case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority + { + if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + break; + } + ////////////////////////// + case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority + { + if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + break; + } + //////////////////// + case TGT_RSP_CONFIG: // send the response for a config transaction + { + if (p_vci_tgt.rspack ) + { + r_config_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_CONFIG_IDLE; + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + { + std::cout + << " Config transaction completed response" + << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_config_to_tgt_rsp_pktid.read() + << std::endl; + } +#endif + } + break; + } + ///////////////////// + case TGT_RSP_TGT_CMD: // send the response for a configuration access + { + if (p_vci_tgt.rspack ) + { + r_tgt_cmd_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + { + std::cout + << " Send response for a configuration access" + << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read() + << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read() + << std::endl; + } +#endif + } + break; + } + ////////////////// + case TGT_RSP_READ: // send the response to a read + { + if (p_vci_tgt.rspack ) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + { + std::cout + << " Read response" + << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_read_to_tgt_rsp_pktid.read() + << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; + } +#endif + + uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + + r_read_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + + if ((is_last_word and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)) + { + // Last word in case of READ or second flit in case if LL + r_tgt_rsp_key_sent = false; + r_read_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; + } + else + { + if (is_ll) + { + r_tgt_rsp_key_sent = true; // Send second flit of ll + } + else + { + r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read + } + } + } + break; + } + ////////////////// + case TGT_RSP_WRITE: // send the write acknowledge + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " Write response" + << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE; + r_write_to_tgt_rsp_req = false; + } + break; + } + ///////////////////// + case TGT_RSP_CLEANUP: // pas clair pour moi (AG) + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " Cleanup response" + << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; + r_cleanup_to_tgt_rsp_req = false; + } + break; + } + ///////////////// + case TGT_RSP_CAS: // send one atomic word response + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " CAS response" + << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE; + r_cas_to_tgt_rsp_req = false; + } + break; + } + ////////////////// + case TGT_RSP_XRAM: // send the response after XRAM access + { + if (p_vci_tgt.rspack ) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + std::cout << " Response following XRAM access" + << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() + << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; +#endif + uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + + r_xram_rsp_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); + + if (((is_last_word or is_error) and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)) + { + // Last word sent in case of READ or second flit sent in case if LL + r_tgt_rsp_key_sent = false; + r_xram_rsp_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; + } + else + { + if (is_ll) + { + r_tgt_rsp_key_sent = true; // Send second flit of ll + } + else + { + r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read + } + } + } + break; + } + /////////////////////// + case TGT_RSP_MULTI_ACK: // send the write response after coherence transaction + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " Write response after coherence transaction" + << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE; + r_multi_ack_to_tgt_rsp_req = false; + } + break; + } + } // end switch tgt_rsp_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_UPT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), + // with a round robin priority between three FSMs, with the following order: + // WRITE -> CAS -> MULTI_ACK + // - The WRITE FSM initiates update transaction and sets a new entry in UPT. + // - The CAS FSM does the same thing as the WRITE FSM. + // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. + // The resource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_upt_fsm" << std::endl; + + switch(r_alloc_upt_fsm.read()) + { + ///////////////////////// + case ALLOC_UPT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_UPT_LOCK) + { + if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + + else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + } + break; + + ///////////////////////// + case ALLOC_UPT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_UPT_LOCK) + { + if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + + else if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + } + break; + + ///////////////////////// + case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM + if (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) + { + if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + } + break; + } // end switch r_alloc_upt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_IVT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), + // with a round robin priority between five FSMs, with the following order: + // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG + // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry + // in IVT. + // - The CAS FSM does the same thing as the WRITE FSM. + // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets + // a new entry in the IVT + // - The CONFIG FSM does the same thing as the XRAM_RSP FSM + // - The CLEANUP FSM complete those trasactions and erase the IVT entry. + // The resource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_ivt_fsm" << std::endl; + + switch(r_alloc_ivt_fsm.read()) + { + ///////////////////// + case ALLOC_IVT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + } + break; + + //////////////////////// + case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM + if (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK) + { + if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + } + break; + + /////////////////////// + case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM + if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and + (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) + { + if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) + { + if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM + if (r_config_fsm.read() != CONFIG_IVT_LOCK) + { + if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + } + break; + + } // end switch r_alloc_ivt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_DIR FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_DIR FSM allocates the access to the directory and + // the data cache with a round robin priority between 6 user FSMs : + // The cyclic ordering is CONFIG > READ > WRITE > CAS > CLEANUP > XRAM_RSP + // The ressource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_dir_fsm" << std::endl; + + switch(r_alloc_dir_fsm.read()) + { + ///////////////////// + case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. + // All the WAYS of a SET initialized in parallel + + r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); + + if (r_alloc_dir_reset_cpt.read() == (m_sets - 1)) + { + m_cache_directory.init(); + r_alloc_dir_fsm = ALLOC_DIR_READ; + } + break; + + ////////////////////// + case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM + if ((r_config_fsm.read() != CONFIG_DIR_REQ) and + (r_config_fsm.read() != CONFIG_DIR_ACCESS) and + (r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET) and + (r_config_fsm.read() != CONFIG_IVT_LOCK)) + { + if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + } + break; + + //////////////////// + case ALLOC_DIR_READ: // allocated to READ FSM + if (((r_read_fsm.read() != READ_DIR_REQ) and + (r_read_fsm.read() != READ_DIR_LOCK) and + (r_read_fsm.read() != READ_TRT_LOCK) and + (r_read_fsm.read() != READ_HEAP_REQ)) + or + ((r_read_fsm.read() == READ_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_READ))) + { + if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + } + break; + + ///////////////////// + case ALLOC_DIR_WRITE: // allocated to WRITE FSM + if (((r_write_fsm.read() != WRITE_DIR_REQ) and + (r_write_fsm.read() != WRITE_DIR_LOCK) and + (r_write_fsm.read() != WRITE_BC_DIR_READ) and + (r_write_fsm.read() != WRITE_DIR_HIT) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and + (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) + or + ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) + or + ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) + { + if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + } + break; + + /////////////////// + case ALLOC_DIR_CAS: // allocated to CAS FSM + if (((r_cas_fsm.read() != CAS_DIR_REQ) and + (r_cas_fsm.read() != CAS_DIR_LOCK) and + (r_cas_fsm.read() != CAS_DIR_HIT_READ) and + (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and + (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and + (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) + or + ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)) + or + ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) + { + if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + } + break; + + /////////////////////// + case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM + if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and + (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + } + break; + + //////////////////////// + case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM + if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) + { + if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + } + break; + + } // end switch alloc_dir_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_TRT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer) + // with a round robin priority between 7 user FSMs : + // The priority is READ > WRITE > CAS > IXR_CMD > XRAM_RSP > IXR_RSP > CONFIG + // The ressource is always allocated. + /////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_trt_fsm" << std::endl; + + switch(r_alloc_trt_fsm.read()) + { + //////////////////// + case ALLOC_TRT_READ: + if (r_read_fsm.read() != READ_TRT_LOCK) + { + if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + } + break; + + ///////////////////// + case ALLOC_TRT_WRITE: + if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) + { + if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + } + break; + + /////////////////// + case ALLOC_TRT_CAS: + if ((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) + { + if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + } + break; + + /////////////////////// + case ALLOC_TRT_IXR_CMD: + if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) + { + if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + } + break; + + //////////////////////// + case ALLOC_TRT_XRAM_RSP: + if (((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or + (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) + { + if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + } + break; + + /////////////////////// + case ALLOC_TRT_IXR_RSP: + if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and + (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) + { + if (r_config_fsm.read() == CONFIG_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + } + break; + + ////////////////////// + case ALLOC_TRT_CONFIG: + if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET)) + { + if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + } + break; + + } // end switch alloc_trt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_HEAP FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_HEAP FSM allocates the access to the heap + // with a round robin priority between 6 user FSMs : + // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP > CONFIG + // The ressource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_heap_fsm" << std::endl; + + switch (r_alloc_heap_fsm.read()) + { + //////////////////// + case ALLOC_HEAP_RESET: + // Initializes the heap one ENTRY each cycle. + + r_alloc_heap_reset_cpt.write(r_alloc_heap_reset_cpt.read() + 1); + + if (r_alloc_heap_reset_cpt.read() == (m_heap_size - 1)) + { + m_heap.init(); + + r_alloc_heap_fsm = ALLOC_HEAP_READ; + } + break; + + //////////////////// + case ALLOC_HEAP_READ: + if ((r_read_fsm.read() != READ_HEAP_REQ) and + (r_read_fsm.read() != READ_HEAP_LOCK) and + (r_read_fsm.read() != READ_HEAP_ERASE)) + { + if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + } + break; + + ///////////////////// + case ALLOC_HEAP_WRITE: + if ((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and + (r_write_fsm.read() != WRITE_UPT_REQ) and + (r_write_fsm.read() != WRITE_UPT_NEXT)) + { + if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + } + break; + + //////////////////// + case ALLOC_HEAP_CAS: + if ((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and + (r_cas_fsm.read() != CAS_UPT_REQ) and + (r_cas_fsm.read() != CAS_UPT_NEXT)) + { + if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + } + break; + + /////////////////////// + case ALLOC_HEAP_CLEANUP: + if ((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + } + break; + + //////////////////////// + case ALLOC_HEAP_XRAM_RSP: + if ((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and + (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE)) + { + if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + } + break; + + /////////////////////// + case ALLOC_HEAP_CONFIG: + if ((r_config_fsm.read() != CONFIG_HEAP_REQ) and + (r_config_fsm.read() != CONFIG_HEAP_SCAN)) + { + if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + } + break; + + } // end switch alloc_heap_fsm + + //std::cout << std::endl << "fifo_update" << std::endl; + + ///////////////////////////////////////////////////////////////////// + // TGT_CMD to READ FIFO + ///////////////////////////////////////////////////////////////////// + + m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.address.read()); + m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.plen.read() >> 2 ); + m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.srcid.read()); + m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.trdid.read()); + m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.pktid.read()); + + ///////////////////////////////////////////////////////////////////// + // TGT_CMD to WRITE FIFO + ///////////////////////////////////////////////////////////////////// + + m_cmd_write_addr_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + (addr_t)p_vci_tgt.address.read()); + m_cmd_write_eop_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.eop.read()); + m_cmd_write_srcid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.srcid.read()); + m_cmd_write_trdid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.trdid.read()); + m_cmd_write_pktid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.pktid.read()); + m_cmd_write_data_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.wdata.read()); + m_cmd_write_be_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.be.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // TGT_CMD to CAS FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cmd_cas_addr_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + (addr_t)p_vci_tgt.address.read()); + m_cmd_cas_eop_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.eop.read()); + m_cmd_cas_srcid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.srcid.read()); + m_cmd_cas_trdid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.trdid.read()); + m_cmd_cas_pktid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.pktid.read()); + m_cmd_cas_wdata_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.wdata.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE to CLEANUP FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, + cc_receive_to_cleanup_fifo_put, + p_dspin_p2m.data.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE to MULTI_ACK FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, + cc_receive_to_multi_ack_fifo_put, + p_dspin_p2m.data.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // WRITE to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, + write_to_cc_send_fifo_put, + write_to_cc_send_fifo_inst ); + m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, + write_to_cc_send_fifo_put, + write_to_cc_send_fifo_srcid ); + + //////////////////////////////////////////////////////////////////////////////////// + // CONFIG to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, + config_to_cc_send_fifo_put, + config_to_cc_send_fifo_inst ); + m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, + config_to_cc_send_fifo_put, + config_to_cc_send_fifo_srcid ); + + //////////////////////////////////////////////////////////////////////////////////// + // XRAM_RSP to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, + xram_rsp_to_cc_send_fifo_put, + xram_rsp_to_cc_send_fifo_inst ); + m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, + xram_rsp_to_cc_send_fifo_put, + xram_rsp_to_cc_send_fifo_srcid ); + + //////////////////////////////////////////////////////////////////////////////////// + // CAS to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, + cas_to_cc_send_fifo_put, + cas_to_cc_send_fifo_inst ); + m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, + cas_to_cc_send_fifo_put, + cas_to_cc_send_fifo_srcid ); + m_cpt_cycles++; + + //////////////////////////////////////////////////////////////////////////////////// + // Update r_config_rsp_lines counter. + // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs + //////////////////////////////////////////////////////////////////////////////////// + if ( config_rsp_lines_incr and not + (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) + { + r_config_rsp_lines = r_config_rsp_lines.read() + 1; + } + if ( not config_rsp_lines_incr and + (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) + { + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + } + + } // end transition() + + ///////////////////////////// + tmpl(void)::genMoore() + ///////////////////////////// + { +#if MONITOR_MEMCACHE_FSM == 1 + p_read_fsm.write (r_read_fsm.read() ); + p_write_fsm.write (r_write_fsm.read() ); + p_xram_rsp_fsm.write (r_xram_rsp_fsm.read() ); + p_cas_fsm.write (r_cas_fsm.read() ); + p_cleanup_fsm.write (r_cleanup_fsm.read() ); + p_config_fsm.write (r_config_fsm.read() ); + p_alloc_heap_fsm.write (r_alloc_heap_fsm.read() ); + p_alloc_dir_fsm.write (r_alloc_dir_fsm.read() ); + p_alloc_trt_fsm.write (r_alloc_trt_fsm.read() ); + p_alloc_upt_fsm.write (r_alloc_upt_fsm.read() ); + p_alloc_ivt_fsm.write (r_alloc_ivt_fsm.read() ); + p_tgt_cmd_fsm.write (r_tgt_cmd_fsm.read() ); + p_tgt_rsp_fsm.write (r_tgt_rsp_fsm.read() ); + p_ixr_cmd_fsm.write (r_ixr_cmd_fsm.read() ); + p_ixr_rsp_fsm.write (r_ixr_rsp_fsm.read() ); + p_cc_send_fsm.write (r_cc_send_fsm.read() ); + p_cc_receive_fsm.write (r_cc_receive_fsm.read() ); + p_multi_ack_fsm.write (r_multi_ack_fsm.read() ); +#endif + + //////////////////////////////////////////////////////////// + // Command signals on the p_vci_ixr port + //////////////////////////////////////////////////////////// + + // DATA width is 8 bytes + // The following values are not transmitted to XRAM + // p_vci_ixr.be + // p_vci_ixr.pktid + // p_vci_ixr.cons + // p_vci_ixr.wrap + // p_vci_ixr.contig + // p_vci_ixr.clen + // p_vci_ixr.cfixed + + p_vci_ixr.plen = 64; + p_vci_ixr.srcid = m_srcid_x; + p_vci_ixr.trdid = r_ixr_cmd_trdid.read(); + p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); + p_vci_ixr.be = 0xFF; + p_vci_ixr.pktid = 0; + p_vci_ixr.cons = false; + p_vci_ixr.wrap = false; + p_vci_ixr.contig = true; + p_vci_ixr.clen = 0; + p_vci_ixr.cfixed = false; + + if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_SEND)) + { + p_vci_ixr.cmdval = true; + + if (r_ixr_cmd_get.read()) // GET + { + p_vci_ixr.cmd = vci_param_ext::CMD_READ; + p_vci_ixr.wdata = 0; + p_vci_ixr.eop = true; + } + else // PUT + { + size_t word = r_ixr_cmd_word.read(); + p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[word].read())) | + ((wide_data_t)(r_ixr_cmd_wdata[word+1].read()) << 32); + p_vci_ixr.eop = (word == (m_words-2)); + } + } + else + { + p_vci_ixr.cmdval = false; + } + + //////////////////////////////////////////////////// + // Response signals on the p_vci_ixr port + //////////////////////////////////////////////////// + + if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE)) + { + p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP); + } + else // r_ixr_rsp_fsm == IXR_RSP_IDLE + { + p_vci_ixr.rspack = false; + } + + //////////////////////////////////////////////////// + // Command signals on the p_vci_tgt port + //////////////////////////////////////////////////// + + switch((tgt_cmd_fsm_state_e) r_tgt_cmd_fsm.read()) + { + case TGT_CMD_IDLE: + p_vci_tgt.cmdack = false; + break; + + case TGT_CMD_CONFIG: + { + addr_t addr_lsb = p_vci_tgt.address.read() & + m_config_addr_mask; + + addr_t cell = (addr_lsb / vci_param_int::B); + + size_t regr = cell & + m_config_regr_idx_mask; + + size_t func = (cell >> m_config_regr_width) & + m_config_func_idx_mask; + + switch(func) + { + case MEMC_CONFIG: + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + and (regr == MEMC_CMD_TYPE)) + { + p_vci_tgt.cmdack = true; + } + else + { + p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); + } + break; + + default: + p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); + break; + } + + break; + } + case TGT_CMD_ERROR: + p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); + break; + + case TGT_CMD_READ: + p_vci_tgt.cmdack = m_cmd_read_addr_fifo.wok(); + break; + + case TGT_CMD_WRITE: + p_vci_tgt.cmdack = m_cmd_write_addr_fifo.wok(); + break; + + case TGT_CMD_CAS: + p_vci_tgt.cmdack = m_cmd_cas_addr_fifo.wok(); + break; + } + + //////////////////////////////////////////////////// + // Response signals on the p_vci_tgt port + //////////////////////////////////////////////////// + + switch(r_tgt_rsp_fsm.read()) + { + case TGT_RSP_CONFIG_IDLE: + case TGT_RSP_TGT_CMD_IDLE: + case TGT_RSP_READ_IDLE: + case TGT_RSP_WRITE_IDLE: + case TGT_RSP_CAS_IDLE: + case TGT_RSP_XRAM_IDLE: + case TGT_RSP_MULTI_ACK_IDLE: + case TGT_RSP_CLEANUP_IDLE: + { + p_vci_tgt.rspval = false; + p_vci_tgt.rsrcid = 0; + p_vci_tgt.rdata = 0; + p_vci_tgt.rpktid = 0; + p_vci_tgt.rtrdid = 0; + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = false; + break; + } + case TGT_RSP_CONFIG: + { + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_config_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_config_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_config_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = r_config_to_tgt_rsp_error.read(); + p_vci_tgt.reop = true; + + break; + } + case TGT_RSP_TGT_CMD: + { + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = r_tgt_cmd_to_tgt_rsp_rdata.read(); + p_vci_tgt.rsrcid = r_tgt_cmd_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_tgt_cmd_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = r_tgt_cmd_to_tgt_rsp_error.read(); + p_vci_tgt.reop = true; + + break; + } + case TGT_RSP_READ: + { + uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + + p_vci_tgt.rspval = true; + + if (is_ll and not r_tgt_rsp_key_sent.read()) + { + // LL response first flit + p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read(); + } + else + { + // LL response second flit or READ response + p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); + } + + p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll); + break; + } + + case TGT_RSP_WRITE: + p_vci_tgt.rspval = true; + if (((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read()) + p_vci_tgt.rdata = 1; + else + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_write_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; + break; + + case TGT_RSP_CLEANUP: + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_cleanup_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_cleanup_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_cleanup_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; // Can be a CAS rsp + p_vci_tgt.reop = true; + break; + + case TGT_RSP_CAS: + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = r_cas_to_tgt_rsp_data.read(); + p_vci_tgt.rsrcid = r_cas_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_cas_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_cas_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; + break; + + case TGT_RSP_XRAM: + { + uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); + + p_vci_tgt.rspval = true; + + if (is_ll and not r_tgt_rsp_key_sent.read()) { + // LL response first flit + p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); + } + else { + // LL response second flit or READ response + p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); + } + + p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = is_error; + p_vci_tgt.reop = (((is_last_word or is_error) and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)); + break; + } + + case TGT_RSP_MULTI_ACK: + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; // Can be a CAS or SC rsp + p_vci_tgt.rsrcid = r_multi_ack_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_multi_ack_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_multi_ack_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; + break; + } // end switch r_tgt_rsp_fsm + + //////////////////////////////////////////////////////////////////// + // p_irq port + // + // WRITE MISS response error signaling + //////////////////////////////////////////////////////////////////// + + p_irq = + r_xram_rsp_rerror_irq.read() && + r_xram_rsp_rerror_irq_enable.read(); + + //////////////////////////////////////////////////////////////////// + // p_dspin_m2p port (CC_SEND FSM) + //////////////////////////////////////////////////////////////////// + + p_dspin_m2p.write = false; + p_dspin_m2p.eop = false; + p_dspin_m2p.data = 0; + + switch(r_cc_send_fsm.read()) + { + /////////////////////////// + case CC_SEND_CONFIG_IDLE: + case CC_SEND_XRAM_RSP_IDLE: + case CC_SEND_WRITE_IDLE: + case CC_SEND_CAS_IDLE: + { + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_HEADER: + { + uint8_t multi_inval_type; + if (m_config_to_cc_send_inst_fifo.read()) + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; + } + else + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; + } + + uint64_t flit = 0; + uint64_t dest = m_config_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set( flit, + multi_inval_type, + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_HEADER: + { + if (not m_xram_rsp_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_inval_type; + if (m_xram_rsp_to_cc_send_inst_fifo.read()) + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; + } + else + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; + } + + uint64_t flit = 0; + uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set( flit, + multi_inval_type, + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + + ////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_NLINE: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + + ///////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_HEADER: + case CC_SEND_XRAM_RSP_BRDCAST_HEADER: + case CC_SEND_WRITE_BRDCAST_HEADER: + case CC_SEND_CAS_BRDCAST_HEADER: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( flit, + m_broadcast_boundaries, + DspinDhccpParam::BROADCAST_BOX); + + DspinDhccpParam::dspin_set( flit, + 1ULL, + DspinDhccpParam::M2P_BC); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + //////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + ////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + ///////////////////////////////// + case CC_SEND_WRITE_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_write_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////// + case CC_SEND_CAS_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_cas_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////// + case CC_SEND_WRITE_UPDT_HEADER: + { + if (not m_write_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_updt_type; + if (m_write_to_cc_send_inst_fifo.read()) + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; + } + else + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + m_write_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::MULTI_UPDT_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_type, + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + ////////////////////////////// + case CC_SEND_WRITE_UPDT_NLINE: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_index.read(), + DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_UPDT_NLINE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + ///////////////////////////// + case CC_SEND_WRITE_UPDT_DATA: + { + + uint8_t multi_updt_cpt = + r_cc_send_cpt.read() + r_write_to_cc_send_index.read(); + + uint8_t multi_updt_be = r_write_to_cc_send_be[multi_updt_cpt].read(); + uint32_t multi_updt_data = r_write_to_cc_send_data[multi_updt_cpt].read(); + + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + multi_updt_be, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_data, + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()); + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////// + case CC_SEND_CAS_UPDT_HEADER: + { + if (not m_cas_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_updt_type; + if (m_cas_to_cc_send_inst_fifo.read()) + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; + } + else + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + m_cas_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::MULTI_UPDT_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_type, + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////// + case CC_SEND_CAS_UPDT_NLINE: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_index.read(), + DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_UPDT_NLINE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + /////////////////////////// + case CC_SEND_CAS_UPDT_DATA: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + 0xF, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_wdata.read(), + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////////// + case CC_SEND_CAS_UPDT_DATA_HIGH: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + 0xF, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_wdata_high.read(), + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + + break; + } + } + + //////////////////////////////////////////////////////////////////// + // p_dspin_clack port (CLEANUP FSM) + //////////////////////////////////////////////////////////////////// + + if (r_cleanup_fsm.read() == CLEANUP_SEND_CLACK) + { + uint8_t cleanup_ack_type; + if (r_cleanup_inst.read()) + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; + } + else + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; + } + + uint64_t flit = 0; + uint64_t dest = r_cleanup_srcid.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::CLACK_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_nline.read(), + DspinDhccpParam::CLACK_SET); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_way_index.read(), + DspinDhccpParam::CLACK_WAY); + + DspinDhccpParam::dspin_set( + flit, + cleanup_ack_type, + DspinDhccpParam::CLACK_TYPE); + + p_dspin_clack.eop = true; + p_dspin_clack.write = true; + p_dspin_clack.data = flit; + } + else + { + p_dspin_clack.write = false; + p_dspin_clack.eop = false; + p_dspin_clack.data = 0; + } + + /////////////////////////////////////////////////////////////////// + // p_dspin_p2m port (CC_RECEIVE FSM) + /////////////////////////////////////////////////////////////////// + // + switch(r_cc_receive_fsm.read()) + { + case CC_RECEIVE_IDLE: + { + p_dspin_p2m.read = false; + break; + } + case CC_RECEIVE_CLEANUP: + case CC_RECEIVE_CLEANUP_EOP: + { + p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); + break; + } + case CC_RECEIVE_MULTI_ACK: + { + p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); + break; + } + } + // end switch r_cc_send_fsm + } // end genMoore() + +} +} // end name space + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: branches/fault_tolerance/module/internal_component/vci_mem_cache/include/soclib/mem_cache.h =================================================================== --- branches/fault_tolerance/module/internal_component/vci_mem_cache/include/soclib/mem_cache.h (revision 647) +++ branches/fault_tolerance/module/internal_component/vci_mem_cache/include/soclib/mem_cache.h (revision 647) @@ -0,0 +1,200 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * alain greiner + * + * Maintainers: alain + */ +#ifndef MEM_CACHE_REGS_H +#define MEM_CACHE_REGS_H + +enum SoclibMemCacheFunc +{ + MEMC_CONFIG = 0, + MEMC_INSTRM = 1, + MEMC_RERROR = 2, + + MEMC_FUNC_SPAN = 0x200 +}; + +enum SoclibMemCacheConfigRegs +{ + MEMC_LOCK, + MEMC_ADDR_LO, + MEMC_ADDR_HI, + MEMC_BUF_LENGTH, + MEMC_CMD_TYPE +}; + +enum SoclibMemCacheConfigCmd +{ + MEMC_CMD_NOP, + MEMC_CMD_INVAL, + MEMC_CMD_SYNC +}; + +/////////////////////////////////////////////////////////// +// Decoding CONFIG interface commands // +// // +// VCI ADDRESS // +// ================================================ // +// GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // +// IDX | IDX | | (3 bits) | (7 bits) | // +// ================================================ // +// // +// For instrumentation: FUNC_IDX = 0b001 // +// // +// REGS_IDX // +// ============================================ // +// Z | Y | X | W // +// (1 bit) | (2 bits) | (3 bits) | (1 bit) // +// ============================================ // +// // +// For configuration: FUNC_IDX = 0b000 // +// // +// REGS_IDX // +// ============================================ // +// RESERVED | X | // +// (4 bits) | (3 bits) | // +// ============================================ // +// // +// X : REGISTER INDEX // +// // +// For WRITE MISS error signaling: FUNC = 0x010 // +// // +// REGS_IDX // +// ============================================ // +// RESERVED | X | // +// (4 bits) | (3 bits) | // +// ============================================ // +// // +// X : REGISTER INDEX // +// // +/////////////////////////////////////////////////////////// + +enum SoclibMemCacheInstrRegs { + /////////////////////////////////////////////////////// + // DIRECT instrumentation registers // + /////////////////////////////////////////////////////// + + // LOCAL + + MEMC_LOCAL_READ_LO = 0x00, + MEMC_LOCAL_READ_HI = 0x01, + MEMC_LOCAL_WRITE_LO = 0x02, + MEMC_LOCAL_WRITE_HI = 0x03, + MEMC_LOCAL_LL_LO = 0x04, + MEMC_LOCAL_LL_HI = 0x05, + MEMC_LOCAL_SC_LO = 0x06, + MEMC_LOCAL_SC_HI = 0x07, + MEMC_LOCAL_CAS_LO = 0x08, + MEMC_LOCAL_CAS_HI = 0x09, + + // REMOTE + + MEMC_REMOTE_READ_LO = 0x10, + MEMC_REMOTE_READ_HI = 0x11, + MEMC_REMOTE_WRITE_LO = 0x12, + MEMC_REMOTE_WRITE_HI = 0x13, + MEMC_REMOTE_LL_LO = 0x14, + MEMC_REMOTE_LL_HI = 0x15, + MEMC_REMOTE_SC_LO = 0x16, + MEMC_REMOTE_SC_HI = 0x17, + MEMC_REMOTE_CAS_LO = 0x18, + MEMC_REMOTE_CAS_HI = 0x19, + + // COST + + MEMC_COST_READ_LO = 0x20, + MEMC_COST_READ_HI = 0x21, + MEMC_COST_WRITE_LO = 0x22, + MEMC_COST_WRITE_HI = 0x23, + MEMC_COST_LL_LO = 0x24, + MEMC_COST_LL_HI = 0x25, + MEMC_COST_SC_LO = 0x26, + MEMC_COST_SC_HI = 0x27, + MEMC_COST_CAS_LO = 0x28, + MEMC_COST_CAS_HI = 0x29, + + /////////////////////////////////////////////////////// + // COHERENCE instrumentation registers // + /////////////////////////////////////////////////////// + + // LOCAL + + MEMC_LOCAL_MUPDATE_LO = 0x40, + MEMC_LOCAL_MUPDATE_HI = 0x41, + MEMC_LOCAL_MINVAL_LO = 0x42, + MEMC_LOCAL_MINVAL_HI = 0x43, + MEMC_LOCAL_CLEANUP_LO = 0x44, + MEMC_LOCAL_CLEANUP_HI = 0x45, + + // REMOTE + + MEMC_REMOTE_MUPDATE_LO = 0x50, + MEMC_REMOTE_MUPDATE_HI = 0x51, + MEMC_REMOTE_MINVAL_LO = 0x52, + MEMC_REMOTE_MINVAL_HI = 0x53, + MEMC_REMOTE_CLEANUP_LO = 0x54, + MEMC_REMOTE_CLEANUP_HI = 0x55, + + // COST + + MEMC_COST_MUPDATE_LO = 0x60, + MEMC_COST_MUPDATE_HI = 0x61, + MEMC_COST_MINVAL_LO = 0x62, + MEMC_COST_MINVAL_HI = 0x63, + MEMC_COST_CLEANUP_LO = 0x64, + MEMC_COST_CLEANUP_HI = 0x65, + + // TOTAL + + MEMC_TOTAL_MUPDATE_LO = 0x68, + MEMC_TOTAL_MUPDATE_HI = 0x69, + MEMC_TOTAL_MINVAL_LO = 0x6A, + MEMC_TOTAL_MINVAL_HI = 0x6B, + MEMC_TOTAL_BINVAL_LO = 0x6C, + MEMC_TOTAL_BINVAL_HI = 0x6D, +}; + +enum SoclibMemCacheRerrorRegs +{ + MEMC_RERROR_ADDR_LO = 0, + MEMC_RERROR_ADDR_HI, + MEMC_RERROR_SRCID, + MEMC_RERROR_IRQ_RESET, + MEMC_RERROR_IRQ_ENABLE +}; + +#define MEMC_REG(func,idx) ((func<<7)|idx) + +#endif /* MEM_CACHE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: branches/fault_tolerance/module/network_component/dspin_router/caba/metadata/dspin_router.sd =================================================================== --- branches/fault_tolerance/module/network_component/dspin_router/caba/metadata/dspin_router.sd (revision 647) +++ branches/fault_tolerance/module/network_component/dspin_router/caba/metadata/dspin_router.sd (revision 647) @@ -0,0 +1,27 @@ +# -*- python -*- + +Module('caba:dspin_router', + classname = 'soclib::caba::DspinRouter', + tmpl_parameters = [ parameter.Int('flit_width'), ], + header_files = ['../source/include/dspin_router.h',], + implementation_files = ['../source/src/dspin_router.cpp',], + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_out', 5, dspin_data_size = parameter.Reference('flit_width')), + Port('caba:dspin_input', 'p_in', 5, dspin_data_size = parameter.Reference('flit_width')), + ], + instance_parameters = [ + parameter.Int('x'), + parameter.Int('y'), + parameter.Int('x_width'), + parameter.Int('y_width'), + parameter.Int('in_fifo_depth'), + parameter.Int('out_fifo_depth'), + parameter.Bool('broadcast_supported'), + ], + uses = [ + Uses('caba:base_module'), + Uses('caba:generic_fifo'), + ], +) Index: branches/fault_tolerance/module/network_component/dspin_router/caba/source/include/dspin_router.h =================================================================== --- branches/fault_tolerance/module/network_component/dspin_router/caba/source/include/dspin_router.h (revision 647) +++ branches/fault_tolerance/module/network_component/dspin_router/caba/source/include/dspin_router.h (revision 647) @@ -0,0 +1,162 @@ +/* -*- c++ -*- + * + * File : dspin_router.h + * Copyright (c) UPMC, Lip6 + * Authors : Alain Greiner, Abbas Sheibanyrad, Ivan Miro, Zhen Zhang + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + */ + + /////////////////////////////////////////////////////////////////////////// + // Implementation Note : + // The xfirst_route(), broadcast_route() and is_broadcast() functions + // defined below are used to decode the DSPIN first flit format: + // - In case of a non-broadcast packet : + // | X | Y |---------------------------------------|BC | + // | x_width | y_width | flit_width - (x_width + y_width + 2) | 0 | + // + // - In case of a broacast + // | XMIN | XMAX | YMIN | YMAX |-------------------|BC | + // | 5 | 5 | 5 | 5 | flit_width - 22 | 1 | + /////////////////////////////////////////////////////////////////////////// + +#ifndef DSPIN_ROUTER_H_ +#define DSPIN_ROUTER_H_ + +#include +#include "caba_base_module.h" +#include "generic_fifo.h" +#include "dspin_interface.h" +#include "alloc_elems.h" + +namespace soclib { namespace caba { + +using namespace sc_core; + +template +class DspinRouter +: public soclib::caba::BaseModule +{ + // Port indexing + enum + { + REQ_NORTH = 0, + REQ_SOUTH = 1, + REQ_EAST = 2, + REQ_WEST = 3, + REQ_LOCAL = 4, + REQ_NOP = 5, + }; + + // Input Port FSM + enum + { + INFSM_IDLE, + INFSM_REQ, + INFSM_ALLOC, + INFSM_REQ_FIRST, + INFSM_ALLOC_FIRST, + INFSM_REQ_SECOND, + INFSM_ALLOC_SECOND, + INFSM_REQ_THIRD, + INFSM_ALLOC_THIRD, + INFSM_REQ_FOURTH, + INFSM_ALLOC_FOURTH, + }; + + protected: + SC_HAS_PROCESS(DspinRouter); + + public: + + // ports + sc_in p_clk; + sc_in p_resetn; + DspinInput *p_in; + DspinOutput *p_out; + + // constructor / destructor + DspinRouter( sc_module_name name, + const size_t x, + const size_t y, + const size_t x_width, + const size_t y_width, + const size_t in_fifo_depth, + const size_t out_fifo_depth, + const bool broadcast_supported = false ); // default value + + private: + + // define the FIFO flit + typedef struct internal_flit_s + { + sc_uint data; + bool eop; + } internal_flit_t; + + // registers + sc_signal *r_alloc_out; // output port is allocated + sc_signal *r_index_out; // index of owner input port + + sc_signal *r_fsm_in; // input port state + sc_signal *r_index_in; // index of requested output port + internal_flit_t *r_buf_in; // save first flit for a broadcast + + // fifos + soclib::caba::GenericFifo* r_fifo_in; + soclib::caba::GenericFifo* r_fifo_out; + + // structural parameters + size_t m_local_x; + size_t m_local_y; + size_t m_x_width; + size_t m_x_shift; + size_t m_x_mask; + size_t m_y_width; + size_t m_y_shift; + size_t m_y_mask; + bool m_broadcast_supported; + + // methods + void transition(); + void genMoore(); + int xfirst_route( sc_uint data ); + int broadcast_route( int iter, int source, sc_uint data ); + bool is_broadcast( sc_uint data ); + + public: + + void print_trace(); +}; + +}} // end namespace + +#endif // DSPIN_ROUTER_BC_H_ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: branches/fault_tolerance/module/network_component/dspin_router/caba/source/src/dspin_router.cpp =================================================================== --- branches/fault_tolerance/module/network_component/dspin_router/caba/source/src/dspin_router.cpp (revision 647) +++ branches/fault_tolerance/module/network_component/dspin_router/caba/source/src/dspin_router.cpp (revision 647) @@ -0,0 +1,586 @@ +/* -*- c++ -*- + * + * File : dspin_router.cpp + * Copyright (c) UPMC, Lip6 + * Authors : Alain Greiner, Abbas Sheibanyrad, Ivan Miro, Zhen Zhang + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + */ + + /////////////////////////////////////////////////////////////////////////// + // Implementation Note : + // The xfirst_route(), broadcast_route() and is_broadcast() functions + // defined below are used to decode the DSPIN first flit format: + // - In case of a non-broadcast packet : + // | X | Y |---------------------------------------|BC | + // | x_width | y_width | flit_width - (x_width + y_width + 2) | 0 | + // + // - In case of a broacast + // | XMIN | XMAX | YMIN | YMAX |-------------------|BC | + // | 5 | 5 | 5 | 5 | flit_width - 22 | 1 | + /////////////////////////////////////////////////////////////////////////// + +#include "../include/dspin_router.h" + +namespace soclib { namespace caba { + +using namespace soclib::common; +using namespace soclib::caba; + +#define tmpl(x) template x DspinRouter + + //////////////////////////////////////////////// + // constructor + //////////////////////////////////////////////// + tmpl(/**/)::DspinRouter( sc_module_name name, + const size_t x, + const size_t y, + const size_t x_width, + const size_t y_width, + const size_t in_fifo_depth, + const size_t out_fifo_depth, + const bool broadcast_supported ) + : soclib::caba::BaseModule(name), + + p_clk( "p_clk" ), + p_resetn( "p_resetn" ), + p_in( alloc_elems >("p_in", 5) ), + p_out( alloc_elems >("p_out", 5) ), + + r_alloc_out( alloc_elems >("r_alloc_out", 5)), + r_index_out( soclib::common::alloc_elems >("r_index_out", 5)), + r_fsm_in( alloc_elems >("r_fsm_in", 5)), + r_index_in( alloc_elems >("r_index_in", 5)), + + m_local_x( x ), + m_local_y( y ), + m_x_width( x_width ), + m_x_shift( flit_width - x_width ), + m_x_mask( (0x1 << x_width) - 1 ), + m_y_width( y_width ), + m_y_shift( flit_width - x_width - y_width ), + m_y_mask( (0x1 << y_width) - 1 ), + m_broadcast_supported( broadcast_supported ) + { + std::cout << " - Building DspinRouter : " << name << std::endl; + + SC_METHOD (transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD (genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + r_fifo_in = (GenericFifo*) + malloc(sizeof(GenericFifo) * 5); + + r_fifo_out = (GenericFifo*) + malloc(sizeof(GenericFifo) * 5); + + r_buf_in = (internal_flit_t*) + malloc(sizeof(internal_flit_t) * 5); + + for( size_t i = 0 ; i < 5 ; i++ ) + { + std::ostringstream stri; + stri << "r_in_fifo_" << i; + new(&r_fifo_in[i]) + GenericFifo(stri.str(), in_fifo_depth); + + std::ostringstream stro; + stro << "r_out_fifo_" << i; + new(&r_fifo_out[i]) + GenericFifo(stro.str(), out_fifo_depth); + } + } // end constructor + + /////////////////////////////////////////////////// + tmpl(int)::xfirst_route( sc_uint data ) + { + size_t xdest = (size_t)(data >> m_x_shift) & m_x_mask; + size_t ydest = (size_t)(data >> m_y_shift) & m_y_mask; + return (xdest < m_local_x ? REQ_WEST : + (xdest > m_local_x ? REQ_EAST : + (ydest < m_local_y ? REQ_SOUTH : + (ydest > m_local_y ? REQ_NORTH : REQ_LOCAL)))); + } + + ////////////////////////////////////////////////////////////////////////// + tmpl(int)::broadcast_route(int step, int source, sc_uint data) + { + int sel = REQ_NOP; + size_t xmin = (data >> (flit_width - 5 )) & 0x1F; + size_t xmax = (data >> (flit_width - 10)) & 0x1F; + size_t ymin = (data >> (flit_width - 15)) & 0x1F; + size_t ymax = (data >> (flit_width - 20)) & 0x1F; + + switch(source) { + case REQ_LOCAL : + if ( step == 1 ) sel = REQ_NORTH; + else if ( step == 2 ) sel = REQ_SOUTH; + else if ( step == 3 ) sel = REQ_EAST; + else if ( step == 4 ) sel = REQ_WEST; + break; + case REQ_NORTH : + if ( step == 1 ) sel = REQ_SOUTH; + else if ( step == 2 ) sel = REQ_LOCAL; + else if ( step == 3 ) sel = REQ_NOP; + else if ( step == 4 ) sel = REQ_NOP; + break; + case REQ_SOUTH : + if ( step == 1 ) sel = REQ_NORTH; + else if ( step == 2 ) sel = REQ_LOCAL; + else if ( step == 3 ) sel = REQ_NOP; + else if ( step == 4 ) sel = REQ_NOP; + break; + case REQ_EAST : + if ( step == 1 ) sel = REQ_WEST; + else if ( step == 2 ) sel = REQ_NORTH; + else if ( step == 3 ) sel = REQ_SOUTH; + else if ( step == 4 ) sel = REQ_LOCAL; + break; + case REQ_WEST : + if ( step == 1 ) sel = REQ_EAST; + else if ( step == 2 ) sel = REQ_NORTH; + else if ( step == 3 ) sel = REQ_SOUTH; + else if ( step == 4 ) sel = REQ_LOCAL; + break; + } + if ( (sel == REQ_NORTH) && !(m_local_y < ymax) ) sel = REQ_NOP; + else if ( (sel == REQ_SOUTH) && !(m_local_y > ymin) ) sel = REQ_NOP; + else if ( (sel == REQ_EAST ) && !(m_local_x < xmax) ) sel = REQ_NOP; + else if ( (sel == REQ_WEST ) && !(m_local_x > xmin) ) sel = REQ_NOP; + + return sel; + } + + ///////////////////////////////////////////////////////// + tmpl(inline bool)::is_broadcast(sc_uint data) + { + return ( (data & 0x1) != 0); + } + + ///////////////////////// + tmpl(void)::print_trace() + { + const char* port_name[] = + { + "N", + "S", + "E", + "W", + "L" + }; + + const char* infsm_str[] = + { + "IDLE", + "REQ", + "ALLOC", + "REQ_FIRST", + "ALLOC_FIRST", + "REQ_SECOND", + "ALLOC_SECOND", + "REQ_THIRD", + "ALLOC_THIRD", + "REQ_FOURTH", + "ALLOC_FOURTH" + }; + + std::cout << "DSPIN_ROUTER " << name(); + + for( size_t i = 0 ; i < 5 ; i++) // loop on input ports + { + std::cout << " / infsm[" << port_name[i] << "] " + << infsm_str[r_fsm_in[i].read()]; + } + + for ( size_t out=0 ; out<5 ; out++) // loop on output ports + { + if ( r_alloc_out[out].read() ) + { + int in = r_index_out[out]; + std::cout << " / " << port_name[in] << " -> " << port_name[out] ; + } + } + std::cout << std::endl; + } + + //////////////////////// + tmpl(void)::transition() + { + // Long wires connecting input and output ports + size_t req_in[5]; // input ports -> output ports + size_t get_out[5]; // output ports -> input ports + bool put_in[5]; // input ports -> output ports + internal_flit_t data_in[5]; // input ports -> output ports + + // control signals for the input fifos + bool fifo_in_write[5]; + bool fifo_in_read[5]; + internal_flit_t fifo_in_wdata[5]; + + // control signals for the output fifos + bool fifo_out_write[5]; + bool fifo_out_read[5]; + internal_flit_t fifo_out_wdata[5]; + + // Reset + if ( p_resetn == false ) + { + for(size_t i = 0 ; i < 5 ; i++) + { + r_alloc_out[i] = false; + r_index_out[i] = 0; + r_index_in[i] = 0; + r_fsm_in[i] = INFSM_IDLE; + r_fifo_in[i].init(); + r_fifo_out[i].init(); + } + return; + } + + // fifos signals default values + for(size_t i = 0 ; i < 5 ; i++) + { + fifo_in_read[i] = false; + fifo_in_write[i] = p_in[i].write.read(); + fifo_in_wdata[i].data = p_in[i].data.read(); + fifo_in_wdata[i].eop = p_in[i].eop.read(); + + fifo_out_read[i] = p_out[i].read.read(); + fifo_out_write[i] = false; + } + + // loop on the output ports: + // compute get_out[j] depending on the output port state + // and combining fifo_out[j].wok and r_alloc_out[j] + for ( size_t j = 0 ; j < 5 ; j++ ) + { + if( r_alloc_out[j].read() and (r_fifo_out[j].wok()) ) + { + get_out[j] = r_index_out[j].read(); + } + else + { + get_out[j] = 0xFFFFFFFF; + } + } + + // loop on the input ports : + // The port state is defined by r_fsm_in[i], r_index_in[i] & r_buf_in[i] + // The req_in[i] computation implements the X-FIRST algorithm. + // data_in[i], put_in[i] and req_in[i] depend on the input port state. + // The fifo_in_read[i] is computed further... + + for ( size_t i = 0 ; i < 5 ; i++ ) + { + switch ( r_fsm_in[i].read() ) + { + case INFSM_IDLE: // no output port allocated + { + put_in[i] = false; + if ( r_fifo_in[i].rok() ) // packet available in input fifo + { + if ( is_broadcast( r_fifo_in[i].read().data ) and + m_broadcast_supported ) // broadcast + { + fifo_in_read[i] = true; + req_in[i] = broadcast_route(1, i, r_fifo_in[i].read().data); + r_buf_in[i] = r_fifo_in[i].read(); + r_index_in[i] = req_in[i]; + if( req_in[i] == REQ_NOP ) r_fsm_in[i] = INFSM_REQ_SECOND; + else r_fsm_in[i] = INFSM_REQ_FIRST; + } + else // unicast + { + req_in[i] = xfirst_route(r_fifo_in[i].read().data); + r_index_in[i] = req_in[i]; + r_fsm_in[i] = INFSM_REQ; + } + } + else + { + req_in[i] = REQ_NOP; + } + break; + } + case INFSM_REQ: // not a broadcast / waiting output port allocation + { + data_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = r_index_in[i]; + fifo_in_read[i] = (get_out[r_index_in[i].read()] == i); + if ( get_out[r_index_in[i].read()] == i ) // first flit transfered + { + if ( r_fifo_in[i].read().eop ) r_fsm_in[i] = INFSM_IDLE; + else r_fsm_in[i] = INFSM_ALLOC; + } + break; + } + case INFSM_ALLOC: // not a broadcast / output port allocated + { + data_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = REQ_NOP; // no request + fifo_in_read[i] = (get_out[r_index_in[i].read()] == i); + if ( r_fifo_in[i].read().eop and + r_fifo_in[i].rok() and + (get_out[r_index_in[i].read()] == i) ) // last flit transfered + { + r_fsm_in[i] = INFSM_IDLE; + } + break; + } + case INFSM_REQ_FIRST: // broacast / waiting first output port allocation + { + data_in[i] = r_buf_in[i]; + put_in[i] = true; + req_in[i] = broadcast_route(1, i, r_buf_in[i].data); + r_index_in[i] = req_in[i]; + if ( req_in[i] == REQ_NOP ) // no transfer for this step + { + r_fsm_in[i] = INFSM_REQ_SECOND; + } + else + { + if( get_out[req_in[i]] == i ) // header flit transfered + { + r_fsm_in[i] = INFSM_ALLOC_FIRST; + } + } + break; + } + case INFSM_ALLOC_FIRST: // broadcast / first output port allocated + { + data_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = REQ_NOP; + if( (get_out[r_index_in[i].read()] == i) + and r_fifo_in[i].rok() ) // data flit transfered + { + if ( not r_fifo_in[i].read().eop ) + { + std::cout << "ERROR in DSPIN_ROUTER " << name() + << " : broadcast packet must be 2 flits" << std::endl; + } + r_fsm_in[i] = INFSM_REQ_SECOND; + } + break; + } + case INFSM_REQ_SECOND: // broacast / waiting second output port allocation + { + data_in[i] = r_buf_in[i]; + put_in[i] = true; + req_in[i] = broadcast_route(2, i, r_buf_in[i].data); + r_index_in[i] = req_in[i]; + if ( req_in[i] == REQ_NOP ) // no transfer for this step + { + r_fsm_in[i] = INFSM_REQ_THIRD; + } + else + { + if( get_out[req_in[i]] == i ) // header flit transfered + { + r_fsm_in[i] = INFSM_ALLOC_SECOND; + } + } + break; + } + case INFSM_ALLOC_SECOND: // broadcast / second output port allocated + { + data_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = REQ_NOP; + if( (get_out[r_index_in[i].read()] == i ) + and r_fifo_in[i].rok() ) // data flit transfered + { + if ( not r_fifo_in[i].read().eop ) + { + std::cout << "ERROR in DSPIN_ROUTER " << name() + << " : broadcast packet must be 2 flits" << std::endl; + } + r_fsm_in[i] = INFSM_REQ_THIRD; + } + break; + } + case INFSM_REQ_THIRD: // broacast / waiting third output port allocation + { + data_in[i] = r_buf_in[i]; + put_in[i] = true; + req_in[i] = broadcast_route(3, i, r_buf_in[i].data); + r_index_in[i] = req_in[i]; + if ( req_in[i] == REQ_NOP ) // no transfer for this step + { + r_fsm_in[i] = INFSM_REQ_FOURTH; + } + else + { + if( get_out[req_in[i]] == i ) // header flit transfered + { + r_fsm_in[i] = INFSM_ALLOC_THIRD; + } + } + break; + } + case INFSM_ALLOC_THIRD: // broadcast / third output port allocated + { + data_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = REQ_NOP; + if( (get_out[r_index_in[i].read()] == i ) + and r_fifo_in[i].rok() ) // data flit transfered + { + if ( not r_fifo_in[i].read().eop ) + { + std::cout << "ERROR in DSPIN_ROUTER " << name() + << " : broadcast packet must be 2 flits" << std::endl; + } + r_fsm_in[i] = INFSM_REQ_FOURTH; + } + break; + } + case INFSM_REQ_FOURTH: // broacast / waiting fourth output port allocation + { + data_in[i] = r_buf_in[i]; + put_in[i] = true; + req_in[i] = broadcast_route(4, i, r_buf_in[i].data); + r_index_in[i] = req_in[i]; + if ( req_in[i] == REQ_NOP ) // no transfer for this step + { + fifo_in_read[i] = true; + r_fsm_in[i] = INFSM_IDLE; + } + else + { + if( get_out[req_in[i]] == i ) // header flit transfered + { + r_fsm_in[i] = INFSM_ALLOC_FOURTH; + } + } + break; + } + case INFSM_ALLOC_FOURTH: // broadcast / fourth output port allocated + { + data_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = REQ_NOP; + if( (get_out[r_index_in[i].read()] == i ) + and r_fifo_in[i].rok() ) // data flit transfered + { + if ( not r_fifo_in[i].read().eop ) + { + std::cout << "ERROR in DSPIN_ROUTER " << name() + << " : broadcast packet must be 2 flits" << std::endl; + } + fifo_in_read[i] = true; + r_fsm_in[i] = INFSM_IDLE; + } + break; + } + } // end switch + } // end for input ports + + // loop on the output ports : + // The r_alloc_out[j] and r_index_out[j] computation + // implements the round-robin allocation policy. + // These two registers implement a 10 states FSM. + for( size_t j = 0 ; j < 5 ; j++ ) + { + if( not r_alloc_out[j].read() ) // not allocated: possible new allocation + { + for( size_t k = r_index_out[j].read() + 1 ; + k < (r_index_out[j] + 6) ; k++) + { + size_t i = k % 5; + + if( req_in[i] == j ) + { + r_alloc_out[j] = true; + r_index_out[j] = i; + break; + } + } // end loop on input ports + } + else // allocated: possible desallocation + { + if ( data_in[r_index_out[j]].eop and + r_fifo_out[j].wok() and + put_in[r_index_out[j]] ) + { + r_alloc_out[j] = false; + } + } + } // end loop on output ports + + // loop on the output ports : + // The fifo_out_write[j] and fifo_out_wdata[j] computation + // implements the output port mux. + for( size_t j = 0 ; j < 5 ; j++ ) + { + if( r_alloc_out[j] ) // output port allocated + { + fifo_out_write[j] = put_in[r_index_out[j]]; + fifo_out_wdata[j] = data_in[r_index_out[j]]; + } + } // end loop on the output ports + + // FIFOS update + for(size_t i = 0 ; i < 5 ; i++) + { + r_fifo_in[i].update(fifo_in_read[i], + fifo_in_write[i], + fifo_in_wdata[i]); + r_fifo_out[i].update(fifo_out_read[i], + fifo_out_write[i], + fifo_out_wdata[i]); + } + } // end transition + + //////////////////////////////// + // genMoore + //////////////////////////////// + tmpl(void)::genMoore() + { + for(size_t i = 0 ; i < 5 ; i++) + { + // input ports : READ signals + p_in[i].read = r_fifo_in[i].wok(); + + // output ports : DATA & WRITE signals + p_out[i].data = r_fifo_out[i].read().data; + p_out[i].eop = r_fifo_out[i].read().eop; + p_out[i].write = r_fifo_out[i].rok(); + } + } // end genMoore + +}} // end namespace + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4