Changeset 648 for branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include
- Timestamp:
- Mar 2, 2014, 10:14:35 PM (10 years ago)
- Location:
- branches/fault_tolerance/platform/tsar_generic_iob
- Files:
-
- 1 edited
- 1 copied
Legend:
- Unmodified
- Added
- Removed
-
branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r607 r648 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_iob_cluster.h 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : april 2013 … … 32 32 #include "vci_io_bridge.h" 33 33 34 namespace soclib { namespace caba 34 namespace soclib { namespace caba { 35 35 36 36 /////////////////////////////////////////////////////////////////////////// 37 template<typename vci_param_int, 37 template<typename vci_param_int, 38 38 typename vci_param_ext, 39 size_t dspin_int_cmd_width, 39 size_t dspin_int_cmd_width, 40 40 size_t dspin_int_rsp_width, 41 41 size_t dspin_ram_cmd_width, 42 42 size_t dspin_ram_rsp_width> 43 class TsarIobCluster 43 class TsarIobCluster 44 44 /////////////////////////////////////////////////////////////////////////// 45 45 : public soclib::caba::BaseModule 46 46 { 47 47 48 public: 49 50 // Ports 51 sc_in<bool> p_clk; 52 sc_in<bool> p_resetn; 53 54 // Thes two ports are used to connect IOB to IOX nework in top cell 55 soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; 56 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 57 58 // These ports are used to connect IOB to RAM network in top cell 59 soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out; 60 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in; 61 62 // These ports are used to connect hard IRQ from external peripherals to IOB0 63 sc_in<bool>* p_irq[32]; 64 65 // These arrays of ports are used to connect the INT & RAM networks in top cell 66 soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; 67 soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; 68 soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out; 69 soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in; 70 71 soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; 72 soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; 73 soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; 74 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; 75 76 // interrupt signals 77 sc_signal<bool> signal_false; 78 sc_signal<bool> signal_proc_it[8]; 79 sc_signal<bool> signal_irq_mdma[8]; 80 sc_signal<bool> signal_irq_memc; 81 82 // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars 83 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 84 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 85 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 86 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 87 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 88 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 89 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 90 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 91 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 92 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 93 94 // INT network VCI signals between VCI components and VCI/DSPIN wrappers 95 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 96 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 97 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 98 99 VciSignals<vci_param_int> signal_int_vci_tgt_memc; 100 VciSignals<vci_param_int> signal_int_vci_tgt_xicu; 101 VciSignals<vci_param_int> signal_int_vci_tgt_mdma; 102 VciSignals<vci_param_int> signal_int_vci_tgt_iobx; 103 104 // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN wrappers 105 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8]; 106 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8]; 107 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i; 108 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i; 109 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i; 110 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i; 111 112 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t; 113 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t; 114 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t; 115 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t; 116 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t; 117 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t; 118 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t; 119 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t; 120 121 // Coherence DSPIN signals between DSPIN local crossbars and CC components 122 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; 123 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; 124 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; 125 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; 126 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; 127 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; 128 129 // RAM network VCI signals between VCI components and VCI/DSPIN wrappers 130 VciSignals<vci_param_ext> signal_ram_vci_ini_memc; 131 VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; 132 VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; 133 134 // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 135 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 136 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; 137 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; 138 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; 139 140 ////////////////////////////////////// 141 // Hardwate Components (pointers) 142 ////////////////////////////////////// 143 VciCcVCacheWrapper<vci_param_int, 144 dspin_int_cmd_width, 145 dspin_int_rsp_width, 146 GdbServer<Mips32ElIss> >* proc[8]; 147 148 VciDspinInitiatorWrapper<vci_param_int, 149 dspin_int_cmd_width, 150 dspin_int_rsp_width>* proc_wi[8]; 151 152 VciMemCache<vci_param_int, 153 vci_param_ext, 154 dspin_int_rsp_width, 155 dspin_int_cmd_width>* memc; 156 157 VciDspinTargetWrapper<vci_param_int, 158 dspin_int_cmd_width, 159 dspin_int_rsp_width>* memc_int_wt; 160 161 VciDspinInitiatorWrapper<vci_param_ext, 162 dspin_ram_cmd_width, 163 dspin_ram_rsp_width>* memc_ram_wi; 164 165 VciXicu<vci_param_int>* xicu; 166 167 VciDspinTargetWrapper<vci_param_int, 168 dspin_int_cmd_width, 169 dspin_int_rsp_width>* xicu_int_wt; 170 171 VciMultiDma<vci_param_int>* mdma; 172 173 VciDspinInitiatorWrapper<vci_param_int, 174 dspin_int_cmd_width, 175 dspin_int_rsp_width>* mdma_int_wi; 176 177 VciDspinTargetWrapper<vci_param_int, 178 dspin_int_cmd_width, 179 dspin_int_rsp_width>* mdma_int_wt; 180 181 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d; 182 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d; 183 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; 184 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; 185 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; 186 187 VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd; 188 VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp; 189 190 VciSimpleRam<vci_param_ext>* xram; 191 192 VciDspinTargetWrapper<vci_param_ext, 193 dspin_ram_cmd_width, 194 dspin_ram_rsp_width>* xram_ram_wt; 195 196 DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; 197 DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; 198 199 // IO Network Components (not instanciated in all clusters) 200 201 VciIoBridge<vci_param_int, 202 vci_param_ext>* iob; 203 204 VciDspinInitiatorWrapper<vci_param_int, 205 dspin_int_cmd_width, 206 dspin_int_rsp_width>* iob_int_wi; 207 208 VciDspinTargetWrapper<vci_param_int, 209 dspin_int_cmd_width, 210 dspin_int_rsp_width>* iob_int_wt; 211 212 VciDspinInitiatorWrapper<vci_param_ext, 213 dspin_ram_cmd_width, 214 dspin_ram_rsp_width>* iob_ram_wi; 215 216 // cluster constructor 217 TsarIobCluster( sc_module_name insname, 218 size_t nb_procs, 219 size_t nb_dmas, 220 size_t x, // x coordinate 221 size_t y, // y coordinate 222 size_t xmax, 223 size_t ymax, 224 225 const soclib::common::MappingTable &mt_int, 226 const soclib::common::MappingTable &mt_ext, 227 const soclib::common::MappingTable &mt_iox, 228 229 size_t x_width, // x field bits 230 size_t y_width, // y field bits 231 size_t l_width, // l field bits 232 233 size_t int_memc_tgtid, 234 size_t int_xicu_tgtid, 235 size_t int_mdma_tgtid, 236 size_t int_iobx_tgtid, 237 238 size_t int_proc_srcid, 239 size_t int_mdma_srcid, 240 size_t int_iobx_srcid, 241 242 size_t ext_xram_tgtid, 243 244 size_t ext_memc_srcid, 245 size_t ext_iobx_srcid, 246 247 size_t memc_ways, 248 size_t memc_sets, 249 size_t l1_i_ways, 250 size_t l1_i_sets, 251 size_t l1_d_ways, 252 size_t l1_d_sets, 253 size_t xram_latency, 254 255 const Loader &loader, // loader for XRAM 256 257 uint32_t frozen_cycles, 258 uint32_t start_debug_cycle, 259 bool memc_debug_ok, 260 bool proc_debug_ok, 261 bool iob0_debug_ok ); 262 48 public: 49 50 // Ports 51 sc_in<bool> p_clk; 52 sc_in<bool> p_resetn; 53 54 // Thes two ports are used to connect IOB to IOX nework in top cell 55 soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; 56 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 57 58 // These ports are used to connect IOB to RAM network in top cell 59 soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out; 60 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in; 61 62 // These ports are used to connect hard IRQ from external peripherals to 63 // IOB0 64 sc_in<bool>* p_irq[32]; 65 66 // These arrays of ports are used to connect the INT & RAM networks in 67 // top cell 68 soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; 69 soclib::caba::DspinInput<dspin_int_cmd_width>** p_dspin_int_cmd_in; 70 soclib::caba::DspinOutput<dspin_int_rsp_width>** p_dspin_int_rsp_out; 71 soclib::caba::DspinInput<dspin_int_rsp_width>** p_dspin_int_rsp_in; 72 73 soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_ram_cmd_out; 74 soclib::caba::DspinInput<dspin_ram_cmd_width>* p_dspin_ram_cmd_in; 75 soclib::caba::DspinOutput<dspin_ram_rsp_width>* p_dspin_ram_rsp_out; 76 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_ram_rsp_in; 77 78 // interrupt signals 79 sc_signal<bool> signal_false; 80 sc_signal<bool> signal_proc_it[8]; 81 sc_signal<bool> signal_irq_mdma[8]; 82 sc_signal<bool> signal_irq_memc; 83 84 // INT network DSPIN signals between DSPIN routers and DSPIN 85 // local_crossbars 86 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 87 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 88 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 89 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 90 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 91 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 92 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 93 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 94 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 95 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 96 97 // INT network VCI signals between VCI components and VCI/DSPIN wrappers 98 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 99 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 100 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 101 102 VciSignals<vci_param_int> signal_int_vci_tgt_memc; 103 VciSignals<vci_param_int> signal_int_vci_tgt_xicu; 104 VciSignals<vci_param_int> signal_int_vci_tgt_mdma; 105 VciSignals<vci_param_int> signal_int_vci_tgt_iobx; 106 107 // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN 108 // wrappers 109 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8]; 110 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8]; 111 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i; 112 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i; 113 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i; 114 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i; 115 116 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t; 117 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t; 118 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t; 119 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t; 120 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t; 121 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t; 122 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t; 123 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t; 124 125 // Coherence DSPIN signals between DSPIN local crossbars and CC 126 // components 127 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; 128 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; 129 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc; 130 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8]; 131 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8]; 132 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8]; 133 134 // RAM network VCI signals between VCI components and VCI/DSPIN wrappers 135 VciSignals<vci_param_ext> signal_ram_vci_ini_memc; 136 VciSignals<vci_param_ext> signal_ram_vci_ini_iobx; 137 VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; 138 139 // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 140 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 141 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; 142 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; 143 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; 144 145 ////////////////////////////////////// 146 // Hardwate Components (pointers) 147 ////////////////////////////////////// 148 typedef VciCcVCacheWrapper<vci_param_int, dspin_int_cmd_width, 149 dspin_int_rsp_width, GdbServer<Mips32ElIss> > 150 VciCcVCacheWrapperType; 151 152 typedef VciMemCache<vci_param_int, vci_param_ext, dspin_int_rsp_width, 153 dspin_int_cmd_width> VciMemCacheType; 154 155 typedef VciDspinInitiatorWrapper<vci_param_int, dspin_int_cmd_width, 156 dspin_int_rsp_width> VciIntDspinInitiatorWrapperType; 157 158 typedef VciDspinTargetWrapper<vci_param_int, dspin_int_cmd_width, 159 dspin_int_rsp_width> VciIntDspinTargetWrapperType; 160 161 typedef VciDspinInitiatorWrapper<vci_param_ext, dspin_ram_cmd_width, 162 dspin_ram_rsp_width> VciExtDspinInitiatorWrapperType; 163 164 typedef VciDspinTargetWrapper<vci_param_ext, dspin_ram_cmd_width, 165 dspin_ram_rsp_width> VciExtDspinTargetWrapperType; 166 167 VciCcVCacheWrapperType* proc[8]; 168 VciIntDspinInitiatorWrapperType* proc_wi[8]; 169 170 VciMemCacheType* memc; 171 VciIntDspinTargetWrapperType* memc_int_wt; 172 VciExtDspinInitiatorWrapperType* memc_ram_wi; 173 174 VciXicu<vci_param_int>* xicu; 175 VciIntDspinTargetWrapperType* xicu_int_wt; 176 177 VciMultiDma<vci_param_int>* mdma; 178 VciIntDspinInitiatorWrapperType* mdma_int_wi; 179 VciIntDspinTargetWrapperType* mdma_int_wt; 180 181 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d; 182 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d; 183 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; 184 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; 185 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_clack_c; 186 187 VirtualDspinRouter<dspin_int_cmd_width>* int_router_cmd; 188 VirtualDspinRouter<dspin_int_rsp_width>* int_router_rsp; 189 190 VciSimpleRam<vci_param_ext>* xram; 191 VciExtDspinTargetWrapperType* xram_ram_wt; 192 193 DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; 194 DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; 195 196 // IO Network Components (not instanciated in all clusters) 197 198 VciIoBridge<vci_param_int, vci_param_ext>* iob; 199 VciIntDspinInitiatorWrapperType* iob_int_wi; 200 VciIntDspinTargetWrapperType* iob_int_wt; 201 VciExtDspinInitiatorWrapperType* iob_ram_wi; 202 203 size_t m_procs; 204 205 struct ClusterParams { 206 sc_module_name insname; 207 208 size_t nb_procs; 209 size_t nb_dmas; 210 size_t x_id; 211 size_t y_id; 212 size_t x_size; 213 size_t y_size; 214 215 const soclib::common::MappingTable &mt_int; 216 const soclib::common::MappingTable &mt_ext; 217 const soclib::common::MappingTable &mt_iox; 218 219 size_t x_width; 220 size_t y_width; 221 size_t l_width; 222 223 size_t int_memc_tgtid; 224 size_t int_xicu_tgtid; 225 size_t int_mdma_tgtid; 226 size_t int_iobx_tgtid; 227 size_t int_proc_srcid; 228 size_t int_mdma_srcid; 229 size_t int_iobx_srcid; 230 size_t ext_xram_tgtid; 231 size_t ext_memc_srcid; 232 size_t ext_iobx_srcid; 233 234 size_t memc_ways; 235 size_t memc_sets; 236 size_t l1_i_ways; 237 size_t l1_i_sets; 238 size_t l1_d_ways; 239 size_t l1_d_sets; 240 size_t xram_latency; 241 242 const Loader& loader; 243 244 uint32_t frozen_cycles; 245 uint32_t debug_start_cycle; 246 bool memc_debug_ok; 247 bool proc_debug_ok; 248 bool iob_debug_ok; 249 }; 250 251 // cluster constructor 252 TsarIobCluster(struct ClusterParams& params); 253 ~TsarIobCluster(); 263 254 }; 264 255 … … 266 257 267 258 #endif 259 260 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
Note: See TracChangeset
for help on using the changeset viewer.