Changeset 653 for trunk/softs
- Timestamp:
- Mar 3, 2014, 5:11:06 PM (11 years ago)
- Location:
- trunk/softs/tsar_boot
- Files:
-
- 1 deleted
- 13 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/softs/tsar_boot/Makefile
r587 r653 9 9 else 10 10 ifdef SOCLIB 11 DEFS+= -DSOCLIB_IOC 11 ifdef RAMDISK 12 DEFS+= -DUSE_RDK 13 else 14 DEFS+= -DUSE_BDV 15 endif 12 16 DTS=platform_soclib.dts 13 17 $(info Make for $(PLATFORM_DIR), SocLib variant) 14 18 else 19 DEFS+= -DUSE_SPI 15 20 DTS=platform_fpga.dts 16 21 $(info Make for $(PLATFORM_DIR), FPGA variant) … … 19 24 endif 20 25 21 LD 22 CC 23 AS 24 DU 25 RM 26 ECHO :=echo27 MKDIR 28 DTC 29 HEXDUMP 26 LD := mipsel-unknown-elf-ld 27 CC := mipsel-unknown-elf-gcc 28 AS := mipsel-unknown-elf-as 29 DU := mipsel-unknown-elf-objdump 30 RM := rm -rf 31 ECHO := @echo 32 MKDIR := mkdir 33 DTC := dtc 34 HEXDUMP := hexdump 30 35 DOXYGEN := doxygen 31 36 … … 38 43 # ============================================================================= 39 44 40 INCLUDE 45 INCLUDE += -I. -I$(INCS_DIR) -I$(PLATFORM_DIR) 41 46 42 47 # ============================================================================= … … 56 61 -fomit-frame-pointer \ 57 62 -mips32 \ 58 63 -ggdb \ 59 64 -mlong-calls \ 60 65 -Werror 61 66 62 C_SRCS 67 C_SRCS := reset_elf_loader.c \ 63 68 reset_ioc.c \ 64 69 reset_utils.c \ … … 70 75 endif 71 76 72 S_SRCS 77 S_SRCS := reset.S 73 78 74 79 OBJS := $(subst .c,.o, $(notdir $(C_SRCS))) … … 78 83 TARGET := preloader.elf 79 84 80 USE_DT 85 USE_DT ?= 1 81 86 82 87 all: $(TARGET) … … 135 140 $(DU) -D $@ > $@.txt 136 141 137 .SILENT:142 #.SILENT: -
trunk/softs/tsar_boot/README.txt
r568 r653 34 34 This constant defines the size in bytes of a cache line. 35 35 36 -> BOOT_DEBUG36 -> RESET_DEBUG 37 37 Set value to 1 to show some debug messages during loading 38 39 -> BOOT_DEBUG_IOC40 Set value to 1 to show some debug messages during loading41 concerning the disk accesses.42 38 43 39 -> IRQ_PER_PROC … … 76 72 ---> SOCLIB=1 77 73 78 If using SOCLIB, define this flag to use the SOCLIB device 79 drivers 74 If using SOCLIB, define this flag to use the BLOCK DEVICE 75 driver and to choose the platform_soclib device tree. 76 77 ---> RAMDISK=1 78 79 If using SOCLIB, define this flag to use a RAMDISK instead 80 of BLOCK DEVICE (Set this flag when the SOCLIB flag is also set) 80 81 81 82 ---> USE_DT=0 -
trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h
r568 r653 8 8 #define CACHE_LINE_SIZE 64//bytes 9 9 10 #define BOOT_DEBUG 1 11 #define BOOT_DEBUG_IOC 0 10 #define RESET_DEBUG 0 12 11 13 #define IOC_BASE 0xFB000000 14 #define TTY_BASE 0xFC000000 15 #define ICU_BASE 0xFD000000 16 #define MCC_BASE 0xFFFFFFFF // not used 12 #define ICU_PADDR_BASE 0xFD000000 13 #define MCC_PADDR_BASE 0xFFFFFFFF // not used 14 #define IOC_PADDR_BASE 0xFB000000 15 #define TTY_PADDR_BASE 0xFC000000 16 #define RDK_PADDR_BASE 0xFFFFFFFF // not used 17 17 18 18 /* Mandatory argument only for FPGA platforms */ -
trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript
r563 r653 5 5 **********************************************************/ 6 6 7 /* Definition of the base address for all segments*/7 /* Definition of the base address for code segment */ 8 8 9 seg_stack_base = 0x08000000 - 0x4000; 10 seg_boot_base = 0xBFC00000; /* le code de boot */ 9 seg_reset_code_base = 0xBFC00000; 10 11 seg_reset_stack_base = 0x08000000 - 0x4000;; 12 seg_reset_stack_size = 0x4000; 11 13 12 14 /* Grouping sections into segments */ 13 15 14 ENTRY(boot) 16 ENTRY(reset) 17 15 18 SECTIONS 16 19 { 17 . = seg_ boot_base;18 .text : {19 *(.boot)20 . = seg_reset_code_base; 21 .text : 22 { 20 23 *(.reset) 21 22 23 24 25 24 *(.rodata) 25 *(.rodata.*) 26 . = ALIGN(0x4); 27 dtb_addr = .; 28 INCLUDE "build/platform.ld"; 26 29 } 27 30 28 . = seg_stack_base; 29 .bss ALIGN(0x4) (NOLOAD) : { 31 . = seg_reset_stack_base; 32 .bss ALIGN(0x4) (NOLOAD) : 33 { 30 34 *(.data) 31 35 *(.bss) -
trunk/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h
r586 r653 6 6 #define USE_IOB 1 7 7 #define CACHE_COHERENCE 1 8 #define CACHE_LINE_SIZE 64 // bytes 9 8 #define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) 10 9 #define RESET_DEBUG 0 11 10 … … 14 13 #define IOC_PADDR_BASE 0xB3000000 15 14 #define TTY_PADDR_BASE 0xB4000000 15 #define RDK_PADDR_BASE 0xFFFFFFFF // not used -
trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h
r568 r653 1 #define NB_PROCS 12 #define NB_CLUSTERS 11 #define NB_PROCS 1 2 #define NB_CLUSTERS 1 3 3 4 #define IRQ_PER_PROC 14 #define IRQ_PER_PROC 1 5 5 6 #define USE_IOB 0 7 #define CACHE_COHERENCE 1 8 #define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) 6 #define USE_IOB 0 7 #define CACHE_COHERENCE 1 8 #define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) 9 #define RESET_DEBUG 0 9 10 10 #define BOOT_DEBUG 1 11 #define BOOT_DEBUG_IOC 0 12 13 #define TTY_BASE 0x20000000 14 #define ICU_BASE 0x30000000 15 #define IOC_BASE 0x40000000 16 #define MCC_BASE 0xFFFFFFFF // not used 11 #define TTY_PADDR_BASE 0x20000000 12 #define ICU_PADDR_BASE 0x30000000 13 #define IOC_PADDR_BASE 0x40000000 14 #define MCC_PADDR_BASE 0xFFFFFFFF // not used 15 #define RDK_PADDR_BASE 0xFFFFFFFF // not used -
trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript
r563 r653 5 5 **********************************************************/ 6 6 7 /* Definition of the base address for all segments*/7 /* Definition of the base address for code segment */ 8 8 9 seg_stack_base = 0x10000000 - 0x8000 - 0x4; 10 seg_boot_base = 0xBFC00000; /* le code de boot */ 9 seg_reset_boot_base = 0xBFC00000; /* le code de boot */ 10 11 seg_reset_stack_base = 0x10000000 - 0x8000 - 0x4; 12 seg_reset_stack_base = 0x00008000; 11 13 12 14 /* Grouping sections into segments */ 13 15 14 ENTRY(boot) 16 ENTRY(reset) 17 15 18 SECTIONS 16 19 { 17 . = seg_ boot_base;18 .text : {19 *(.boot)20 . = seg_reset_code_base; 21 .text : 22 { 20 23 *(.reset) 21 22 23 24 25 24 *(.rodata) 25 *(.rodata.*) 26 . = ALIGN(0x4); 27 dtb_addr = .; 28 INCLUDE "build/platform.ld"; 26 29 } 27 30 28 . = seg_stack_base; 29 .bss ALIGN(0x4) (NOLOAD) : { 31 . = seg_reset_stack_base; 32 .bss ALIGN(0x4) (NOLOAD) : 33 { 30 34 *(.data) 31 35 *(.bss) -
trunk/softs/tsar_boot/include/io.h
r292 r653 39 39 { 40 40 *(volatile unsigned int *) addr = value; 41 asm volatile("sync" );41 asm volatile("sync" ::: "memory"); 42 42 } 43 43 … … 48 48 { 49 49 *(volatile unsigned short *) addr = value; 50 asm volatile("sync" );50 asm volatile("sync" ::: "memory"); 51 51 } 52 52 … … 57 57 { 58 58 *(volatile unsigned char *) addr = value; 59 asm volatile("sync" );59 asm volatile("sync" ::: "memory"); 60 60 } 61 61 -
trunk/softs/tsar_boot/include/reset_ioc.h
r586 r653 2 2 #define RESET_IOC_H 3 3 4 #if ndef SOCLIB_IOC4 #if USE_SPI 5 5 #include <sdcard.h> 6 6 #include <spi.h> 7 #else 7 #endif /* USE_SPI */ 8 9 #if USE_BDV 8 10 #include <block_device.h> 9 11 #include <mcc.h> 10 #endif 12 #endif /* USE_BDV */ 11 13 12 14 #include <defs.h> 13 15 #include <reset_tty.h> 14 16 #include <io.h> 17 #include <reset_utils.h> 15 18 19 #if USE_SPI 16 20 extern int reset_ioc_init(); 21 #endif /* USE_SPI */ 17 22 18 23 extern int reset_ioc_read( unsigned int lba, … … 20 25 unsigned int count ); 21 26 22 extern int reset_ioc_completed(); 23 24 extern void reset_buf_invalidate ( const void * buffer, 25 unsigned int line_size, 26 unsigned int size ); 27 28 extern void reset_mcc_invalidate( const void * buffer, 29 unsigned int size ); 30 #endif 27 #endif /* RESET_IOC_H */ 31 28 32 29 /* -
trunk/softs/tsar_boot/include/reset_utils.h
r586 r653 19 19 extern void reset_print_elf_phdr(Elf32_Phdr * elf_phdr_ptr); 20 20 21 #endif 21 #if USE_IOB 22 void reset_mcc_invalidate ( const void * buffer, 23 unsigned int size); 24 #endif /* USE_IOB */ 25 26 #if (CACHE_COHERENCE == 0) || USE_IOB 27 void reset_buf_invalidate ( const void * buffer, 28 unsigned int line_size, 29 unsigned int size); 30 #endif /* (CACHE_COHERENCE == 0) || USE_IOB */ 31 #endif /* BOOT_UTILS_H */ 22 32 23 33 // vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab -
trunk/softs/tsar_boot/src/reset.S
r634 r653 159 159 160 160 161 #if ndef SOCLIB_IOC162 163 /* Processor 0 Initialize the block device if required*/161 #if USE_SPI 162 163 /* Processor 0 Initialize the SPI controller */ 164 164 165 165 la k0, reset_ioc_init -
trunk/softs/tsar_boot/src/reset_ioc.c
r588 r653 1 1 #include <reset_ioc.h> 2 2 3 #ifndef SOCLIB_IOC 4 5 static struct sdcard_dev _sdcard_device; 6 static struct spi_dev *const _spi_device = ( struct spi_dev * )IOC_PADDR_BASE; 7 3 #if USE_SPI 4 static struct sdcard_dev _sdcard_device; 5 static struct spi_dev *const _spi_device = (struct spi_dev*) IOC_PADDR_BASE; 8 6 #endif 9 7 … … 17 15 } 18 16 19 #if RESET_DEBUG 20 //////////////////////////////////// 21 inline unsigned int reset_proctime() 22 { 23 unsigned int ret; 24 asm volatile ("mfc0 %0, $9":"=r" (ret)); 25 return ret; 26 } 27 #endif 28 29 #ifndef SOCLIB_IOC 30 ///////////////////////////////////////////////////////////////////////////////// 17 #if USE_SPI 18 /////////////////////////////////////////////////////////////////////////////// 31 19 // reset_ioc_init 32 20 // This function initializes the SDCARD / required for FPGA. 33 /////////////////////////////////////////////////////////////////////////////// //21 /////////////////////////////////////////////////////////////////////////////// 34 22 int reset_ioc_init() 35 23 { … … 105 93 #endif 106 94 107 #ifdef SOCLIB_IOC 108 ///////////////////////////////////////////////////////////////////////////////////// 109 // reset_ioc_completed() 110 // This blocking function checks completion of an I/O transfer and reports errors. 111 // It returns 0 if the transfer is successfully completed. 112 // It returns -1 if an error has been reported. 113 ///////////////////////////////////////////////////////////////////////////////////// 114 int reset_ioc_completed() 115 { 95 ////////////////////////////////////////////////////////////////////////////// 96 // reset_bdv_read() 97 ///////////////////////////////////////////////////////////////////////////// 98 #if USE_BDV 99 int reset_bdv_read( unsigned int lba, 100 void* buffer, 101 unsigned int count ) 102 { 103 unsigned int * ioc_address = (unsigned int*)IOC_PADDR_BASE; 104 105 // block_device configuration 106 iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], (unsigned int) buffer ); 107 iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], count ); 108 iowrite32( &ioc_address[BLOCK_DEVICE_LBA], lba ); 109 iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE], 0 ); 110 111 // block_device trigger transfer 112 iowrite32( &ioc_address[BLOCK_DEVICE_OP], ( unsigned int ) 113 BLOCK_DEVICE_READ ); 114 116 115 unsigned int status = 0; 117 118 unsigned int * ioc_address = ( unsigned int * )IOC_PADDR_BASE;119 120 116 while ( 1 ) 121 117 { 122 118 status = ioread32(&ioc_address[BLOCK_DEVICE_STATUS]); 123 124 if (( status == BLOCK_DEVICE_READ_SUCCESS ) || 125 ( status == BLOCK_DEVICE_READ_ERROR )) 126 break; 127 } 128 129 return status; 130 } // end reset_ioc_completed() 131 #endif 132 133 #ifdef SOCLIB_IOC 134 ///////////////////////////////////////////////////////////////////////////////////// 119 if ( status == BLOCK_DEVICE_READ_SUCCESS ) 120 { 121 break; 122 } 123 if ( status == BLOCK_DEVICE_READ_ERROR ) { 124 reset_puts("ERROR during read on the BLK device\n"); 125 return 1; 126 } 127 } 128 #if (CACHE_COHERENCE == 0) || USE_IOB 129 reset_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); 130 #endif 131 return 0; 132 } 133 #endif 134 135 ////////////////////////////////////////////////////////////////////////////// 136 // reset_spi_read() 137 ///////////////////////////////////////////////////////////////////////////// 138 #if USE_SPI 139 static int reset_spi_read( unsigned int lba, 140 void* buffer, 141 unsigned int count ) 142 { 143 unsigned int sdcard_rsp; 144 unsigned int i; 145 146 sdcard_dev_lseek(&_sdcard_device, lba); 147 for(i = 0; i < count; i++) 148 { 149 unsigned char* buf = (unsigned char *) buffer + (512 * i); 150 if (( sdcard_rsp = sdcard_dev_read ( &_sdcard_device, buf, 512 ) )) 151 { 152 reset_puts("ERROR during read on the SDCARD device. Code: "); 153 reset_putx(sdcard_rsp); 154 reset_puts("\n"); 155 return 1; 156 } 157 } 158 return 0; 159 } 160 #endif 161 162 ////////////////////////////////////////////////////////////////////////////// 163 // reset_rdk_read() 164 ///////////////////////////////////////////////////////////////////////////// 165 #if USE_RDK 166 static int reset_rdk_read( unsigned int lba, 167 void* buffer, 168 unsigned int count ) 169 { 170 unsigned int* rdk_address = (unsigned int*) RDK_PADDR_BASE; 171 char* src = (char*) rdk_address + (lba * 512); 172 173 memcpy(buffer, (void*) src, count * 512); 174 return 0; 175 } 176 #endif 177 178 /////////////////////////////////////////////////////////////////////////////// 135 179 // reset_ioc_read() 136 // Transfer data the block device to a memory buffer: SOCLIB version180 // Transfer data from disk to a memory buffer 137 181 // - param lba : first block index on the disk 138 182 // - param buffer : base address of the memory buffer 139 183 // - param count : number of blocks to be transfered 140 // This is a blocking function. The function returns once the transfer is completed. 141 ///////////////////////////////////////////////////////////////////////////////////// 184 // This is a blocking function. The function returns once the transfer is 185 // completed. 186 // 187 // The USE_BDV, USE_SPI and USE_RDK variables signal if the disk is accessed 188 // through a BLOCK DEVICE, SPI or RAMDISK respectively 189 /////////////////////////////////////////////////////////////////////////////// 142 190 int reset_ioc_read( unsigned int lba, 143 191 void* buffer, 144 192 unsigned int count ) 145 193 { 146 147 unsigned int * ioc_address = (unsigned int*)IOC_PADDR_BASE; 148 149 #if RESET_DEBUG 150 unsigned int start_time; 151 unsigned int end_time; 152 reset_puts("[RESET DEBUG] Reading blocks "); 153 reset_putd(lba); 154 reset_puts(" to "); 155 reset_putd(lba + count - 1); 156 157 start_time = reset_proctime(); 158 #endif 159 160 // block_device configuration 161 iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], 162 ( unsigned int ) buffer ); 163 164 iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], 165 ( unsigned int ) count ); 166 167 iowrite32( &ioc_address[BLOCK_DEVICE_LBA], 168 ( unsigned int ) lba ); 169 170 iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE], 171 ( unsigned int ) 0 ); 172 173 iowrite32( &ioc_address[BLOCK_DEVICE_OP], 174 ( unsigned int ) BLOCK_DEVICE_READ ); 175 176 reset_ioc_completed(); 177 178 #if (CACHE_COHERENCE == 0) || (USE_IOB == 1) 179 reset_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); 180 #endif 181 182 #if USE_IOB 183 reset_mcc_invalidate(buffer, count * 512); 184 #endif 185 186 #if RESET_DEBUG 187 end_time = reset_proctime(); 188 reset_puts(" / cycles for transfert: "); 189 reset_putd(end_time - start_time); 190 reset_puts("\n"); 191 #endif 192 193 return 0; 194 } // end reset_ioc_read() 195 196 #else 197 198 ///////////////////////////////////////////////////////////////////////////////////// 199 // reset_ioc_read() 200 // Transfer data the block device to a memory buffer: FPGA version 201 // - param lba : first block index on the disk 202 // - param buffer : base address of the memory buffer 203 // - param count : number of blocks to be transfered 204 // This is a blocking function. The function returns once the transfer is completed. 205 ///////////////////////////////////////////////////////////////////////////////////// 206 int reset_ioc_read( unsigned int lba, 207 void* buffer, 208 unsigned int count ) 209 { 210 unsigned int sdcard_rsp; 211 unsigned int i; 212 213 sdcard_dev_lseek(&_sdcard_device, lba); 214 215 #if RESET_DEBUG 216 unsigned int start_time; 217 unsigned int end_time; 218 reset_puts("[RESET DEBUG] Reading blocks "); 219 reset_putd(lba); 220 reset_puts(" to "); 221 reset_putd(lba + count - 1); 222 start_time = reset_proctime(); 223 #endif 224 225 for(i = 0; i < count; i++) 226 { 227 if (( sdcard_rsp = sdcard_dev_read ( 228 &_sdcard_device, 229 (unsigned char *) buffer + (512 * i), 230 512 231 ) 232 )) 233 { 234 reset_puts("ERROR during read on the SDCARD device. Code: "); 235 reset_putx(sdcard_rsp); 236 reset_puts("\n\r"); 237 238 return 1; 239 } 240 } 241 242 #if RESET_DEBUG 243 end_time = reset_proctime(); 244 reset_puts(" / cycles for transfert: "); 245 reset_putd(end_time - start_time); 246 reset_puts("\n"); 247 #endif 248 249 return 0; 250 } // end reset_ioc_read() 251 #endif 252 253 ////////////////////////////////////////////////////////////////////////////// 254 // reset_dcache_buf_invalidate() 255 // Invalidate all data cache lines corresponding to a memory buffer 256 // (identified by an address and a size) in L1 cache. 257 ///////////////////////////////////////////////////////////////////////////// 258 #if (CACHE_COHERENCE == 0) || (USE_IOB == 1) 259 void reset_buf_invalidate ( const void * buffer, 260 unsigned int line_size, 261 unsigned int size) 262 { 263 unsigned int i; 264 265 // iterate on cache lines 266 for (i = 0; i <= size; i += line_size) 267 { 268 asm volatile( 269 " cache %0, %1" 270 :// no outputs 271 :"i" (0x11), "R" (*((unsigned char *) buffer + i)) 272 ); 273 } 274 } 275 #endif 276 277 ////////////////////////////////////////////////////////////////////////////// 278 // reset_mcc_inval() 279 // Invalidate all data cache lines corresponding to a memory buffer 280 // (identified by an address and a size) in L2 cache. 281 ///////////////////////////////////////////////////////////////////////////// 282 #if USE_IOB 283 void reset_mcc_invalidate ( const void * buffer, 284 unsigned int size) 285 { 286 unsigned int * mcc_address = (unsigned int *)MCC_PADDR_BASE; 287 288 // get the hard lock assuring exclusive access to MEMC 289 while (ioread32(&mcc_address[MCC_LOCK])); 290 291 // write invalidate paremeters on the memory cache 292 // this preloader use only the cluster 0 and then the HI bits are not used 293 294 iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer); 295 iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0); 296 iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size); 297 iowrite32(&mcc_address[MCC_CMD] , (unsigned int) MCC_CMD_INVAL); 298 299 // release the lock protecting MEMC 300 iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0); 301 } 302 #endif 194 int status; 195 #if USE_BDV 196 status = reset_bdv_read(lba, buffer, count); 197 #endif 198 #if USE_SPI 199 status = reset_spi_read(lba, buffer, count); 200 #endif 201 #if USE_RDK 202 status = reset_rdk_read(lba, buffer, count); 203 #endif 204 return status; 205 } 303 206 304 207 /* -
trunk/softs/tsar_boot/src/reset_utils.c
r586 r653 9 9 #include <reset_utils.h> 10 10 11 /***************************************** 11 /******************************************************************** 12 12 * proctime() 13 13 * 14 14 * Returns processor local time. 15 **************************************** /15 ********************************************************************/ 16 16 inline unsigned int proctime() 17 17 { … … 21 21 } 22 22 23 /***************************************** 23 /******************************************************************** 24 24 * memcpy( _dst, _src, size ) 25 25 * … … 30 30 * \param size : Number of bytes to transfer 31 31 * 32 **************************************** /32 ********************************************************************/ 33 33 void * memcpy(void *_dst, const void *_src, unsigned int size) 34 34 { … … 52 52 } 53 53 54 /***************************************** 54 /******************************************************************** 55 55 * memset( _dst, value, size ) 56 56 * … … 61 61 * \param size : Number of bytes to initialize 62 62 * 63 **************************************** /63 ********************************************************************/ 64 64 void * memset(void *_dst, const int value, unsigned int size) 65 65 { … … 71 71 } 72 72 73 /***************************************** 73 /******************************************************************** 74 74 * reset_print_elf_phdr( elf_phdr_ptr ) 75 75 * … … 78 78 * \param elf_phdr_ptr : Pointer to the ELF program header to print 79 79 * 80 **************************************** /80 ********************************************************************/ 81 81 void reset_print_elf_phdr(Elf32_Phdr * elf_phdr_ptr) 82 82 { … … 106 106 } 107 107 108 109 /******************************************************************** 110 * reset_mcc_inval() 111 * 112 * Invalidate all data cache lines corresponding to a memory buffer 113 * (identified by an address and a size) in L2 cache. 114 ********************************************************************/ 115 #if USE_IOB 116 void reset_mcc_invalidate ( const void * buffer, 117 unsigned int size) 118 { 119 unsigned int * mcc_address = (unsigned int *)MCC_PADDR_BASE; 120 121 // get the hard lock assuring exclusive access to MEMC 122 while (ioread32(&mcc_address[MCC_LOCK])); 123 124 // write invalidate paremeters on the memory cache this preloader 125 // use only the cluster 0 and then the HI bits are not used 126 127 iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer); 128 iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0); 129 iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size); 130 iowrite32(&mcc_address[MCC_CMD] , (unsigned int) MCC_CMD_INVAL); 131 132 // release the lock protecting MEMC 133 iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0); 134 } 135 #endif 136 137 /******************************************************************** 138 * reset_dcache_buf_invalidate() 139 * 140 * Invalidate all data cache lines corresponding to a memory buffer 141 * (identified by an address and a size) in L1 cache and L2 cache. 142 ********************************************************************/ 143 #if (CACHE_COHERENCE == 0) || USE_IOB 144 void reset_buf_invalidate ( const void * buffer, 145 unsigned int line_size, 146 unsigned int size) 147 { 148 unsigned int i; 149 150 // iterate on cache lines 151 for (i = 0; i <= size; i += line_size) 152 { 153 asm volatile( 154 " cache %0, %1" 155 :// no outputs 156 :"i" (0x11), "R" (*((unsigned char *) buffer + i)) 157 ); 158 } 159 160 #if USE_IOB 161 reset_mcc_invalidate(buffer, count * 512); 162 #endif 163 } 164 #endif 165 108 166 // vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab
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