Ignore:
Timestamp:
Mar 3, 2014, 5:11:06 PM (11 years ago)
Author:
cfuguet
Message:

Introducing a RAMDISK driver in the preloader.

When using RAMDISK, execute the make command with the flags
SOCLIB=1 and RAMDISK=1. The RDK_PADDR_BASE variable must
also be set on the conf/<platform>/defs_platform.h

These modifications are backward compatibles. Therefore,
when no using RAMDISK, none modifications applied on the
platform configuration file.

Location:
trunk/softs/tsar_boot/conf
Files:
1 deleted
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h

    r568 r653  
    88#define CACHE_LINE_SIZE 64//bytes
    99
    10 #define BOOT_DEBUG      1
    11 #define BOOT_DEBUG_IOC  0
     10#define RESET_DEBUG     0
    1211
    13 #define IOC_BASE        0xFB000000
    14 #define TTY_BASE        0xFC000000
    15 #define ICU_BASE        0xFD000000
    16 #define MCC_BASE        0xFFFFFFFF // not used
     12#define ICU_PADDR_BASE  0xFD000000
     13#define MCC_PADDR_BASE  0xFFFFFFFF // not used
     14#define IOC_PADDR_BASE  0xFB000000
     15#define TTY_PADDR_BASE  0xFC000000
     16#define RDK_PADDR_BASE  0xFFFFFFFF // not used
    1717
    1818/* Mandatory argument only for FPGA platforms */

  • trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript

    r563 r653  
    55**********************************************************/
    66
    7 /* Definition of the base address for all segments */
     7/* Definition of the base address for code segment */
    88
    9 seg_stack_base    = 0x08000000 - 0x4000;
    10 seg_boot_base     = 0xBFC00000;       /* le code de boot */
     9seg_reset_code_base     = 0xBFC00000;
     10
     11seg_reset_stack_base    = 0x08000000 - 0x4000;;
     12seg_reset_stack_size    = 0x4000;
    1113
    1214/* Grouping sections into segments */
    1315
    14 ENTRY(boot)
     16ENTRY(reset)
     17
    1518SECTIONS
    1619{
    17     . = seg_boot_base;
    18     .text : {
    19         *(.boot)
     20    . = seg_reset_code_base;
     21    .text :
     22    {
    2023        *(.reset)
    21         *(.rodata)
    22         *(.rodata.*)
    23         . = ALIGN(0x4);
    24         dtb_addr = .;
    25         INCLUDE "build/platform.ld";
     24        *(.rodata)
     25        *(.rodata.*)
     26        . = ALIGN(0x4);
     27        dtb_addr = .;
     28        INCLUDE "build/platform.ld";
    2629    }
    2730
    28     . = seg_stack_base;
    29     .bss ALIGN(0x4) (NOLOAD) : {
     31    . = seg_reset_stack_base;
     32    .bss ALIGN(0x4) (NOLOAD) :
     33    {
    3034        *(.data)
    3135        *(.bss)

  • trunk/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h

    r586 r653  
    66#define USE_IOB          1
    77#define CACHE_COHERENCE  1
    8 #define CACHE_LINE_SIZE  64   //  bytes
    9 
     8#define CACHE_LINE_SIZE  64 // bytes (ie 16 x 32-bit word)
    109#define RESET_DEBUG      0
    1110
    … …  
    1413#define IOC_PADDR_BASE   0xB3000000
    1514#define TTY_PADDR_BASE   0xB4000000
     15#define RDK_PADDR_BASE   0xFFFFFFFF // not used

  • trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h

    r568 r653  
    1 #define NB_PROCS        1
    2 #define NB_CLUSTERS     1
     1#define NB_PROCS         1
     2#define NB_CLUSTERS      1
    33
    4 #define IRQ_PER_PROC    1
     4#define IRQ_PER_PROC     1
    55
    6 #define USE_IOB         0
    7 #define CACHE_COHERENCE 1
    8 #define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word)
     6#define USE_IOB          0
     7#define CACHE_COHERENCE  1
     8#define CACHE_LINE_SIZE  64 // bytes (ie 16 x 32-bit word)
     9#define RESET_DEBUG      0
    910
    10 #define BOOT_DEBUG      1
    11 #define BOOT_DEBUG_IOC  0
    12 
    13 #define TTY_BASE        0x20000000
    14 #define ICU_BASE        0x30000000
    15 #define IOC_BASE        0x40000000
    16 #define MCC_BASE        0xFFFFFFFF // not used
     11#define TTY_PADDR_BASE   0x20000000
     12#define ICU_PADDR_BASE   0x30000000
     13#define IOC_PADDR_BASE   0x40000000
     14#define MCC_PADDR_BASE   0xFFFFFFFF // not used
     15#define RDK_PADDR_BASE   0xFFFFFFFF // not used

  • trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript

    r563 r653  
    55**********************************************************/
    66
    7 /* Definition of the base address for all segments */
     7/* Definition of the base address for code segment */
    88
    9 seg_stack_base    = 0x10000000 - 0x8000 - 0x4;
    10 seg_boot_base     = 0xBFC00000;       /* le code de boot */
     9seg_reset_boot_base     = 0xBFC00000;       /* le code de boot */
     10
     11seg_reset_stack_base    = 0x10000000 - 0x8000 - 0x4;
     12seg_reset_stack_base    = 0x00008000;
    1113
    1214/* Grouping sections into segments */
    1315
    14 ENTRY(boot)
     16ENTRY(reset)
     17
    1518SECTIONS
    1619{
    17     . = seg_boot_base;
    18     .text : {
    19         *(.boot)
     20    . = seg_reset_code_base;
     21    .text :
     22    {
    2023        *(.reset)
    21         *(.rodata)
    22         *(.rodata.*)
    23         . = ALIGN(0x4);
    24         dtb_addr = .;
    25         INCLUDE "build/platform.ld";
     24        *(.rodata)
     25        *(.rodata.*)
     26        . = ALIGN(0x4);
     27        dtb_addr = .;
     28        INCLUDE "build/platform.ld";
    2629    }
    2730
    28     . = seg_stack_base;
    29     .bss ALIGN(0x4) (NOLOAD) : {
     31    . = seg_reset_stack_base;
     32    .bss ALIGN(0x4) (NOLOAD) :
     33    {
    3034        *(.data)
    3135        *(.bss)
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