Index: /trunk/softs/tsar_boot/Makefile =================================================================== --- /trunk/softs/tsar_boot/Makefile (revision 652) +++ /trunk/softs/tsar_boot/Makefile (revision 653) @@ -9,8 +9,13 @@ else ifdef SOCLIB - DEFS+= -DSOCLIB_IOC + ifdef RAMDISK + DEFS+= -DUSE_RDK + else + DEFS+= -DUSE_BDV + endif DTS=platform_soclib.dts $(info Make for $(PLATFORM_DIR), SocLib variant) else + DEFS+= -DUSE_SPI DTS=platform_fpga.dts $(info Make for $(PLATFORM_DIR), FPGA variant) @@ -19,13 +24,13 @@ endif -LD := mipsel-unknown-elf-ld -CC := mipsel-unknown-elf-gcc -AS := mipsel-unknown-elf-as -DU := mipsel-unknown-elf-objdump -RM := rm -rf -ECHO := echo -MKDIR := mkdir -DTC := dtc -HEXDUMP := hexdump +LD := mipsel-unknown-elf-ld +CC := mipsel-unknown-elf-gcc +AS := mipsel-unknown-elf-as +DU := mipsel-unknown-elf-objdump +RM := rm -rf +ECHO := @echo +MKDIR := mkdir +DTC := dtc +HEXDUMP := hexdump DOXYGEN := doxygen @@ -38,5 +43,5 @@ # ============================================================================= -INCLUDE += -I. -I$(INCS_DIR) -I$(PLATFORM_DIR) +INCLUDE += -I. -I$(INCS_DIR) -I$(PLATFORM_DIR) # ============================================================================= @@ -56,9 +61,9 @@ -fomit-frame-pointer \ -mips32 \ - -ggdb \ + -ggdb \ -mlong-calls \ -Werror -C_SRCS := reset_elf_loader.c \ +C_SRCS := reset_elf_loader.c \ reset_ioc.c \ reset_utils.c \ @@ -70,5 +75,5 @@ endif -S_SRCS := reset.S +S_SRCS := reset.S OBJS := $(subst .c,.o, $(notdir $(C_SRCS))) @@ -78,5 +83,5 @@ TARGET := preloader.elf -USE_DT ?= 1 +USE_DT ?= 1 all: $(TARGET) @@ -135,3 +140,3 @@ $(DU) -D $@ > $@.txt -.SILENT: +#.SILENT: Index: /trunk/softs/tsar_boot/README.txt =================================================================== --- /trunk/softs/tsar_boot/README.txt (revision 652) +++ /trunk/softs/tsar_boot/README.txt (revision 653) @@ -34,10 +34,6 @@ This constant defines the size in bytes of a cache line. - -> BOOT_DEBUG + -> RESET_DEBUG Set value to 1 to show some debug messages during loading - - -> BOOT_DEBUG_IOC - Set value to 1 to show some debug messages during loading - concerning the disk accesses. -> IRQ_PER_PROC @@ -76,6 +72,11 @@ ---> SOCLIB=1 - If using SOCLIB, define this flag to use the SOCLIB device - drivers + If using SOCLIB, define this flag to use the BLOCK DEVICE + driver and to choose the platform_soclib device tree. + + ---> RAMDISK=1 + + If using SOCLIB, define this flag to use a RAMDISK instead + of BLOCK DEVICE (Set this flag when the SOCLIB flag is also set) ---> USE_DT=0 Index: /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 652) +++ /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 653) @@ -8,11 +8,11 @@ #define CACHE_LINE_SIZE 64//bytes -#define BOOT_DEBUG 1 -#define BOOT_DEBUG_IOC 0 +#define RESET_DEBUG 0 -#define IOC_BASE 0xFB000000 -#define TTY_BASE 0xFC000000 -#define ICU_BASE 0xFD000000 -#define MCC_BASE 0xFFFFFFFF // not used +#define ICU_PADDR_BASE 0xFD000000 +#define MCC_PADDR_BASE 0xFFFFFFFF // not used +#define IOC_PADDR_BASE 0xFB000000 +#define TTY_PADDR_BASE 0xFC000000 +#define RDK_PADDR_BASE 0xFFFFFFFF // not used /* Mandatory argument only for FPGA platforms */ Index: /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript =================================================================== --- /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript (revision 652) +++ /trunk/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript (revision 653) @@ -5,27 +5,31 @@ **********************************************************/ -/* Definition of the base address for all segments */ +/* Definition of the base address for code segment */ -seg_stack_base = 0x08000000 - 0x4000; -seg_boot_base = 0xBFC00000; /* le code de boot */ +seg_reset_code_base = 0xBFC00000; + +seg_reset_stack_base = 0x08000000 - 0x4000;; +seg_reset_stack_size = 0x4000; /* Grouping sections into segments */ -ENTRY(boot) +ENTRY(reset) + SECTIONS { - . = seg_boot_base; - .text : { - *(.boot) + . = seg_reset_code_base; + .text : + { *(.reset) - *(.rodata) - *(.rodata.*) - . = ALIGN(0x4); - dtb_addr = .; - INCLUDE "build/platform.ld"; + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; } - . = seg_stack_base; - .bss ALIGN(0x4) (NOLOAD) : { + . = seg_reset_stack_base; + .bss ALIGN(0x4) (NOLOAD) : + { *(.data) *(.bss) Index: /trunk/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h (revision 652) +++ /trunk/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h (revision 653) @@ -6,6 +6,5 @@ #define USE_IOB 1 #define CACHE_COHERENCE 1 -#define CACHE_LINE_SIZE 64 // bytes - +#define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) #define RESET_DEBUG 0 @@ -14,2 +13,3 @@ #define IOC_PADDR_BASE 0xB3000000 #define TTY_PADDR_BASE 0xB4000000 +#define RDK_PADDR_BASE 0xFFFFFFFF // not used Index: /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h =================================================================== --- /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h (revision 652) +++ /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h (revision 653) @@ -1,16 +1,15 @@ -#define NB_PROCS 1 -#define NB_CLUSTERS 1 +#define NB_PROCS 1 +#define NB_CLUSTERS 1 -#define IRQ_PER_PROC 1 +#define IRQ_PER_PROC 1 -#define USE_IOB 0 -#define CACHE_COHERENCE 1 -#define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) +#define USE_IOB 0 +#define CACHE_COHERENCE 1 +#define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) +#define RESET_DEBUG 0 -#define BOOT_DEBUG 1 -#define BOOT_DEBUG_IOC 0 - -#define TTY_BASE 0x20000000 -#define ICU_BASE 0x30000000 -#define IOC_BASE 0x40000000 -#define MCC_BASE 0xFFFFFFFF // not used +#define TTY_PADDR_BASE 0x20000000 +#define ICU_PADDR_BASE 0x30000000 +#define IOC_PADDR_BASE 0x40000000 +#define MCC_PADDR_BASE 0xFFFFFFFF // not used +#define RDK_PADDR_BASE 0xFFFFFFFF // not used Index: /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript =================================================================== --- /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript (revision 652) +++ /trunk/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript (revision 653) @@ -5,27 +5,31 @@ **********************************************************/ -/* Definition of the base address for all segments */ +/* Definition of the base address for code segment */ -seg_stack_base = 0x10000000 - 0x8000 - 0x4; -seg_boot_base = 0xBFC00000; /* le code de boot */ +seg_reset_boot_base = 0xBFC00000; /* le code de boot */ + +seg_reset_stack_base = 0x10000000 - 0x8000 - 0x4; +seg_reset_stack_base = 0x00008000; /* Grouping sections into segments */ -ENTRY(boot) +ENTRY(reset) + SECTIONS { - . = seg_boot_base; - .text : { - *(.boot) + . = seg_reset_code_base; + .text : + { *(.reset) - *(.rodata) - *(.rodata.*) - . = ALIGN(0x4); - dtb_addr = .; - INCLUDE "build/platform.ld"; + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; } - . = seg_stack_base; - .bss ALIGN(0x4) (NOLOAD) : { + . = seg_reset_stack_base; + .bss ALIGN(0x4) (NOLOAD) : + { *(.data) *(.bss) Index: /trunk/softs/tsar_boot/include/io.h =================================================================== --- /trunk/softs/tsar_boot/include/io.h (revision 652) +++ /trunk/softs/tsar_boot/include/io.h (revision 653) @@ -39,5 +39,5 @@ { *(volatile unsigned int *) addr = value; - asm volatile("sync"); + asm volatile("sync" ::: "memory"); } @@ -48,5 +48,5 @@ { *(volatile unsigned short *) addr = value; - asm volatile("sync"); + asm volatile("sync" ::: "memory"); } @@ -57,5 +57,5 @@ { *(volatile unsigned char *) addr = value; - asm volatile("sync"); + asm volatile("sync" ::: "memory"); } Index: /trunk/softs/tsar_boot/include/reset_ioc.h =================================================================== --- /trunk/softs/tsar_boot/include/reset_ioc.h (revision 652) +++ /trunk/softs/tsar_boot/include/reset_ioc.h (revision 653) @@ -2,17 +2,22 @@ #define RESET_IOC_H -#ifndef SOCLIB_IOC +#if USE_SPI #include #include -#else +#endif /* USE_SPI */ + +#if USE_BDV #include #include -#endif +#endif /* USE_BDV */ #include #include #include +#include +#if USE_SPI extern int reset_ioc_init(); +#endif /* USE_SPI */ extern int reset_ioc_read( unsigned int lba, @@ -20,13 +25,5 @@ unsigned int count ); -extern int reset_ioc_completed(); - -extern void reset_buf_invalidate ( const void * buffer, - unsigned int line_size, - unsigned int size ); - -extern void reset_mcc_invalidate( const void * buffer, - unsigned int size ); -#endif +#endif /* RESET_IOC_H */ /* Index: /trunk/softs/tsar_boot/include/reset_utils.h =================================================================== --- /trunk/softs/tsar_boot/include/reset_utils.h (revision 652) +++ /trunk/softs/tsar_boot/include/reset_utils.h (revision 653) @@ -19,5 +19,15 @@ extern void reset_print_elf_phdr(Elf32_Phdr * elf_phdr_ptr); -#endif +#if USE_IOB +void reset_mcc_invalidate ( const void * buffer, + unsigned int size); +#endif /* USE_IOB */ + +#if (CACHE_COHERENCE == 0) || USE_IOB +void reset_buf_invalidate ( const void * buffer, + unsigned int line_size, + unsigned int size); +#endif /* (CACHE_COHERENCE == 0) || USE_IOB */ +#endif /* BOOT_UTILS_H */ // vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab Index: /trunk/softs/tsar_boot/src/reset.S =================================================================== --- /trunk/softs/tsar_boot/src/reset.S (revision 652) +++ /trunk/softs/tsar_boot/src/reset.S (revision 653) @@ -159,7 +159,7 @@ -#ifndef SOCLIB_IOC - - /* Processor 0 Initialize the block device if required */ +#if USE_SPI + + /* Processor 0 Initialize the SPI controller */ la k0, reset_ioc_init Index: /trunk/softs/tsar_boot/src/reset_ioc.c =================================================================== --- /trunk/softs/tsar_boot/src/reset_ioc.c (revision 652) +++ /trunk/softs/tsar_boot/src/reset_ioc.c (revision 653) @@ -1,9 +1,7 @@ #include -#ifndef SOCLIB_IOC - -static struct sdcard_dev _sdcard_device; -static struct spi_dev *const _spi_device = ( struct spi_dev * )IOC_PADDR_BASE; - +#if USE_SPI +static struct sdcard_dev _sdcard_device; +static struct spi_dev *const _spi_device = (struct spi_dev*) IOC_PADDR_BASE; #endif @@ -17,19 +15,9 @@ } -#if RESET_DEBUG -//////////////////////////////////// -inline unsigned int reset_proctime() -{ - unsigned int ret; - asm volatile ("mfc0 %0, $9":"=r" (ret)); - return ret; -} -#endif - -#ifndef SOCLIB_IOC -///////////////////////////////////////////////////////////////////////////////// +#if USE_SPI +/////////////////////////////////////////////////////////////////////////////// // reset_ioc_init // This function initializes the SDCARD / required for FPGA. -///////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////// int reset_ioc_init() { @@ -105,200 +93,115 @@ #endif -#ifdef SOCLIB_IOC -///////////////////////////////////////////////////////////////////////////////////// -// reset_ioc_completed() -// This blocking function checks completion of an I/O transfer and reports errors. -// It returns 0 if the transfer is successfully completed. -// It returns -1 if an error has been reported. -///////////////////////////////////////////////////////////////////////////////////// -int reset_ioc_completed() -{ +////////////////////////////////////////////////////////////////////////////// +// reset_bdv_read() +///////////////////////////////////////////////////////////////////////////// +#if USE_BDV +int reset_bdv_read( unsigned int lba, + void* buffer, + unsigned int count ) +{ + unsigned int * ioc_address = (unsigned int*)IOC_PADDR_BASE; + + // block_device configuration + iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], (unsigned int) buffer ); + iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], count ); + iowrite32( &ioc_address[BLOCK_DEVICE_LBA], lba ); + iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE], 0 ); + + // block_device trigger transfer + iowrite32( &ioc_address[BLOCK_DEVICE_OP], ( unsigned int ) + BLOCK_DEVICE_READ ); + unsigned int status = 0; - - unsigned int * ioc_address = ( unsigned int * )IOC_PADDR_BASE; - while ( 1 ) { status = ioread32(&ioc_address[BLOCK_DEVICE_STATUS]); - - if (( status == BLOCK_DEVICE_READ_SUCCESS ) || - ( status == BLOCK_DEVICE_READ_ERROR )) - break; - } - - return status; -} // end reset_ioc_completed() -#endif - -#ifdef SOCLIB_IOC -///////////////////////////////////////////////////////////////////////////////////// + if ( status == BLOCK_DEVICE_READ_SUCCESS ) + { + break; + } + if ( status == BLOCK_DEVICE_READ_ERROR ) { + reset_puts("ERROR during read on the BLK device\n"); + return 1; + } + } +#if (CACHE_COHERENCE == 0) || USE_IOB + reset_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); +#endif + return 0; +} +#endif + +////////////////////////////////////////////////////////////////////////////// +// reset_spi_read() +///////////////////////////////////////////////////////////////////////////// +#if USE_SPI +static int reset_spi_read( unsigned int lba, + void* buffer, + unsigned int count ) +{ + unsigned int sdcard_rsp; + unsigned int i; + + sdcard_dev_lseek(&_sdcard_device, lba); + for(i = 0; i < count; i++) + { + unsigned char* buf = (unsigned char *) buffer + (512 * i); + if (( sdcard_rsp = sdcard_dev_read ( &_sdcard_device, buf, 512 ) )) + { + reset_puts("ERROR during read on the SDCARD device. Code: "); + reset_putx(sdcard_rsp); + reset_puts("\n"); + return 1; + } + } + return 0; +} +#endif + +////////////////////////////////////////////////////////////////////////////// +// reset_rdk_read() +///////////////////////////////////////////////////////////////////////////// +#if USE_RDK +static int reset_rdk_read( unsigned int lba, + void* buffer, + unsigned int count ) +{ + unsigned int* rdk_address = (unsigned int*) RDK_PADDR_BASE; + char* src = (char*) rdk_address + (lba * 512); + + memcpy(buffer, (void*) src, count * 512); + return 0; +} +#endif + +/////////////////////////////////////////////////////////////////////////////// // reset_ioc_read() -// Transfer data the block device to a memory buffer: SOCLIB version +// Transfer data from disk to a memory buffer // - param lba : first block index on the disk // - param buffer : base address of the memory buffer // - param count : number of blocks to be transfered -// This is a blocking function. The function returns once the transfer is completed. -///////////////////////////////////////////////////////////////////////////////////// +// This is a blocking function. The function returns once the transfer is +// completed. +// +// The USE_BDV, USE_SPI and USE_RDK variables signal if the disk is accessed +// through a BLOCK DEVICE, SPI or RAMDISK respectively +/////////////////////////////////////////////////////////////////////////////// int reset_ioc_read( unsigned int lba, void* buffer, unsigned int count ) { - - unsigned int * ioc_address = (unsigned int*)IOC_PADDR_BASE; - -#if RESET_DEBUG - unsigned int start_time; - unsigned int end_time; - reset_puts("[RESET DEBUG] Reading blocks "); - reset_putd(lba); - reset_puts(" to "); - reset_putd(lba + count - 1); - - start_time = reset_proctime(); -#endif - - // block_device configuration - iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], - ( unsigned int ) buffer ); - - iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], - ( unsigned int ) count ); - - iowrite32( &ioc_address[BLOCK_DEVICE_LBA], - ( unsigned int ) lba ); - - iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE], - ( unsigned int ) 0 ); - - iowrite32( &ioc_address[BLOCK_DEVICE_OP], - ( unsigned int ) BLOCK_DEVICE_READ ); - - reset_ioc_completed(); - -#if (CACHE_COHERENCE == 0) || (USE_IOB == 1) - reset_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); -#endif - -#if USE_IOB - reset_mcc_invalidate(buffer, count * 512); -#endif - -#if RESET_DEBUG - end_time = reset_proctime(); - reset_puts(" / cycles for transfert: "); - reset_putd(end_time - start_time); - reset_puts("\n"); -#endif - - return 0; -} // end reset_ioc_read() - -#else - -///////////////////////////////////////////////////////////////////////////////////// -// reset_ioc_read() -// Transfer data the block device to a memory buffer: FPGA version -// - param lba : first block index on the disk -// - param buffer : base address of the memory buffer -// - param count : number of blocks to be transfered -// This is a blocking function. The function returns once the transfer is completed. -///////////////////////////////////////////////////////////////////////////////////// -int reset_ioc_read( unsigned int lba, - void* buffer, - unsigned int count ) -{ - unsigned int sdcard_rsp; - unsigned int i; - - sdcard_dev_lseek(&_sdcard_device, lba); - -#if RESET_DEBUG - unsigned int start_time; - unsigned int end_time; - reset_puts("[RESET DEBUG] Reading blocks "); - reset_putd(lba); - reset_puts(" to "); - reset_putd(lba + count - 1); - start_time = reset_proctime(); -#endif - - for(i = 0; i < count; i++) - { - if (( sdcard_rsp = sdcard_dev_read ( - &_sdcard_device, - (unsigned char *) buffer + (512 * i), - 512 - ) - )) - { - reset_puts("ERROR during read on the SDCARD device. Code: "); - reset_putx(sdcard_rsp); - reset_puts("\n\r"); - - return 1; - } - } - -#if RESET_DEBUG - end_time = reset_proctime(); - reset_puts(" / cycles for transfert: "); - reset_putd(end_time - start_time); - reset_puts("\n"); -#endif - - return 0; -} // end reset_ioc_read() -#endif - -////////////////////////////////////////////////////////////////////////////// -// reset_dcache_buf_invalidate() -// Invalidate all data cache lines corresponding to a memory buffer -// (identified by an address and a size) in L1 cache. -///////////////////////////////////////////////////////////////////////////// -#if (CACHE_COHERENCE == 0) || (USE_IOB == 1) -void reset_buf_invalidate ( const void * buffer, - unsigned int line_size, - unsigned int size) -{ - unsigned int i; - - // iterate on cache lines - for (i = 0; i <= size; i += line_size) - { - asm volatile( - " cache %0, %1" - :// no outputs - :"i" (0x11), "R" (*((unsigned char *) buffer + i)) - ); - } -} -#endif - -////////////////////////////////////////////////////////////////////////////// -// reset_mcc_inval() -// Invalidate all data cache lines corresponding to a memory buffer -// (identified by an address and a size) in L2 cache. -///////////////////////////////////////////////////////////////////////////// -#if USE_IOB -void reset_mcc_invalidate ( const void * buffer, - unsigned int size) -{ - unsigned int * mcc_address = (unsigned int *)MCC_PADDR_BASE; - - // get the hard lock assuring exclusive access to MEMC - while (ioread32(&mcc_address[MCC_LOCK])); - - // write invalidate paremeters on the memory cache - // this preloader use only the cluster 0 and then the HI bits are not used - - iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer); - iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0); - iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size); - iowrite32(&mcc_address[MCC_CMD] , (unsigned int) MCC_CMD_INVAL); - - // release the lock protecting MEMC - iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0); -} -#endif + int status; +#if USE_BDV + status = reset_bdv_read(lba, buffer, count); +#endif +#if USE_SPI + status = reset_spi_read(lba, buffer, count); +#endif +#if USE_RDK + status = reset_rdk_read(lba, buffer, count); +#endif + return status; +} /* Index: /trunk/softs/tsar_boot/src/reset_utils.c =================================================================== --- /trunk/softs/tsar_boot/src/reset_utils.c (revision 652) +++ /trunk/softs/tsar_boot/src/reset_utils.c (revision 653) @@ -9,9 +9,9 @@ #include -/***************************************** +/******************************************************************** * proctime() * * Returns processor local time. - ****************************************/ + ********************************************************************/ inline unsigned int proctime() { @@ -21,5 +21,5 @@ } -/***************************************** +/******************************************************************** * memcpy( _dst, _src, size ) * @@ -30,5 +30,5 @@ * \param size : Number of bytes to transfer * - ****************************************/ + ********************************************************************/ void * memcpy(void *_dst, const void *_src, unsigned int size) { @@ -52,5 +52,5 @@ } -/***************************************** +/******************************************************************** * memset( _dst, value, size ) * @@ -61,5 +61,5 @@ * \param size : Number of bytes to initialize * - ****************************************/ + ********************************************************************/ void * memset(void *_dst, const int value, unsigned int size) { @@ -71,5 +71,5 @@ } -/***************************************** +/******************************************************************** * reset_print_elf_phdr( elf_phdr_ptr ) * @@ -78,5 +78,5 @@ * \param elf_phdr_ptr : Pointer to the ELF program header to print * - ****************************************/ + ********************************************************************/ void reset_print_elf_phdr(Elf32_Phdr * elf_phdr_ptr) { @@ -106,3 +106,61 @@ } + +/******************************************************************** + * reset_mcc_inval() + * + * Invalidate all data cache lines corresponding to a memory buffer + * (identified by an address and a size) in L2 cache. + ********************************************************************/ +#if USE_IOB +void reset_mcc_invalidate ( const void * buffer, + unsigned int size) +{ + unsigned int * mcc_address = (unsigned int *)MCC_PADDR_BASE; + + // get the hard lock assuring exclusive access to MEMC + while (ioread32(&mcc_address[MCC_LOCK])); + + // write invalidate paremeters on the memory cache this preloader + // use only the cluster 0 and then the HI bits are not used + + iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer); + iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0); + iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size); + iowrite32(&mcc_address[MCC_CMD] , (unsigned int) MCC_CMD_INVAL); + + // release the lock protecting MEMC + iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0); +} +#endif + +/******************************************************************** + * reset_dcache_buf_invalidate() + * + * Invalidate all data cache lines corresponding to a memory buffer + * (identified by an address and a size) in L1 cache and L2 cache. + ********************************************************************/ +#if (CACHE_COHERENCE == 0) || USE_IOB +void reset_buf_invalidate ( const void * buffer, + unsigned int line_size, + unsigned int size) +{ + unsigned int i; + + // iterate on cache lines + for (i = 0; i <= size; i += line_size) + { + asm volatile( + " cache %0, %1" + :// no outputs + :"i" (0x11), "R" (*((unsigned char *) buffer + i)) + ); + } + +#if USE_IOB + reset_mcc_invalidate(buffer, count * 512); +#endif +} +#endif + // vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab