Index: branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 651) +++ branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 656) @@ -113,4 +113,5 @@ DCACHE_XTN_IC_FLUSH, DCACHE_XTN_IC_INVAL_PA, + DCACHE_XTN_IC_PADDR_EXT, DCACHE_XTN_IT_INVAL, DCACHE_XTN_DC_FLUSH, @@ -322,4 +323,7 @@ bool m_debug_ok; + uint32_t m_dcache_paddr_ext_reset; + uint32_t m_icache_paddr_ext_reset; + //////////////////////////////////////// // Communication with processor ISS @@ -399,4 +403,7 @@ sc_signal r_icache_cc_send_way; // ICACHE cc_send way sc_signal r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index + + // Physical address extension for data access + sc_signal r_icache_paddr_ext; // CP2 register (if vci_address > 32) /////////////////////////////// @@ -747,4 +754,26 @@ } + ///////////////////////////////////////////////////////////// + // Set the m_dcache_paddr_ext_reset attribute + // + // The r_dcache_paddr_ext register will be initialized after + // reset with the m_dcache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_dcache_paddr_ext_reset(uint32_t v) + { + m_dcache_paddr_ext_reset = v; + } + + ///////////////////////////////////////////////////////////// + // Set the m_icache_paddr_ext_reset attribute + // + // The r_icache_paddr_ext register will be initialized after + // reset with the m_icache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_icache_paddr_ext_reset(uint32_t v) + { + m_icache_paddr_ext_reset = v; + } + private: void transition(); Index: branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 651) +++ branches/fault_tolerance/module/internal_component/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 656) @@ -32,7 +32,7 @@ #include "../include/vci_cc_vcache_wrapper.h" -#define DEBUG_DCACHE 1 -#define DEBUG_ICACHE 1 -#define DEBUG_CMD 0 +#define DEBUG_DCACHE 1 +#define DEBUG_ICACHE 1 +#define DEBUG_CMD 0 namespace soclib { @@ -85,4 +85,5 @@ "DCACHE_XTN_IC_FLUSH", "DCACHE_XTN_IC_INVAL_PA", + "DCACHE_XTN_IC_PADDR_EXT" "DCACHE_XTN_IT_INVAL", "DCACHE_XTN_DC_FLUSH", @@ -190,26 +191,26 @@ ///////////////////////////////// tmpl(/**/)::VciCcVCacheWrapper( - sc_module_name name, - const int proc_id, - const MappingTable &mtd, - const IntTab &srcid, - const size_t cc_global_id, - const size_t itlb_ways, - const size_t itlb_sets, - const size_t dtlb_ways, - const size_t dtlb_sets, - const size_t icache_ways, - const size_t icache_sets, - const size_t icache_words, - const size_t dcache_ways, - const size_t dcache_sets, - const size_t dcache_words, - const size_t wbuf_nlines, - const size_t wbuf_nwords, - const size_t x_width, - const size_t y_width, - const uint32_t max_frozen_cycles, - const uint32_t debug_start_cycle, - const bool debug_ok ) + sc_module_name name, + const int proc_id, + const MappingTable &mtd, + const IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ) : soclib::caba::BaseModule(name), @@ -244,4 +245,6 @@ m_debug_start_cycle( debug_start_cycle ), m_debug_ok( debug_ok ), + m_dcache_paddr_ext_reset(0), + m_icache_paddr_ext_reset(0), r_mmu_ptpr("r_mmu_ptpr"), @@ -371,6 +374,6 @@ r_vci_rsp_ins_error("r_vci_rsp_ins_error"), r_vci_rsp_data_error("r_vci_rsp_data_error"), - r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth - r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth + r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth + r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth r_cc_send_fsm("r_cc_send_fsm"), @@ -380,7 +383,7 @@ r_cc_receive_data_ins("r_cc_receive_data_ins"), r_cc_receive_word_idx("r_cc_receive_word_idx"), - r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth - r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth - r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth + r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth + r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth + r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth r_cc_receive_icache_req("r_cc_receive_icache_req"), @@ -528,8 +531,8 @@ { bool cache_hit; - size_t cache_way = 0; - size_t cache_set = 0; - size_t cache_word = 0; - uint32_t cache_rdata = 0; + size_t cache_way = 0; + size_t cache_set = 0; + size_t cache_word = 0; + uint32_t cache_rdata = 0; cache_hit = r_dcache.read_neutral( addr, @@ -547,5 +550,5 @@ << " / DATA = " << cache_rdata << " / WAY = " << cache_way << std::endl; - m_debug_previous_d_hit = cache_hit; + m_debug_previous_d_hit = cache_hit; } @@ -564,5 +567,5 @@ << " / DATA = " << cache_rdata << " / WAY = " << cache_way << std::endl; - m_debug_previous_i_hit = cache_hit; + m_debug_previous_i_hit = cache_hit; } } @@ -735,5 +738,8 @@ // reset data physical address extension - r_dcache_paddr_ext = 0; + r_dcache_paddr_ext = m_dcache_paddr_ext_reset; + + // reset inst physical address extension + r_icache_paddr_ext = m_icache_paddr_ext_reset; // reset dcache directory extension @@ -752,5 +758,5 @@ r_mmu_mode = 0x3; - // No request from ICACHE FSM to CMD FSM + // No request from ICACHE FSM to CMD FSM r_icache_miss_req = false; r_icache_unc_req = false; @@ -809,5 +815,5 @@ m_debug_previous_i_hit = false; m_debug_previous_d_hit = false; - m_debug_activated = false; + m_debug_activated = false; // activity counters @@ -870,18 +876,18 @@ m_cost_data_tlb_occup_cache_frz = 0; - m_cpt_ins_tlb_inval = 0; - m_cpt_data_tlb_inval = 0; - m_cost_ins_tlb_inval_frz = 0; - m_cost_data_tlb_inval_frz = 0; + m_cpt_ins_tlb_inval = 0; + m_cpt_data_tlb_inval = 0; + m_cost_ins_tlb_inval_frz = 0; + m_cost_data_tlb_inval_frz = 0; m_cpt_cc_broadcast = 0; - m_cost_updt_data_frz = 0; - m_cost_inval_ins_frz = 0; - m_cost_inval_data_frz = 0; - m_cost_broadcast_frz = 0; - - m_cpt_cc_cleanup_data = 0; - m_cpt_cc_cleanup_ins = 0; + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; m_cpt_itlbmiss_transaction = 0; @@ -906,7 +912,7 @@ m_cpt_read = 0; m_cpt_write = 0; - m_cpt_cc_update_data = 0; - m_cpt_cc_inval_ins = 0; - m_cpt_cc_inval_data = 0; + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; */ @@ -1018,5 +1024,5 @@ { ///////////////// - case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests, + case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests, // and coherence requests with a fixed priority: // 1/ Coherence requests => ICACHE_CC_CHECK @@ -1043,6 +1049,6 @@ // XTN requests sent by DCACHE FSM - // These request are not executed in this IDLE state, because - // they require access to icache or itlb, that are already accessed + // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), + // because they require access to icache or itlb, that are already accessed if ( r_dcache_xtn_req.read() ) { @@ -1066,16 +1072,21 @@ else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) { - if (sizeof(paddr_t) <= 32) + if (sizeof(paddr_t) <= 32) { - assert(r_mmu_word_hi.read() == 0 && - "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); - r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); + assert(r_mmu_word_hi.read() == 0 && + "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); + r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); } else { - r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | - (paddr_t)r_mmu_word_lo.read(); - } - r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | + (paddr_t)r_mmu_word_lo.read(); + } + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT) + { + r_icache_paddr_ext = r_dcache_save_wdata.read(); + r_dcache_xtn_req = false; } else @@ -1090,6 +1101,6 @@ if ( m_ireq.valid ) { - bool cacheable; - paddr_t paddr; + bool cacheable; + paddr_t paddr; bool tlb_hit = false; pte_info_t tlb_flags; @@ -1116,11 +1127,19 @@ &paddr, &tlb_flags, - &tlb_nline, // unused - &tlb_way, // unused - &tlb_set ); // unused + &tlb_nline, // unused + &tlb_way, // unused + &tlb_set ); // unused } else { - paddr = (paddr_t)m_ireq.addr; + if (vci_param::N > 32) + { + paddr = (paddr_t)m_ireq.addr | + ((paddr_t)r_icache_paddr_ext.read() << 32); + } + else + { + paddr = (paddr_t)m_ireq.addr; + } } @@ -1148,5 +1167,5 @@ // and there is no access rights checking - if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: + if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: { // cacheability @@ -1154,7 +1173,7 @@ else cacheable = m_cacheability_table[(uint64_t)m_ireq.addr]; } - else // itlb activated - { - if ( tlb_hit ) // ITLB hit + else // itlb activated + { + if ( tlb_hit ) // ITLB hit { // cacheability @@ -1200,5 +1219,5 @@ if ( cacheable ) { - if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss { @@ -1215,10 +1234,10 @@ r_icache_miss_req = true; } - else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup { // stalled until cleanup is acknowledged r_icache_fsm = ICACHE_IDLE; } - else // cache hit + else // cache hit { @@ -1237,5 +1256,5 @@ } } - else // non cacheable read + else // non cacheable read { r_icache_unc_req = true; @@ -1255,5 +1274,5 @@ } ///////////////////// - case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss + case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss // the itlb is udated by the DCACHE FSM, as well as the // r_mmu_ietr and r_mmu_ibvar registers in case of error. @@ -1290,5 +1309,5 @@ r_icache_fsm = ICACHE_IDLE; } - else // tlb updated : return to IDLE state + else // tlb updated : return to IDLE state { r_icache_fsm = ICACHE_IDLE; @@ -1298,5 +1317,5 @@ } ////////////////////////// - case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries + case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries { r_itlb.flush(); @@ -1306,11 +1325,11 @@ } //////////////////////////// - case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using + case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using // r_icache_flush_count as a slot counter, - // looping in this state until all slots are visited. + // looping in this state until all slots are visited. // It can require two cycles per slot: // We test here the slot state, and make the actual inval // (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state. - // A cleanup request is generated for each valid line + // A cleanup request is generated for each valid line { // coherence clack interrupt @@ -1334,6 +1353,6 @@ int state; paddr_t tag; - size_t way = r_icache_flush_count.read()/m_icache_sets; - size_t set = r_icache_flush_count.read()%m_icache_sets; + size_t way = r_icache_flush_count.read()/m_icache_sets; + size_t set = r_icache_flush_count.read()%m_icache_sets; #ifdef INSTRUMENTATION @@ -1361,7 +1380,7 @@ (m_icache_sets*m_icache_ways - 1) ) // last slot { - r_dcache_xtn_req = false; + r_dcache_xtn_req = false; m_drsp.valid = true; - r_icache_fsm = ICACHE_IDLE; + r_icache_fsm = ICACHE_IDLE; } @@ -1376,8 +1395,8 @@ } /////////////////////////////// - case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush - { - size_t way = r_icache_miss_way.read(); - size_t set = r_icache_miss_set.read(); + case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush + { + size_t way = r_icache_miss_way.read(); + size_t set = r_icache_miss_set.read(); #ifdef INSTRUMENTATION @@ -1392,7 +1411,7 @@ (m_icache_sets*m_icache_ways - 1) ) // last slot { - r_dcache_xtn_req = false; + r_dcache_xtn_req = false; m_drsp.valid = true; - r_icache_fsm = ICACHE_IDLE; + r_icache_fsm = ICACHE_IDLE; } else @@ -1404,6 +1423,6 @@ ////////////////////////// - case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address - // stored in the r_dcache_save_wdata register + case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address + // stored in the r_dcache_save_wdata register { r_itlb.inval(r_dcache_save_wdata.read()); @@ -1413,14 +1432,14 @@ } /////////////////////////////// - case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address + case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address // requires 3 cycles (in case of hit on itlb and icache). - // In this state, access TLB to translate virtual address - // stored in the r_dcache_save_wdata register. - { - paddr_t paddr; - bool hit; + // In this state, access TLB to translate virtual address + // stored in the r_dcache_save_wdata register. + { + paddr_t paddr; + bool hit; // read physical address in TLB when MMU activated - if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated + if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated { @@ -1431,16 +1450,16 @@ &paddr); } - else // itlb not activated - { - paddr = (paddr_t)r_dcache_save_wdata.read(); - hit = true; - } - - if ( hit ) // continue the selective inval process + else // itlb not activated + { + paddr = (paddr_t)r_dcache_save_wdata.read(); + hit = true; + } + + if ( hit ) // continue the selective inval process { r_icache_vci_paddr = paddr; r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; } - else // miss : send a request to DCACHE FSM + else // miss : send a request to DCACHE FSM { @@ -1449,5 +1468,5 @@ #endif r_icache_tlb_miss_req = true; - r_icache_vaddr_save = r_dcache_save_wdata.read(); + r_icache_vaddr_save = r_dcache_save_wdata.read(); r_icache_fsm = ICACHE_TLB_WAIT; } @@ -1455,12 +1474,12 @@ } /////////////////////////////// - case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address + case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address // require 2 cycles. In this state, we read directory // with address stored in r_icache_vci_paddr register. { int state; - size_t way; - size_t set; - size_t word; + size_t way; + size_t set; + size_t word; #ifdef INSTRUMENTATION @@ -1473,5 +1492,5 @@ &word); - if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done { r_icache_miss_way = way; @@ -1479,5 +1498,5 @@ r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; } - else // miss : acknowlege the XTN request and return + else // miss : acknowlege the XTN request and return { r_dcache_xtn_req = false; @@ -1543,7 +1562,7 @@ bool found; bool cleanup; - size_t way; - size_t set; - paddr_t victim; + size_t way; + size_t set; + paddr_t victim; #ifdef INSTRUMENTATION @@ -1603,5 +1622,5 @@ } /////////////////////// - case ICACHE_MISS_CLEAN: // switch the slot to zombi state + case ICACHE_MISS_CLEAN: // switch the slot to zombi state { if (m_ireq.valid) m_cost_ins_miss_frz++; @@ -1627,5 +1646,5 @@ } ////////////////////// - case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM + case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM { if (m_ireq.valid) m_cost_ins_miss_frz++; @@ -1674,9 +1693,9 @@ } /////////////////////////// - case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) + case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) { if ( m_ireq.valid ) m_cost_ins_miss_frz++; - if ( r_vci_rsp_fifo_icache.rok() ) // response available + if ( r_vci_rsp_fifo_icache.rok() ) // response available { @@ -1702,5 +1721,5 @@ r_icache_miss_word = r_icache_miss_word.read() + 1; - if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word + if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word { r_icache_fsm = ICACHE_MISS_DIR_UPDT; @@ -1710,5 +1729,5 @@ } ////////////////////////// - case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted, + case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted, // and the cleanup ack has not been received, // as indicated by r_icache_miss_clack. @@ -1807,5 +1826,5 @@ } //////////////////// - case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM + case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM { // coherence clack interrupt @@ -1848,5 +1867,5 @@ } ///////////////////// - case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm + case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm // handling coherence requests. // if there is a matching pending miss, it is @@ -1938,8 +1957,8 @@ // CC request handler - int state = 0; - size_t way = 0; - size_t set = 0; - size_t word = 0; + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; #ifdef INSTRUMENTATION @@ -1989,5 +2008,5 @@ } ///////////////////// - case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state + case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state { assert (not r_icache_cc_send_req.read() && @@ -2025,5 +2044,5 @@ } //////////////////// - case ICACHE_CC_UPDT: // hit update : write one word per cycle + case ICACHE_CC_UPDT: // hit update : write one word per cycle { assert (not r_icache_cc_send_req.read() && @@ -2064,5 +2083,5 @@ } - if ( r_cc_receive_updt_fifo_eop.read() ) // last word + if ( r_cc_receive_updt_fifo_eop.read() ) // last word { // no need to write in the cache anymore @@ -2204,14 +2223,14 @@ { paddr_t paddr; // physical address - pte_info_t tlb_flags; - size_t tlb_way; - size_t tlb_set; - paddr_t tlb_nline = 0; - size_t cache_way; - size_t cache_set; - size_t cache_word; - uint32_t cache_rdata = 0; - bool tlb_hit = false; - int cache_state = CACHE_SLOT_STATE_EMPTY; + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + uint32_t cache_rdata = 0; + bool tlb_hit = false; + int cache_state = CACHE_SLOT_STATE_EMPTY; bool tlb_inval_required = false; // request TLB inval after cache update @@ -2301,8 +2320,8 @@ { tlb_inval_required = true; - r_dcache_tlb_inval_set = 0; - r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> + r_dcache_tlb_inval_set = 0; + r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> (uint32_log2(m_dcache_words<<2)); - r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_in_tlb[way*m_dcache_sets+set] = false; } else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) @@ -2310,5 +2329,5 @@ r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; } @@ -2467,4 +2486,10 @@ break; + case iss_t::XTN_INST_PADDR_EXT: + m_drsp.rdata = r_icache_paddr_ext.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + default: r_mmu_detr = MMU_READ_UNDEFINED_XTN; @@ -2508,10 +2533,10 @@ switch( xtn_opcode ) { - case iss_t::XTN_PTPR: // itlb & dtlb must be flushed + case iss_t::XTN_PTPR: // itlb & dtlb must be flushed r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_SWITCH; break; - case iss_t::XTN_TLB_MODE: // no cache or tlb access + case iss_t::XTN_TLB_MODE: // no cache or tlb access r_mmu_mode = m_dreq.wdata; m_drsp.valid = true; @@ -2519,18 +2544,18 @@ break; - case iss_t::XTN_DTLB_INVAL: // dtlb access + case iss_t::XTN_DTLB_INVAL: // dtlb access r_dcache_fsm = DCACHE_XTN_DT_INVAL; break; - case iss_t::XTN_ITLB_INVAL: // itlb access + case iss_t::XTN_ITLB_INVAL: // itlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IT_INVAL; break; - case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access + case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; break; - case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access + case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; if (sizeof(paddr_t) <= 32) @@ -2547,29 +2572,29 @@ break; - case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset + case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset r_dcache_flush_count = 0; r_dcache_fsm = DCACHE_XTN_DC_FLUSH; break; - case iss_t::XTN_ICACHE_INVAL: // icache and itlb access + case iss_t::XTN_ICACHE_INVAL: // icache and itlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; break; - case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access + case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; break; - case iss_t::XTN_ICACHE_FLUSH: // icache access + case iss_t::XTN_ICACHE_FLUSH: // icache access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_FLUSH; break; - case iss_t::XTN_SYNC: // wait until write buffer empty + case iss_t::XTN_SYNC: // wait until write buffer empty r_dcache_fsm = DCACHE_XTN_SYNC; break; - case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access + case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access r_mmu_word_lo = m_dreq.wdata; m_drsp.valid = true; @@ -2577,5 +2602,5 @@ break; - case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access + case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access r_mmu_word_hi = m_dreq.wdata; m_drsp.valid = true; @@ -2595,9 +2620,14 @@ break; - case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action - case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; + break; + + case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action m_drsp.valid = true; r_dcache_fsm = DCACHE_IDLE; - break; + break; default: @@ -2622,8 +2652,8 @@ else { - bool valid_req; - bool cacheable; - - if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated + bool valid_req; + bool cacheable; + + if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated { valid_req = true; @@ -2632,7 +2662,7 @@ else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr]; } - else // dtlb activated + else // dtlb activated { - if ( tlb_hit ) // tlb hit + if ( tlb_hit ) // tlb hit { // cacheability @@ -2684,5 +2714,5 @@ } } - else // tlb miss + else // tlb miss { valid_req = false; @@ -2693,5 +2723,5 @@ } // end DTLB activated - if ( valid_req ) // processor request is valid (after MMU check) + if ( valid_req ) // processor request is valid (after MMU check) { // READ request @@ -2702,5 +2732,5 @@ and not r_dcache_updt_req.read() ) { - if ( cacheable ) // cacheable read + if ( cacheable ) // cacheable read { if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss @@ -2749,5 +2779,5 @@ } } - else // uncacheable read + else // uncacheable read { r_dcache_vci_paddr = paddr; @@ -2794,14 +2824,14 @@ { if ( (r_mmu_mode.read() & DATA_TLB_MASK ) - and not tlb_flags.d ) // Dirty bit must be set + and not tlb_flags.d ) // Dirty bit must be set { // The PTE physical address is obtained from the nline value (dtlb), // and from the virtual address (word index) - if ( tlb_flags.b ) // PTE1 + if ( tlb_flags.b ) // PTE1 { r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | (paddr_t)((m_dreq.addr>>19) & 0x3c); } - else // PTE2 + else // PTE2 { r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | @@ -2810,5 +2840,5 @@ r_dcache_fsm = DCACHE_DIRTY_GET_PTE; } - else // Write request accepted + else // Write request accepted { #ifdef INSTRUMENTATION @@ -2852,14 +2882,14 @@ { if ( (r_mmu_mode.read() & DATA_TLB_MASK ) - and not tlb_flags.d ) // Dirty bit must be set + and not tlb_flags.d ) // Dirty bit must be set { // The PTE physical address is obtained from the nline value (dtlb), // and the word index (virtual address) - if ( tlb_flags.b ) // PTE1 + if ( tlb_flags.b ) // PTE1 { r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | (paddr_t)((m_dreq.addr>>19) & 0x3c); } - else // PTE2 + else // PTE2 { r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | @@ -2871,5 +2901,5 @@ m_drsp.rdata = 0; } - else // SC request accepted + else // SC request accepted { #ifdef INSTRUMENTATION @@ -2888,7 +2918,7 @@ else // local fail { - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = 0x1; + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = 0x1; } } @@ -2899,5 +2929,5 @@ // itlb miss request - else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss ) + else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss ) { r_dcache_tlb_ins = true; @@ -2925,14 +2955,14 @@ // r_mmu_ins_* or r_mmu_data* error reporting registers. { - uint32_t ptba = 0; - bool bypass; - paddr_t pte_paddr; + uint32_t ptba = 0; + bool bypass; + paddr_t pte_paddr; // evaluate bypass in order to skip first level page table access - if ( r_dcache_tlb_ins.read() ) // itlb miss + if ( r_dcache_tlb_ins.read() ) // itlb miss { bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); } - else // dtlb miss + else // dtlb miss { bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); @@ -2971,5 +3001,5 @@ } ///////////////////////// - case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache + case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache { // coherence clack request (from DSPIN CLACK) @@ -2989,8 +3019,8 @@ } - uint32_t entry; - size_t way; - size_t set; - size_t word; + uint32_t entry; + size_t way; + size_t set; + size_t word; int cache_state; r_dcache.read( r_dcache_tlb_paddr.read(), @@ -3006,5 +3036,5 @@ if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache { - if ( not (entry & PTE_V_MASK) ) // unmapped + if ( not (entry & PTE_V_MASK) ) // unmapped { if ( r_dcache_tlb_ins.read() ) @@ -3038,5 +3068,5 @@ } - else if( entry & PTE_T_MASK ) // PTD : me must access PT2 + else if( entry & PTE_T_MASK ) // PTD : me must access PT2 { // mark the cache line ac containing a PTD @@ -3044,5 +3074,5 @@ // register bypass - if ( r_dcache_tlb_ins.read() ) // itlb + if ( r_dcache_tlb_ins.read() ) // itlb { r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), @@ -3050,5 +3080,5 @@ r_dcache_tlb_paddr.read() / (m_icache_words<<2) ); } - else // dtlb + else // dtlb { r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), @@ -3074,5 +3104,5 @@ #endif } - else // PTE1 : we must update the TLB + else // PTE1 : we must update the TLB { r_dcache_in_tlb[m_icache_sets*way+set] = true; @@ -3102,5 +3132,5 @@ r_dcache_fsm = DCACHE_TLB_PTE1_GET; } - else // we must load the missing cache line in dcache + else // we must load the missing cache line in dcache { r_dcache_vci_miss_req = true; @@ -3122,8 +3152,8 @@ } //////////////////////////// - case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 - { - size_t way; - size_t set; + case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 + { + size_t way; + size_t set; if ( r_dcache_tlb_ins.read() ) @@ -3167,5 +3197,5 @@ } ////////////////////////// - case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit + case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit // - if L/R bit already set, exit the sub-fsm. // - if not, we update the page table but we dont write @@ -3173,8 +3203,8 @@ // the coherence mechanism. { - paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); uint32_t pte = r_dcache_tlb_pte_flags.read(); - bool pt_updt = false; - bool local = true; + bool pt_updt = false; + bool local = true; // We should compute the access locality: @@ -3185,5 +3215,5 @@ // As long as this computation is not done, all access are local. - if ( local ) // local access + if ( local ) // local access { if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit @@ -3196,5 +3226,5 @@ } } - else // remote access + else // remote access { if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit @@ -3208,11 +3238,11 @@ } - if ( not pt_updt ) // update TLB and return + if ( not pt_updt ) // update TLB and return { if ( r_dcache_tlb_ins.read() ) { - r_itlb.write( true, // 2M page + r_itlb.write( true, // 2M page pte, - 0, // argument unused for a PTE1 + 0, // argument unused for a PTE1 r_dcache_tlb_vaddr.read(), r_dcache_tlb_way.read(), @@ -3236,7 +3266,7 @@ else { - r_dtlb.write( true, // 2M page + r_dtlb.write( true, // 2M page pte, - 0, // argument unused for a PTE1 + 0, // argument unused for a PTE1 r_dcache_tlb_vaddr.read(), r_dcache_tlb_way.read(), @@ -3276,5 +3306,5 @@ } ///////////////////////// - case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache + case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache { // coherence clack request (from DSPIN CLACK) @@ -3294,9 +3324,9 @@ } - uint32_t pte_flags; - uint32_t pte_ppn; - size_t way; - size_t set; - size_t word; + uint32_t pte_flags; + uint32_t pte_ppn; + size_t way; + size_t set; + size_t word; int cache_state; @@ -3314,5 +3344,5 @@ if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache { - if ( not (pte_flags & PTE_V_MASK) ) // unmapped + if ( not (pte_flags & PTE_V_MASK) ) // unmapped { if ( r_dcache_tlb_ins.read() ) @@ -3342,5 +3372,5 @@ #endif } - else // mapped : we must update the TLB + else // mapped : we must update the TLB { r_dcache_in_tlb[m_dcache_sets*way+set] = true; @@ -3405,5 +3435,5 @@ { r_itlb.select( r_dcache_tlb_vaddr.read(), - false, // PTE2 + false, // PTE2 &way, &set ); @@ -3415,5 +3445,5 @@ { r_dtlb.select( r_dcache_tlb_vaddr.read(), - false, // PTE2 + false, // PTE2 &way, &set ); @@ -3442,5 +3472,5 @@ } ////////////////////////// - case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit + case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit // - if L/R bit already set, exit the sub-fsm. // - if not, we update the page table but we dont write @@ -3448,5 +3478,5 @@ // the coherence mechanism. { - paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); @@ -3461,5 +3491,5 @@ // As long as this computation is not done, all access are local. - if ( local ) // local access + if ( local ) // local access { if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit @@ -3469,5 +3499,5 @@ r_dcache_vci_cas_new = pte_flags | PTE_L_MASK; pte_flags = pte_flags | PTE_L_MASK; - r_dcache_tlb_pte_flags = pte_flags; + r_dcache_tlb_pte_flags = pte_flags; } } @@ -3480,5 +3510,5 @@ r_dcache_vci_cas_new = pte_flags | PTE_R_MASK; pte_flags = pte_flags | PTE_R_MASK; - r_dcache_tlb_pte_flags = pte_flags; + r_dcache_tlb_pte_flags = pte_flags; } } @@ -3488,5 +3518,5 @@ if ( r_dcache_tlb_ins.read() ) { - r_itlb.write( false, // 4K page + r_itlb.write( false, // 4K page pte_flags, pte_ppn, @@ -3512,5 +3542,5 @@ else { - r_dtlb.write( false, // 4K page + r_dtlb.write( false, // 4K page pte_flags, pte_ppn, @@ -3539,5 +3569,5 @@ else // update page table but not TLB { - r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update + r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update #if DEBUG_DCACHE @@ -3574,5 +3604,5 @@ } //////////////////////// - case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit. + case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit. // We consume the response in rsp FIFO, // and exit the sub-fsm, but we don't @@ -3599,5 +3629,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if ( r_vci_rsp_data_error.read() ) // bus error { std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl; @@ -3620,5 +3650,5 @@ } /////////////////////// - case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type + case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type { #if DEBUG_DCACHE @@ -3634,5 +3664,5 @@ } /////////////////////// - case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written, + case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written, // and both itlb and dtlb must be flushed. // Caution : the itlb miss requests must be taken @@ -3676,5 +3706,5 @@ } ///////////////////// - case DCACHE_XTN_SYNC: // waiting until write buffer empty + case DCACHE_XTN_SYNC: // waiting until write buffer empty // The coherence request must be taken // as there is a risk of dead-lock @@ -3704,9 +3734,10 @@ } //////////////////////// - case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM - case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken - case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache - case DCACHE_XTN_IT_INVAL: // can generate an itlb miss, - // and because it can exist a simultaneous ITLB miss + case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM + case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken + case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache + case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss, + case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss + { // coherence clack request (from DSPIN CLACK) @@ -3744,5 +3775,5 @@ } ///////////////////////// - case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using + case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using // r_dcache_flush_count as a slot counter, // looping in this state until all slots have been visited. @@ -3845,5 +3876,5 @@ } ///////////////////////// - case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request + case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request { r_dtlb.inval(r_dcache_save_wdata.read()); @@ -3855,10 +3886,10 @@ case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address // requires 3 cycles: access tlb, read cache, inval cache - // we compute the physical address in this state + // we compute the physical address in this state { paddr_t paddr; bool hit; - if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated + if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated { @@ -3869,5 +3900,5 @@ &paddr ); } - else // dtlb not activated + else // dtlb not activated { paddr = (paddr_t)r_dcache_save_wdata.read(); @@ -3877,16 +3908,16 @@ } - if ( hit ) // tlb hit + if ( hit ) // tlb hit { r_dcache_save_paddr = paddr; r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; } - else // tlb miss - { + else // tlb miss + { #ifdef INSTRUMENTATION m_cpt_dtlb_miss++; #endif - r_dcache_tlb_ins = false; // dtlb + r_dcache_tlb_ins = false; // dtlb r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); r_dcache_fsm = DCACHE_TLB_MISS; @@ -3910,7 +3941,7 @@ // In this state we read dcache. { - size_t way; - size_t set; - size_t word; + size_t way; + size_t set; + size_t word; int state; @@ -3924,5 +3955,5 @@ &word ); - if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done { r_dcache_xtn_way = way; @@ -3930,5 +3961,5 @@ r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; } - else // miss : nothing to do + else // miss : nothing to do { r_dcache_fsm = DCACHE_IDLE; @@ -3951,11 +3982,11 @@ //////////////////////////// case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line - // Blocked if previous cleanup not completed + // Blocked if previous cleanup not completed // Test if itlb or dtlb inval is required { if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent { - size_t way = r_dcache_xtn_way.read(); - size_t set = r_dcache_xtn_set.read(); + size_t way = r_dcache_xtn_way.read(); + size_t set = r_dcache_xtn_set.read(); paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2); @@ -4004,9 +4035,9 @@ } #endif - } + } break; } ////////////////////////////// - case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request + case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request { r_dcache_fsm = DCACHE_IDLE; @@ -4108,5 +4139,5 @@ } /////////////////////// - case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state + case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state // and possibly request itlb or dtlb invalidate { @@ -4160,5 +4191,5 @@ } ////////////////////// - case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM + case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM // This state is in charge of error signaling // There is 5 types of error depending on the requester @@ -4192,5 +4223,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if ( r_vci_rsp_data_error.read() ) // bus error { switch ( r_dcache_miss_type.read() ) @@ -4246,17 +4277,17 @@ r_vci_rsp_data_error = false; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available + else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available { r_dcache_miss_word = 0; - r_dcache_fsm = DCACHE_MISS_DATA_UPDT; + r_dcache_fsm = DCACHE_MISS_DATA_UPDT; } break; } ////////////////////////// - case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) + case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) { if ( m_dreq.valid) m_cost_data_miss_frz++; - if ( r_vci_rsp_fifo_dcache.rok() ) // one word available + if ( r_vci_rsp_fifo_dcache.rok() ) // one word available { #ifdef INSTRUMENTATION @@ -4407,5 +4438,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if ( r_vci_rsp_data_error.read() ) // bus error { if(r_dcache_vci_unc_write.read()) @@ -4421,6 +4452,6 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // data available - { + else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + { // consume data vci_rsp_fifo_dcache_get = true; @@ -4430,9 +4461,9 @@ if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) { - m_drsp.valid = true; + m_drsp.valid = true; m_drsp.error = false; - m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); - } - } + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + } + } break; } @@ -4456,5 +4487,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if ( r_vci_rsp_data_error.read() ) // bus error { r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -4466,6 +4497,6 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // data available - { + else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + { // consume data vci_rsp_fifo_dcache_get = true; @@ -4488,9 +4519,9 @@ r_dcache_fsm = DCACHE_IDLE; } - } + } break; } //////////////////// - case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction + case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction { // coherence clack request (from DSPIN CLACK) @@ -4510,5 +4541,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if ( r_vci_rsp_data_error.read() ) // bus error { r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -4520,6 +4551,6 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // response available - { + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + { // consume response vci_rsp_fifo_dcache_get = true; @@ -4527,9 +4558,9 @@ m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); r_dcache_fsm = DCACHE_IDLE; - } + } break; } ////////////////////////// - case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory + case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory // before handling a processor WRITE or SC request // Input argument is r_dcache_dirty_paddr @@ -4937,5 +4968,5 @@ } /////////////////////////// - case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB + case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB // It makes assumption: m_itlb_sets == m_dtlb_sets // All ways are handled in parallel. @@ -4953,5 +4984,5 @@ // - r_dcache_fsm_scan_save { - paddr_t line = r_dcache_tlb_inval_line.read(); + paddr_t line = r_dcache_tlb_inval_line.read(); size_t set = r_dcache_tlb_inval_set.read(); size_t way; @@ -5010,6 +5041,6 @@ if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) ) { - m_cpt_frz_cycles++; // used for instrumentation - m_cpt_stop_simulation++; // used for debug + m_cpt_frz_cycles++; // used for instrumentation + m_cpt_stop_simulation++; // used for debug if ( m_cpt_stop_simulation > m_max_frozen_cycles ) { Index: branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/metadata/vci_simple_rom.sd =================================================================== --- branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/metadata/vci_simple_rom.sd (revision 656) +++ branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/metadata/vci_simple_rom.sd (revision 656) @@ -0,0 +1,42 @@ + +# -*- python -*- + +Module('caba:vci_simple_rom', + classname = 'soclib::caba::VciSimpleRom', + + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + ], + + header_files = [ + '../source/include/vci_simple_rom.h', + ], + + implementation_files = [ + '../source/src/vci_simple_rom.cpp', + ], + + ports = [ + Port('caba:vci_target', 'p_vci'), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:loader'), + Uses('common:mapping_table'), + ], + + instance_parameters = [ + parameter.IntTab('ident'), + parameter.Module('mt', 'common:mapping_table'), + parameter.Module('loader', 'common:loader', auto='env:loader'), + ], + extensions = [ + 'dsx:addressable=ident', + 'dsx:get_ident=ident:p_vci:mt', + 'dsx:obtain_ident_method=param:ident', + 'dsx:mapping_type=memory', + ], +) Index: branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/source/include/vci_simple_rom.h =================================================================== --- branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/source/include/vci_simple_rom.h (revision 656) +++ branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/source/include/vci_simple_rom.h (revision 656) @@ -0,0 +1,150 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * Alain Greiner , 2008 + * + * Maintainers: alain + */ + +//////////////////////////////////////////////////////////////////////////// +// This component is a multi-segments ROM controller. +// The VCI DATA can must be 32 bits or 64 bits. +// The VCI ADDRESS and the PLEN fields should be multiple of 4 bytes. +// It does not accept WRITE, LL, SC or CAS commands. +// A READ burst command packet (such a cache line request) +// contains one single flit. The number of flits in the response packet +// depends on the PLEN field: +// - If VCI DATA width = 32 bits, each flit contains 4 bytes, and the +// number of flits is PLEN/4. +// - If VCI DATA width = 64 bits, and PLEN define an even number of words, +// each flit contains 8 bytes, and the number of flits is PLEN/8. +// - If VCI DATA width = 64 bits, and PLEN define an odd number of words, +// the last flit contains only 4 bytes right justified, +// and the number of flits is PLEN/8 + 1. +//////////////////////////////////////////////////////////////////////////// +// Implementation note: +// The ROM segments are implemented as a set of uint32_t arrays +// (one array per segment). +// This component is controlled by a single FSM. +// The VCI command is analysed and checked in the IDLE state. +// The response is sent in the READ (or ERROR) state. +///////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_VCI_SIMPLE_ROM_H +#define SOCLIB_CABA_VCI_SIMPLE_ROM_H + +#include +#include +#include +#include +#include "caba_base_module.h" +#include "vci_target.h" +#include "mapping_table.h" +#include "int_tab.h" +#include "loader.h" +#include "soclib_endian.h" + +namespace soclib { +namespace caba { + +using namespace sc_core; + +template +class VciSimpleRom + : public soclib::caba::BaseModule +{ +public: + + typedef typename vci_param::fast_data_t vci_data_t; + typedef typename vci_param::srcid_t vci_srcid_t; + typedef typename vci_param::trdid_t vci_trdid_t; + typedef typename vci_param::pktid_t vci_pktid_t; + + enum fsm_state_e + { + FSM_IDLE, + FSM_RSP_READ, + FSM_RSP_ERROR, + }; + +private: + + const soclib::common::Loader &m_loader; + std::list m_seglist; + int m_drop_msb; + + sc_signal r_fsm_state; + sc_signal r_flit_count; + sc_signal r_odd_words; + sc_signal r_seg_index; + sc_signal r_rom_index; + sc_signal r_srcid; + sc_signal r_trdid; + sc_signal r_pktid; + + size_t m_nbseg; + uint32_t **m_rom; + soclib::common::Segment **m_seg; + +protected: + + SC_HAS_PROCESS(VciSimpleRom); + +public: + + // Ports + sc_in p_resetn; + sc_in p_clk; + soclib::caba::VciTarget p_vci; + + VciSimpleRom(sc_module_name name, + const soclib::common::IntTab index, + const soclib::common::MappingTable &mt, + const soclib::common::Loader &loader, + const int nb_msb_drop = 0); + + ~VciSimpleRom(); + + void print_trace(); + +private: + + void transition(); + void genMoore(); + void reload(); + void reset(); +}; + +}} + +#endif + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/source/src/vci_simple_rom.cpp =================================================================== --- branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/source/src/vci_simple_rom.cpp (revision 656) +++ branches/fault_tolerance/module/internal_component/vci_simple_rom/caba/source/src/vci_simple_rom.cpp (revision 656) @@ -0,0 +1,318 @@ +/* + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * Alain Greiner , 2008 + * + * Maintainers: alain + */ + +#include +#include +#include "arithmetics.h" +#include "vci_simple_rom.h" + +namespace soclib { +namespace caba { + +using namespace soclib; + +#define tmpl(x) template x VciSimpleRom + +////////////////////////// +tmpl(/**/)::VciSimpleRom( + sc_module_name name, + const soclib::common::IntTab index, + const soclib::common::MappingTable &mt, + const soclib::common::Loader &loader, + const int nb_msb_drop) + : caba::BaseModule(name), + m_loader(loader), + m_seglist(mt.getSegmentList(index)), + m_drop_msb(nb_msb_drop), + + r_fsm_state("r_fsm_state"), + r_flit_count("r_flit_count"), + r_odd_words("r_odd_words"), + r_seg_index("r_seg_index"), + r_rom_index("r_rom_index"), + r_srcid("r_srcid"), + r_trdid("r_trdid"), + r_pktid("r_pktid"), + + p_resetn("p_resetn"), + p_clk("p_clk"), + p_vci("p_vci") +{ + std::cout << " - Building SimpleRom " << name << std::endl; + + size_t nsegs = 0; + + assert( (m_seglist.empty() == false) and + "VCI_SIMPLE_ROM error : no segment allocated"); + + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; + nsegs++; + } + + m_nbseg = nsegs; + + assert( ((vci_param::B == 4) or (vci_param::B == 8)) and + "VCI_SIMPLE_ROM error : The VCI DATA field must be 32 or 64 bits"); + + // actual memory allocation + m_rom = new uint32_t*[m_nbseg]; + m_seg = new soclib::common::Segment*[m_nbseg]; + + size_t i = 0; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + m_rom[i] = new uint32_t[ (seg->size()+3)/4 ]; + m_seg[i] = &(*seg); + i++; + } + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); +} + +/////////////////////////// +tmpl(/**/)::~VciSimpleRom() +{ + for (size_t i=0 ; ibaseAddress() & mask; + m_loader.load(&m_rom[i][0], base_address, m_seg[i]->size()); + for ( size_t addr = 0 ; addr < m_seg[i]->size()/vci_param::B ; ++addr ) + m_rom[i][addr] = le_to_machine(m_rom[i][addr]); + } +} + +//////////////////// +tmpl(void)::reset() +{ + for ( size_t i=0 ; isize()); + r_fsm_state = FSM_IDLE; +} + +////////////////////////// +tmpl(void)::print_trace() +{ + const char* state_str[] = { "IDLE", "READ", "ERROR" }; + std::cout << "SIMPLE_ROM " << name() + << " : state = " << state_str[r_fsm_state] + << " / flit_count = " << std::dec << r_flit_count << std::endl; +} + +///////////////////////// +tmpl(void)::transition() +{ + if (!p_resetn) + { + reset(); + reload(); + return; + } + + switch ( r_fsm_state ) + { + ////////////// + case FSM_IDLE: // waiting a VCI command + { + if ( p_vci.cmdval.read() ) + { + bool error = true; + + assert( ((p_vci.address.read() & 0x3) == 0) and + "VCI_SIMPLE_ROM ERROR : The VCI ADDRESS must be multiple of 4"); + + assert( ((p_vci.plen.read() & 0x3) == 0) and + "VCI_SIMPLE_ROM ERROR : The VCI PLEN must be multiple of 4"); + + assert( (p_vci.plen.read() != 0) and + "VCI_SIMPLE_ROM ERROR : The VCI PLEN should be != 0"); + + assert( (p_vci.cmd.read() == vci_param::CMD_READ) and + "VCI_SIMPLE_ROM ERROR : The VCI command must be a READ"); + + assert( p_vci.eop.read() and + "VCI_SIMPLE_ROM ERROR : The VCI command packet must be 1 flit"); + + for ( size_t index = 0 ; indexcontains(p_vci.address.read())) and + (m_seg[index]->contains(p_vci.address.read()+p_vci.plen.read()-1)) ) + { + error = false; + r_seg_index = index; + } + } + + if ( error ) + { + r_fsm_state = FSM_RSP_ERROR; + } + else + { + unsigned int plen = p_vci.plen.read(); + + r_fsm_state = FSM_RSP_READ; + r_srcid = p_vci.srcid.read(); + r_trdid = p_vci.trdid.read(); + r_pktid = p_vci.pktid.read(); + r_rom_index = (size_t)((p_vci.address.read() - + m_seg[r_seg_index.read()]->baseAddress())>>2); + + if ( vci_param::B == 8 ) // 64 bits data width + { + if ( plen & 0x4 ) // odd number of words + { + r_flit_count = (plen>>3) + 1; + r_odd_words = true; + } + else // even number of words + { + r_flit_count = plen>>3; + r_odd_words = false; + } + } + else // 32 bits data width + { + r_flit_count = plen>>2; + } + } + } + break; + } + ////////////////// + case FSM_RSP_READ: // send one response flit + { + if ( p_vci.rspack.read() ) + { + r_flit_count = r_flit_count - 1; + r_rom_index = r_rom_index.read() + (vci_param::B>>2); + if ( r_flit_count.read() == 1) r_fsm_state = FSM_IDLE; + } + break; + } + /////////////////// + case FSM_RSP_ERROR: // waits lat flit of a VCI CMD erroneous packet + { + if ( p_vci.rspack.read() && p_vci.eop.read() ) + { + r_fsm_state = FSM_IDLE; + } + break; + } + } // end switch fsm_state + +} // end transition() + +/////////////////////// +tmpl(void)::genMoore() +{ + switch ( r_fsm_state.read() ) + { + case FSM_IDLE: + { + p_vci.cmdack = true; + p_vci.rspval = false; + p_vci.rdata = 0; + p_vci.rsrcid = 0; + p_vci.rtrdid = 0; + p_vci.rpktid = 0; + p_vci.rerror = 0; + p_vci.reop = false; + break; + } + case FSM_RSP_READ: + { + vci_data_t rdata; + size_t seg_index = r_seg_index.read(); + size_t rom_index = r_rom_index.read(); + + if ( (vci_param::B == 4) or // 32 bits data + ( r_odd_words.read() and (r_flit_count.read() == 1)) ) // last odd flit + { + rdata = (vci_data_t)m_rom[seg_index][rom_index]; + } + else // 64 bits data + { + rdata = (uint64_t)m_rom[seg_index][rom_index] | + (((uint64_t)m_rom[seg_index][rom_index+1]) << 32); + } + + p_vci.cmdack = false; + p_vci.rspval = true; + p_vci.rdata = rdata; + p_vci.rsrcid = r_srcid.read(); + p_vci.rtrdid = r_trdid.read(); + p_vci.rpktid = r_pktid.read(); + p_vci.rerror = vci_param::ERR_NORMAL; + p_vci.reop = (r_flit_count.read() == 1); + break; + } + case FSM_RSP_ERROR: + { + p_vci.cmdack = false; + p_vci.rspval = true; + p_vci.rdata = 0; + p_vci.rsrcid = r_srcid.read(); + p_vci.rtrdid = r_trdid.read(); + p_vci.rpktid = r_pktid.read(); + p_vci.rerror = vci_param::ERR_GENERAL_DATA_ERROR; + p_vci.reop = true; + break; + } + } // end switch fsm_state +} // end genMoore() + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 +