Index: branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 671)
+++ branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 673)
@@ -3099,4 +3099,7 @@
                         r_read_ll_done  = true;
                     }
+
+                    bool s_getm_hit         = m_cmd_read_pktid_fifo.read() & 0x8;
+
                     r_read_is_cnt           = entry.is_cnt;
                     r_read_dirty            = entry.dirty;
@@ -3120,5 +3123,7 @@
                         {
                                 // Invalid the line in the others processors and put the line in trt with data.
-                                if( entry.count == 0 or ((entry.count == 1) and (entry.state == ENTRY_SHARED) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read())))
+                                if( (entry.count == 0) or 
+                                    ((entry.count == 1) and not entry.is_cnt and (entry.state == ENTRY_SHARED) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) or
+                                    (entry.count == 1 and entry.is_cnt and entry.state == ENTRY_SHARED and s_getm_hit))
                                 {
                                     r_read_fsm = READ_DIR_HIT;
@@ -3622,7 +3627,7 @@
                         entry.lock   = r_read_lock.read();
                         entry.count  = r_read_count.read() + 1;
-                    
-                        r_read_shared = true;
-
+
+                        r_read_shared = true;  //ack to cache L1 with shared state
+    
                         if(not go_cnt)         // Not entering counter mode
                         {
@@ -5078,4 +5083,10 @@
                     if( not r_write_to_ixr_cmd_req.read() )
                     {
+                        if((r_write_state.read() == ENTRY_EXCLUSIVE) and (r_write_count.read() == 1))
+                        {
+                            std::cout << "can't send a trt req when the line state is exlusive"<< std::endl;
+                            exit(0);
+                        }
+ 
                         r_write_to_ixr_cmd_req     = true;
                         r_write_to_ixr_cmd_index   = r_write_trt_index.read();
@@ -6060,4 +6071,9 @@
                     if ( not r_xram_rsp_to_ixr_cmd_req.read() )
                     {
+                        if((r_xram_rsp_victim_state.read() == ENTRY_EXCLUSIVE) and (r_xram_rsp_victim_count.read() == 1))
+                        {
+                            std::cout << "can't send a trt req when the line state is exlusive" << std::endl;
+                            exit(0);
+                        }
                         r_xram_rsp_to_ixr_cmd_req = true;
                         r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read();
@@ -7218,5 +7234,5 @@
                             r_cleanup_to_ixr_cmd_req     = true;
 
-                            if( (r_write_to_cleanup_req == true) and (r_write_to_cleanup_nline == r_cleanup_nline.read()) )
+                            if( (r_write_to_cleanup_req == true) and (r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) )
                             {
                                 r_write_to_cleanup_req   = false;