Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 672)
+++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 674)
@@ -1295,5 +1295,5 @@
                     r_icache_fsm      = ICACHE_MISS_SELECT;
 #if DEBUG_ICACHE
-if ( m_debug_activated )
+if ( m_debug_activated or m_ireq.addr == 0x11020 )
 std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 
           << " : PADDR = " << std::hex << paddr << std::endl;
@@ -2100,10 +2100,11 @@
 
         // coherence request completed
-        r_icache_cc_send_req   = true;
-        r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
-        r_icache_cc_send_way   = r_icache_cc_way.read();
-        r_icache_cc_send_type  = CC_TYPE_CLEANUP;
-
-        r_icache_fsm           = r_icache_fsm_save.read();
+        r_icache_cc_send_req    = true;
+        r_icache_cc_send_nline  = r_cc_receive_icache_nline.read();
+        r_icache_cc_send_way    = r_icache_cc_way.read();
+        r_icache_cc_send_type   = CC_TYPE_CLEANUP;
+
+        r_icache_fsm            = r_icache_fsm_save.read();
+        r_cc_receive_icache_req = false;
 
 #if DEBUG_ICACHE
@@ -2821,5 +2822,5 @@
                                     m_drsp.rdata   = cache_rdata;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
+if ( m_debug_activated or m_drsp.rdata == 0x11020)
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
           << " READ HIT in dcache" 
@@ -2967,5 +2968,5 @@
                     }
 #if DEBUG_DCACHE
-if ( m_debug_activated )
+if ( m_debug_activated or m_dreq.wdata == 0x11020)
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
       << " WRITE REQ " 
@@ -5620,7 +5621,8 @@
     }
     } // end switch r_dcache_fsm
-if(r_dcache_miss_updt.read())
-std::cout << "  <PROC " << name() 
-          << " miss updt " << r_dcache_miss_updt.read() << std::endl;
+
+//if(r_dcache_miss_updt.read())
+//std::cout << "  <PROC " << name() 
+//          << " miss updt " << r_dcache_miss_updt.read() << std::endl;
 
 //std::cout << "  <PROC " << name() 
@@ -6265,6 +6267,6 @@
                 r_cc_receive_dcache_srcid = DspinDhccpParam::dspin_get(receive_data,
                                             DspinDhccpParam::BROADCAST_SRCID);
-            }
-            r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
+                r_cc_receive_fsm          = CC_RECEIVE_BRDCAST_NLINE;
+            }
             break;
         }
@@ -6278,7 +6280,10 @@
             // not to actually post a request to an available cache => need a
             // flip_flop to check that ?
-            if (not (r_cc_receive_icache_req.read()) and 
-                not (r_cc_receive_dcache_req.read()) and
-                (p_dspin_m2p.write.read()))
+            if (r_cc_receive_icache_req.read() or r_cc_receive_dcache_req.read())
+            {   
+                std::cout << "illege flags for handling brdcast request" << std::endl;
+                exit(0);
+            }
+            if(p_dspin_m2p.write.read())
             {
                 // request dcache to handle the BROADCAST
@@ -6296,4 +6301,5 @@
                 break;
             }
+
             // keep waiting for the caches to accept the request
             break;
@@ -6846,13 +6852,4 @@
         case CC_RECEIVE_BRDCAST_HEADER:
         {
-            p_dspin_m2p.read = true;
-            break;
-        }
-        //////////////////////////////
-        case CC_RECEIVE_BRDCAST_NLINE:
-        {
-            // TODO maybe we need to wait for both only to leave the state, but
-            // not to actually post a request to an available cache => need a
-            // flip_flop to check that ?
             if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
                 p_dspin_m2p.read = true;
@@ -6860,4 +6857,14 @@
                 p_dspin_m2p.read = false;
             break;
+        }
+        //////////////////////////////
+        case CC_RECEIVE_BRDCAST_NLINE:
+        {
+            // TODO maybe we need to wait for both only to leave the state, but
+            // not to actually post a request to an available cache => need a
+            // flip_flop to check that ?
+            p_dspin_m2p.read = true;
+            break;
+
         }
         /////////////////////////////
