Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 674) +++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 675) @@ -133,4 +133,5 @@ DCACHE_MISS_DATA_UPDT, DCACHE_MISS_DIR_UPDT, + DCACHE_MISS_BACKOFF, // handling processor unc, ll and sc requests DCACHE_UNC_WAIT, @@ -470,4 +471,8 @@ sc_signal r_dcache_miss_updt; // cc updt request matching a miss sc_signal r_dcache_miss_clack; // waiting for a cleanup acknowledge + + + sc_signal r_dcache_count_backoff; // selected set for cache update + sc_signal r_dcache_count_begin; // selected set for cache update // handling coherence requests @@ -620,4 +625,5 @@ sc_signal r_cc_receive_dcache_srcid; // cc_receive to dcache set sc_signal r_cc_receive_brdcast; // is brdcast + sc_signal r_cc_receive_dcache_is_shared; // the line state in memcache /////////////////////////////////// Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 674) +++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 675) @@ -106,4 +106,5 @@ "DCACHE_MISS_DATA_UPDT", "DCACHE_MISS_DIR_UPDT", + "DCACHE_MISS_BACKOFF", "DCACHE_UNC_WAIT", @@ -385,5 +386,5 @@ r_vci_rsp_data_error("r_vci_rsp_data_error"), r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth - r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth + r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16), // 2 words depth // r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth r_cc_send_data_fifo("r_cc_send_data_fifo", 16), @@ -872,4 +873,6 @@ r_dcache_xtn_flush_data_cpt = 0; r_dcache_cc_inval_data_cpt = 0; + r_dcache_count_backoff = 0; + r_dcache_count_begin = 0; r_dcache_cleanup_victim_req = false; @@ -2295,4 +2298,12 @@ { +//#if 1 +// // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE +// if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { +// std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; +// raise(SIGINT); +// } +//#endif + if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated { @@ -2439,5 +2450,5 @@ } // coherence request (from CC_RECEIVE FSM) - else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_miss_updt.read()) + else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -2449,5 +2460,4 @@ else if ( m_dreq.valid ) { - r_dcache_miss_updt = false; // register processor request and DCACHE response r_dcache_save_vaddr = m_dreq.addr; @@ -3121,5 +3131,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_miss_updt.read()) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3128,5 +3138,4 @@ } - r_dcache_miss_updt = false; uint32_t entry; size_t way; @@ -3437,5 +3446,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_miss_updt.read()) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3444,5 +3453,4 @@ } - r_dcache_miss_updt = false; uint32_t pte_flags = 0; uint32_t pte_ppn = 0; @@ -4747,5 +4755,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_updt.read()) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_inval.read() and not r_dcache_miss_updt.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4754,26 +4762,25 @@ } - if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge + if ( not r_dcache_miss_clack.read() and not r_dcache_cc_send_req.read()) // waiting cleanup acknowledge { if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup { - if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent - { - r_dcache_miss_inval = false; - // request cleanup - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); - r_dcache_cc_send_way = r_dcache_miss_way.read(); - r_dcache_cc_send_type = CC_TYPE_CLEANUP; - r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. - r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line + r_dcache_miss_inval = false; + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); + r_dcache_cc_send_way = r_dcache_miss_way.read(); + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. + r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line #ifdef INSTRUMENTATION m_cpt_dcache_dir_write++; #endif - r_dcache.write_dir( r_dcache_save_paddr.read(), - r_dcache_miss_way.read(), - r_dcache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + r_dcache.write_dir( r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI ); + #if DEBUG_DCACHE if ( m_debug_activated ) @@ -4784,7 +4791,26 @@ << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif + + if( not r_dcache_miss_updt.read()) + { + r_dcache_fsm = DCACHE_MISS_BACKOFF; + r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; + r_dcache_count_begin = 0; } - else - break; + break; + } + else if( r_dcache_miss_updt.read()) + { + r_dcache_miss_updt = false; + r_cc_receive_dcache_req = false; + r_dcache_cc_send_req = true; + r_dcache_cc_send_multi_ack_miss = true; + r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); + r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); + r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; + + r_dcache_fsm = DCACHE_MISS_BACKOFF; + r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; + r_dcache_count_begin = 0; } else // switch slot to VALID state @@ -4794,5 +4820,5 @@ m_cpt_dcache_dir_write++; #endif - + r_dcache_count_backoff = 0; size_t way = r_dcache_miss_way.read(); size_t set = r_dcache_miss_set.read(); @@ -4822,12 +4848,32 @@ #endif // reset directory extension - - } + if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; + else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; + else r_dcache_fsm = DCACHE_IDLE; + } + } + break; + } + ///////////////////// + case DCACHE_MISS_BACKOFF: + { + size_t count_max = r_dcache_count_backoff.read() << 4; + r_dcache_count_begin = r_dcache_count_begin.read() + 1; + if(r_dcache_count_begin.read() == count_max) + { if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; else r_dcache_fsm = DCACHE_IDLE; } - break; - } + break; +#if DEBUG_DCACHE +if ( m_debug_activated ) +std::cout << " operation back off" + << std::endl; +#endif + + } + ///////////////////// case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read @@ -5245,29 +5291,19 @@ { - if(r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST and r_dcache_read_for_modify.read() and - r_cc_receive_dcache_srcid.read() == m_srcid and (r_dcache_miss_type.read() == PROC_MISS)) - { + if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) + { + r_dcache_fsm = DCACHE_CC_INVAL; + } + else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + r_dcache_miss_updt = true; + r_dcache_miss_inval = true; + } + else + { + r_dcache_miss_inval = true; r_cc_receive_dcache_req = false; r_dcache_fsm = r_dcache_fsm_cc_save.read(); - } - else if(r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST and - r_dcache_read_for_modify.read() and - r_cc_receive_dcache_srcid.read() != m_srcid and - (r_dcache_miss_type.read() == PROC_MISS) and - (state == CACHE_SLOT_STATE_SHARED)) - { - r_dcache_fsm = DCACHE_CC_INVAL; - } - else if(r_cc_receive_dcache_type.read() == CC_TYPE_INVAL and r_dcache_read_for_modify.read() and - (r_dcache_miss_type.read() == PROC_MISS) and - (state == CACHE_SLOT_STATE_SHARED)) - { - r_dcache_fsm = DCACHE_CC_INVAL; - } - else - { - r_dcache_miss_inval = false; - r_dcache_miss_updt = true; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); } // signaling matching @@ -5622,11 +5658,4 @@ } // end switch r_dcache_fsm -//if(r_dcache_miss_updt.read()) -//std::cout << " r_read_to_cc_send_brdcast_req; // bd inval sc_signal r_read_to_cc_send_type; //cc inval or cc updt + sc_signal r_read_to_cc_send_is_shared; //line is or not shared //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) @@ -1039,4 +1040,5 @@ sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid sc_signal r_cleanup_to_tgt_rsp_ll_key; + sc_signal r_cleanup_to_tgt_rsp_nline; sc_signal r_cleanup_to_tgt_rsp_type; Index: branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 674) +++ branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 675) @@ -3195,12 +3195,7 @@ bool last_multi_req = multi_req and (r_read_count.read() == 1); bool not_last_multi_req = multi_req and (r_read_count.read() != 1); - bool match_send = (r_read_copy.read() == m_cmd_read_srcid_fifo.read()) and - (r_read_copy_inst.read() == 0); - - if(last_multi_req and match_send) - { - std::cout << "last_multi_req and match srcid are true" << std::endl; - exit(0); - } + //bool match_send = (r_read_copy.read() == m_cmd_read_srcid_fifo.read()) and + // (r_read_copy_inst.read() == 0); + size_t ivt_send_count = 0; @@ -3240,4 +3235,6 @@ r_read_to_cc_send_nline = nline; r_read_to_cc_send_srcid = m_cmd_read_srcid_fifo.read(); + r_read_to_cc_send_is_shared = r_read_state.read() == ENTRY_SHARED; + if(r_read_need_block.read()) { @@ -3248,18 +3245,19 @@ r_read_to_cleanup_req = true; } - r_read_to_cc_send_type = true; - - if(not match_send) - { - read_to_cc_send_fifo_srcid = r_read_copy.read(); - read_to_cc_send_fifo_inst = r_read_copy_inst.read(); - read_to_cc_send_fifo_put = multi_req; - } + r_read_to_cc_send_type = true; //CC_INVAL + + // if(not match_send) + // { + read_to_cc_send_fifo_srcid = r_read_copy.read(); + read_to_cc_send_fifo_inst = r_read_copy_inst.read(); + read_to_cc_send_fifo_put = multi_req; + // } r_read_next_ptr = r_read_ptr.read(); - if(((m_cmd_read_pktid_fifo.read() & 0x8) == 0x8) and (r_read_state.read() == ENTRY_SHARED)) - ivt_send_count = r_read_count.read() - 1; - else - ivt_send_count = r_read_count.read(); + // if(((m_cmd_read_pktid_fifo.read() & 0x8) == 0x8) and (r_read_state.read() == ENTRY_SHARED)) + // ivt_send_count = r_read_count.read() - 1; + // else + // ivt_send_count = r_read_count.read(); + m_ivt.set(false, // it's an inval transaction not multi_req, // multi_inval or brdcast @@ -3270,5 +3268,5 @@ m_cmd_read_pktid_fifo.read() & 0x7, nline, - ivt_send_count, + r_read_count.read(), index); @@ -3318,12 +3316,12 @@ HeapEntry entry = m_heap.read(r_read_next_ptr.read()); - bool match_send = ( entry.owner.srcid == m_cmd_read_srcid_fifo.read()) and - ( entry.owner.inst == 0); - if(not match_send) - { - read_to_cc_send_fifo_srcid = entry.owner.srcid; - read_to_cc_send_fifo_inst = entry.owner.inst; - read_to_cc_send_fifo_put = true; - } + // bool match_send = ( entry.owner.srcid == m_cmd_read_srcid_fifo.read()) and + // ( entry.owner.inst == 0); + // if(not match_send) + // { + read_to_cc_send_fifo_srcid = entry.owner.srcid; + read_to_cc_send_fifo_inst = entry.owner.inst; + read_to_cc_send_fifo_put = true; + // } // if(read_to_cc_send_inst_fifo.wok()) always not full r_read_next_ptr = entry.next; @@ -3435,5 +3433,5 @@ r_read_to_cc_send_brdcast_req = false; r_read_to_cc_send_nline = nline; - r_read_to_cc_send_type = false; + r_read_to_cc_send_type = false; //CC_UPDT read_to_cc_send_fifo_srcid = r_read_copy.read(); @@ -6781,4 +6779,5 @@ r_cleanup_to_tgt_rsp_srcid = r_cleanup_locked_srcid.read(); r_cleanup_to_tgt_rsp_trdid = r_cleanup_locked_trdid.read(); + r_cleanup_to_tgt_rsp_nline = r_cleanup_nline.read(); r_cleanup_to_tgt_rsp_pktid = 0x8 + r_cleanup_locked_pktid.read(); // there is not a brdcast for cas operation. in cache L1, the line can be in M state @@ -8279,4 +8278,7 @@ case CC_SEND_CONFIG_IDLE: // XRAM_RSP FSM has highest priority { + bool cc_send_updt_delay = not r_read_to_cc_send_type.read() and r_tgt_rsp_fsm.read() == TGT_RSP_CLEANUP and + r_read_to_cc_send_nline.read() == r_cleanup_to_tgt_rsp_nline.read() and + m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); // XRAM_RSP if(m_xram_rsp_to_cc_send_inst_fifo.rok() or @@ -8305,6 +8307,6 @@ // READ - if(m_read_to_cc_send_inst_fifo.rok() or - r_read_to_cc_send_multi_req.read()) + if((m_read_to_cc_send_inst_fifo.rok() or + r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) { r_cc_send_fsm = CC_SEND_READ_MULTI_HEADER; @@ -8351,4 +8353,7 @@ case CC_SEND_WRITE_IDLE: // CONFIG FSM has highest priority { + bool cc_send_updt_delay = not r_read_to_cc_send_type.read() and r_tgt_rsp_fsm.read() == TGT_RSP_CLEANUP and + r_read_to_cc_send_nline.read() == r_cleanup_to_tgt_rsp_nline.read() and + m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); // CONFIG if(r_config_to_cc_send_multi_req.read()) @@ -8387,6 +8392,6 @@ } // READ - if(m_read_to_cc_send_inst_fifo.rok() or - r_read_to_cc_send_multi_req.read()) + if((m_read_to_cc_send_inst_fifo.rok() or + r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) { r_cc_send_fsm = CC_SEND_READ_MULTI_HEADER; @@ -8420,4 +8425,7 @@ case CC_SEND_XRAM_RSP_IDLE: // CAS FSM has highest priority { + bool cc_send_updt_delay = not r_read_to_cc_send_type.read() and r_tgt_rsp_fsm.read() == TGT_RSP_CLEANUP and + r_read_to_cc_send_nline.read() == r_cleanup_to_tgt_rsp_nline.read() and + m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); // CAS if(m_cas_to_cc_send_inst_fifo.rok() or @@ -8433,6 +8441,6 @@ } // READ - if(m_read_to_cc_send_inst_fifo.rok() or - r_read_to_cc_send_multi_req.read()) + if((m_read_to_cc_send_inst_fifo.rok() or + r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) { r_cc_send_fsm = CC_SEND_READ_MULTI_HEADER; @@ -8484,7 +8492,10 @@ case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority { + bool cc_send_updt_delay = not r_read_to_cc_send_type.read() and r_tgt_rsp_fsm.read() == TGT_RSP_CLEANUP and + r_read_to_cc_send_nline.read() == r_cleanup_to_tgt_rsp_nline.read() and + m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); // READ - if(m_read_to_cc_send_inst_fifo.rok() or - r_read_to_cc_send_multi_req.read()) + if((m_read_to_cc_send_inst_fifo.rok() or + r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) { r_cc_send_fsm = CC_SEND_READ_MULTI_HEADER; @@ -8548,4 +8559,7 @@ case CC_SEND_READ_IDLE: // WRITE FSM has highest priority { + bool cc_send_updt_delay = not r_read_to_cc_send_type.read() and r_tgt_rsp_fsm.read() == TGT_RSP_CLEANUP and + r_read_to_cc_send_nline.read() == r_cleanup_to_tgt_rsp_nline.read() and + m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); //WRITE if(m_write_to_cc_send_inst_fifo.rok() or @@ -8596,6 +8610,6 @@ } // READ - if(m_read_to_cc_send_inst_fifo.rok() or - r_read_to_cc_send_multi_req.read()) + if((m_read_to_cc_send_inst_fifo.rok() or + r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) { r_cc_send_fsm = CC_SEND_READ_MULTI_HEADER; @@ -8613,4 +8627,5 @@ case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) { + if(m_config_to_cc_send_inst_fifo.rok()) { @@ -11499,5 +11514,5 @@ DspinDhccpParam::dspin_set( flit, 1, - DspinDhccpParam::MULTI_INVAL_IS_CONFIG); + DspinDhccpParam::BRDCAST_IS_CONFIG); DspinDhccpParam::dspin_set( flit, @@ -11546,4 +11561,8 @@ r_read_to_cc_send_srcid.read(), // send the srcid itself which demands the request getM DspinDhccpParam::BROADCAST_SRCID); + + DspinDhccpParam::dspin_set( flit, + r_read_to_cc_send_is_shared.read(), // send the actuel line state in memcache + DspinDhccpParam::BRDCAST_IS_SHARED); DspinDhccpParam::dspin_set( flit, @@ -11618,6 +11637,6 @@ DspinDhccpParam::dspin_set( flit, - r_read_to_cc_send_srcid.read(), - DspinDhccpParam::MULTI_INVAL_SRCID); + r_read_to_cc_send_is_shared.read(), + DspinDhccpParam::MULTI_INVAL_IS_SHARED); if(r_read_to_cc_send_type.read())