Changeset 677 for branches/MESI
- Timestamp:
- Apr 14, 2014, 2:15:01 PM (11 years ago)
- Location:
- branches/MESI/modules
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r675 r677 2298 2298 { 2299 2299 2300 //#if 12301 //// @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE2302 //if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {2303 //std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl;2304 //raise(SIGINT);2305 //}2306 //#endif2300 #if 1 2301 // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE 2302 if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { 2303 std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; 2304 raise(SIGINT); 2305 } 2306 #endif 2307 2307 2308 2308 if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated … … 4616 4616 4617 4617 // coherence request (from CC_RECEIVE FSM) 4618 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_updt.read())4618 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) 4619 4619 { 4620 4620 r_dcache_fsm = DCACHE_CC_CHECK; … … 4755 4755 4756 4756 // coherence request (from CC_RECEIVE FSM) 4757 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() and not r_dcache_miss_inval.read() and not r_dcache_miss_updt.read())4757 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) 4758 4758 { 4759 4759 r_dcache_fsm = DCACHE_CC_CHECK; … … 4762 4762 } 4763 4763 4764 if ( not r_dcache_miss_clack.read() and not r_dcache_cc_send_req.read()) // waiting cleanup acknowledge4764 if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge 4765 4765 { 4766 4766 if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup 4767 4767 { 4768 r_dcache_miss_inval = false; 4769 // request cleanup 4770 r_dcache_cc_send_req = true; 4771 r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); 4772 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4773 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4774 r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. 4775 r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line 4768 if(not r_dcache_cc_send_req.read()) 4769 { 4770 r_dcache_miss_inval = false; 4771 // request cleanup 4772 r_dcache_cc_send_req = true; 4773 r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); 4774 r_dcache_cc_send_way = r_dcache_miss_way.read(); 4775 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4776 r_dcache_cc_line_dirty = false; // in case of miss inval, the cleanup is not with data. 4777 r_dcache_cc_line_no_shared = r_dcache_rsp_state.read(); // the miss read rsp contents the state of this line 4776 4778 4777 4779 #ifdef INSTRUMENTATION 4778 4780 m_cpt_dcache_dir_write++; 4779 4781 #endif 4780 r_dcache.write_dir( r_dcache_save_paddr.read(),4781 r_dcache_miss_way.read(),4782 r_dcache_miss_set.read(),4783 CACHE_SLOT_STATE_ZOMBI );4782 r_dcache.write_dir( r_dcache_save_paddr.read(), 4783 r_dcache_miss_way.read(), 4784 r_dcache_miss_set.read(), 4785 CACHE_SLOT_STATE_ZOMBI ); 4784 4786 4785 4787 #if DEBUG_DCACHE … … 4792 4794 #endif 4793 4795 4794 if( not r_dcache_miss_updt.read())4795 {4796 4796 r_dcache_fsm = DCACHE_MISS_BACKOFF; 4797 4797 r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; 4798 4798 r_dcache_count_begin = 0; 4799 4799 } 4800 break; 4801 } 4802 else if( r_dcache_miss_updt.read()) 4803 { 4804 r_dcache_miss_updt = false; 4805 r_cc_receive_dcache_req = false; 4806 r_dcache_cc_send_req = true; 4807 r_dcache_cc_send_multi_ack_miss = true; 4808 r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); 4809 r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); 4810 r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; 4811 4812 r_dcache_fsm = DCACHE_MISS_BACKOFF; 4813 r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; 4814 r_dcache_count_begin = 0; 4800 else 4801 { 4802 break; 4803 } 4815 4804 } 4816 4805 else // switch slot to VALID state … … 5293 5282 if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) 5294 5283 { 5295 r_dcache_fsm = DCACHE_CC_INVAL; 5284 r_dcache_miss_clack = true; 5285 r_dcache_fsm = DCACHE_CC_INVAL; 5296 5286 } 5297 5287 else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 5298 5288 { 5299 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5300 r_dcache_miss_updt = true; 5289 assert((state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI) && " CC_UPDT WITH A NO INVALID STATE"); 5290 5291 r_dcache_cc_send_multi_ack_miss = true; 5301 5292 r_dcache_miss_inval = true; 5293 r_dcache_fsm = DCACHE_CC_UPDT; 5302 5294 } 5303 5295 else … … 5389 5381 r_dcache_cc_send_multi_ack_miss = false; 5390 5382 } 5391 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL or r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) // hit inval5383 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval 5392 5384 { 5393 5385 r_dcache_fsm = DCACHE_CC_INVAL; … … 6327 6319 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, 6328 6320 DspinDhccpParam::BROADCAST_NLINE); 6329 r_cc_receive_dcache_type = CC_TYPE_ BRDCAST;6321 r_cc_receive_dcache_type = CC_TYPE_INVAL; 6330 6322 // request icache to handle the BROADCAST 6331 6323 r_cc_receive_icache_req = true; -
branches/MESI/modules/vci_mem_cache/caba/source/include/update_tab.h
r670 r677 27 27 addr_t nline; // The identifier of the cache line 28 28 size_t count; // The number of acknowledge responses to receive 29 bool is_change; // multi ack miss req sends this bit to 1 29 30 30 31 UpdateTabEntry() 31 32 { 32 valid = false; 33 update = false; 34 brdcast = false; 35 rsp = false; 36 ack = false; 37 srcid = 0; 38 trdid = 0; 39 pktid = 0; 40 nline = 0; 41 count = 0; 33 valid = false; 34 update = false; 35 brdcast = false; 36 rsp = false; 37 ack = false; 38 srcid = 0; 39 trdid = 0; 40 pktid = 0; 41 nline = 0; 42 count = 0; 43 is_change = 0; 42 44 } 43 45 … … 51 53 size_t i_pktid, 52 54 addr_t i_nline, 53 size_t i_count) 54 { 55 valid = i_valid; 56 update = i_update; 57 brdcast = i_brdcast; 58 rsp = i_rsp; 59 ack = i_ack; 60 srcid = i_srcid; 61 trdid = i_trdid; 62 pktid = i_pktid; 63 nline = i_nline; 64 count = i_count; 55 size_t i_count, 56 size_t i_is_change) 57 { 58 valid = i_valid; 59 update = i_update; 60 brdcast = i_brdcast; 61 rsp = i_rsp; 62 ack = i_ack; 63 srcid = i_srcid; 64 trdid = i_trdid; 65 pktid = i_pktid; 66 nline = i_nline; 67 count = i_count; 68 is_change = i_is_change; 65 69 } 66 70 67 71 UpdateTabEntry(const UpdateTabEntry &source) 68 72 { 69 valid = source.valid; 70 update = source.update; 71 brdcast = source.brdcast; 72 rsp = source.rsp; 73 ack = source.ack; 74 srcid = source.srcid; 75 trdid = source.trdid; 76 pktid = source.pktid; 77 nline = source.nline; 78 count = source.count; 73 valid = source.valid; 74 update = source.update; 75 brdcast = source.brdcast; 76 rsp = source.rsp; 77 ack = source.ack; 78 srcid = source.srcid; 79 trdid = source.trdid; 80 pktid = source.pktid; 81 nline = source.nline; 82 count = source.count; 83 is_change = source.is_change; 79 84 } 80 85 … … 84 89 void init() 85 90 { 86 valid = false; 87 update = false; 88 brdcast= false; 89 rsp = false; 90 ack = false; 91 srcid = 0; 92 trdid = 0; 93 pktid = 0; 94 nline = 0; 95 count = 0; 91 valid = false; 92 update = false; 93 brdcast = false; 94 rsp = false; 95 ack = false; 96 srcid = 0; 97 trdid = 0; 98 pktid = 0; 99 nline = 0; 100 count = 0; 101 is_change = 0; 96 102 } 97 103 … … 103 109 void copy(const UpdateTabEntry &source) 104 110 { 105 valid = source.valid; 106 update = source.update; 107 brdcast= source.brdcast; 108 rsp = source.rsp; 109 ack = source.ack ; 110 srcid = source.srcid; 111 trdid = source.trdid; 112 pktid = source.pktid; 113 nline = source.nline; 114 count = source.count; 111 valid = source.valid; 112 update = source.update; 113 brdcast = source.brdcast; 114 rsp = source.rsp; 115 ack = source.ack; 116 srcid = source.srcid; 117 trdid = source.trdid; 118 pktid = source.pktid; 119 nline = source.nline; 120 count = source.count; 121 is_change = source.is_change; 115 122 } 116 123 … … 220 227 const addr_t nline, 221 228 const size_t count, 222 size_t &index) 229 size_t &index, 230 const bool is_change=false) 223 231 { 224 232 for ( size_t i=0 ; i<size_tab ; i++ ) … … 236 244 tab[i].nline = (addr_t) nline; 237 245 tab[i].count = (size_t) count; 246 tab[i].is_change = is_change; 238 247 index = i; 239 248 return true; … … 452 461 } 453 462 463 void change(const size_t index) 464 { 465 assert(index<size_tab && "Bad Update Tab Entry"); 466 tab[index].is_change = true; 467 } 468 469 size_t is_change(const size_t index) 470 { 471 assert(index<size_tab && "Bad Update Tab Entry"); 472 return tab[index].is_change; 473 } 454 474 }; 455 475 -
branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r675 r677 161 161 MULTI_ACK_HEAP_LOCK, 162 162 MULTI_ACK_HEAP_WRITE, 163 MULTI_ACK_ WAIT163 MULTI_ACK_IVT_CHANGE 164 164 }; 165 165 … … 1024 1024 sc_signal<size_t> r_cleanup_locked_index; // ivt index 1025 1025 sc_signal<bool> r_cleanup_locked_is_updt; 1026 sc_signal<bool> r_cleanup_locked_is_change; 1026 1027 1027 1028 sc_signal<size_t> r_cleanup_miss_srcid; // srcid of write rsp … … 1029 1030 sc_signal<size_t> r_cleanup_miss_pktid; // pktid of write rsp 1030 1031 sc_signal<size_t> r_cleanup_miss_index; // ivt index 1031 sc_signal<bool> r_cleanup_miss_is_updt;1032 1032 sc_signal<bool> r_cleanup_miss_need_rsp; // write response required 1033 1033 sc_signal<bool> r_cleanup_miss_need_ack; // config acknowledge required -
branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r676 r677 135 135 "MULTI_ACK_HEAP_LOCK", 136 136 "MULTI_ACK_HEAP_WRITE", 137 "MULTI_ACK_ WAIT"137 "MULTI_ACK_IVT_CHANGE" 138 138 }; 139 139 const char *config_fsm_str[] = … … 1112 1112 r_tgt_cmd_to_tgt_rsp_req = false; 1113 1113 1114 r_read_to_cc_send_multi_req = false; 1115 r_read_to_cc_send_brdcast_req = false; 1114 1116 r_read_to_tgt_rsp_req = false; 1115 1117 r_read_to_ixr_cmd_req = false; 1116 r_read_to_cc_send_req = false;1117 1118 r_read_to_cleanup_req = false; 1118 1119 r_read_to_multi_ack_req = false; … … 2155 2156 if(not entry.count) 2156 2157 { 2158 r_multi_ack_fsm = MULTI_ACK_IVT_LOCK; 2157 2159 r_multi_ack_miss_updt = false; 2158 2160 } 2159 r_multi_ack_fsm = MULTI_ACK_WAIT; 2161 else 2162 { 2163 r_multi_ack_fsm = MULTI_ACK_IVT_CHANGE; 2164 } 2160 2165 } 2161 2166 else if( not entry.count or match_ll) // The line has been already evicted from cache L1 … … 2173 2178 } 2174 2179 ///////////// 2175 case MULTI_ACK_WAIT: // release all locks and retry from beginning 2176 { 2177 2180 case MULTI_ACK_IVT_CHANGE: // release all locks and retry from beginning 2181 { 2182 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break; 2183 2184 m_ivt.change(r_multi_ack_ivt_index.read()); 2178 2185 #if DEBUG_MEMC_MULTI_ACK 2179 2186 if(m_debug) 2180 2187 { 2181 2188 std::cout << " <MEMC " << name() 2182 << " MULTI_ACK_ WAIT> Release all locks" << std::endl;2183 } 2184 #endif 2185 r_multi_ack_fsm = MULTI_ACK_I VT_LOCK;2189 << " MULTI_ACK_IVT_CHANGE> multi ack miss, count is 1, change ivt state" << std::endl; 2190 } 2191 #endif 2192 r_multi_ack_fsm = MULTI_ACK_IDLE; 2186 2193 break; 2187 2194 } … … 3234 3241 r_read_to_cc_send_brdcast_req = not multi_req; 3235 3242 r_read_to_cc_send_nline = nline; 3236 r_read_to_cc_send_srcid = m_cmd_read_srcid_fifo.read();3237 r_read_to_cc_send_is_shared = r_read_state.read() == ENTRY_SHARED;3243 //r_read_to_cc_send_srcid = m_cmd_read_srcid_fifo.read(); 3244 //r_read_to_cc_send_is_shared = r_read_state.read() == ENTRY_SHARED; 3238 3245 3239 3246 if(r_read_need_block.read()) … … 3442 3449 false, // multi_inval 3443 3450 true, // it needs a read response 3444 true, // acknowledge required3451 false, // acknowledge required 3445 3452 m_cmd_read_srcid_fifo.read(), 3446 3453 m_cmd_read_trdid_fifo.read(), … … 6635 6642 << " CLEANUP_LOCKED_IVT_LOCK> :" 6636 6643 << "/ is_updt =" << m_ivt.is_update(index) 6644 << "/ is_change =" << m_ivt.is_change(index) 6637 6645 << "/ match =" << match_inval 6638 6646 << "/ need rsp =" << m_ivt.need_rsp(index) … … 6641 6649 #endif 6642 6650 6643 r_cleanup_locked_srcid = m_ivt.srcid(index); 6644 r_cleanup_locked_trdid = m_ivt.trdid(index); 6645 r_cleanup_locked_pktid = m_ivt.pktid(index); 6646 r_cleanup_locked_index = index; 6647 r_cleanup_locked_is_updt = m_ivt.is_update(index); 6648 6649 if( not m_ivt.is_update(index)) 6650 { 6651 r_cleanup_fsm = CLEANUP_LOCKED_IVT_DECREMENT; 6651 r_cleanup_locked_srcid = m_ivt.srcid(index); 6652 r_cleanup_locked_trdid = m_ivt.trdid(index); 6653 r_cleanup_locked_pktid = m_ivt.pktid(index); 6654 r_cleanup_locked_index = index; 6655 r_cleanup_locked_is_updt = m_ivt.is_update(index); 6656 r_cleanup_locked_is_change = m_ivt.is_change(index); 6657 6658 if( m_ivt.is_update(index) and not m_ivt.is_change(index)) 6659 { 6660 r_cleanup_fsm = CLEANUP_LOCKED_IVT_CLEAR; 6652 6661 } 6653 6662 else 6654 6663 { 6655 r_cleanup_fsm = CLEANUP_LOCKED_IVT_ CLEAR;6664 r_cleanup_fsm = CLEANUP_LOCKED_IVT_DECREMENT; 6656 6665 } 6657 6666 … … 6705 6714 size_t match_cas_multi_inval = r_cas_to_cleanup_req.read() and 6706 6715 (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); 6716 6717 bool match_ll = ((r_cleanup_locked_pktid.read() & 0x07) == TYPE_LL); 6707 6718 DirectoryEntry entry; 6708 6719 entry.is_cnt = false; 6709 6720 entry.lock = r_cleanup_lock.read(); 6710 entry.dirty = r_cleanup_dirty.read() ;6721 entry.dirty = r_cleanup_dirty.read() or r_cleanup_contains_data.read(); 6711 6722 entry.tag = r_cleanup_tag.read(); 6712 6723 entry.ptr = r_cleanup_ptr.read(); … … 6728 6739 } 6729 6740 6730 if(r_cleanup_locked_is_updt.read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state. 6731 { 6741 if(r_cleanup_locked_is_updt.read() and not r_cleanup_locked_is_change.read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state. 6742 { 6743 assert(r_cleanup_count.read() == 1 && " only one copy when cleanup fsm receives a req for is_updt command"); 6732 6744 entry.state = r_cleanup_state.read(); //cross with cc updt cmd, don't modify the state 6733 6745 entry.count = 0; … … 6735 6747 entry.owner.inst = 0; 6736 6748 r_cleanup_fsm = CLEANUP_SEND_CLACK; 6749 } 6750 else if(r_cleanup_locked_is_updt.read() and r_cleanup_locked_is_change.read()) 6751 { 6752 entry.state = ENTRY_SHARED; 6753 if(match_ll) 6754 { 6755 entry.count = 0; 6756 entry.owner.srcid = 0; 6757 } 6758 else 6759 { 6760 entry.count = 1; 6761 entry.owner.srcid = r_cleanup_locked_srcid.read(); 6762 } 6763 6764 if((r_cleanup_locked_pktid.read() & 0x7) == 0x03) 6765 { 6766 entry.owner.inst = true; 6767 } 6768 else 6769 { 6770 entry.owner.inst = false; 6771 } 6772 6773 r_cleanup_fsm = CLEANUP_LOCKED_RSP; 6774 m_ivt.clear(r_cleanup_locked_index.read()); 6737 6775 } 6738 6776 else // cas, getm, one copy updated in dir … … 6781 6819 r_cleanup_to_tgt_rsp_nline = r_cleanup_nline.read(); 6782 6820 6783 r_cleanup_to_tgt_rsp_pktid = 0x8 + r_cleanup_locked_pktid.read(); // there is not a brdcast for cas operation. in cache L1, the line can be in M state 6784 6785 if(r_read_to_cleanup_req.read() and (r_read_to_cleanup_nline.read() == r_cleanup_nline.read())) // rsp for LL or pheriph 6821 if(r_cleanup_locked_is_change.read() and r_cleanup_locked_is_updt.read()) 6822 { 6823 r_cleanup_to_tgt_rsp_pktid = r_cleanup_locked_pktid.read(); // rsp for is_updt in shared state 6824 } 6825 else 6826 { 6827 6828 r_cleanup_to_tgt_rsp_pktid = 0x8 + r_cleanup_locked_pktid.read(); // there is not a brdcast for cas operation. in cache L1, the line can be in M state 6829 } 6830 6831 if(r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_cleanup_nline.read()) and // rsp for LL or pheriph 6832 (r_cleanup_locked_is_change.read() and r_cleanup_locked_is_updt.read())) 6833 { 6834 r_cleanup_to_tgt_rsp_ll_key = r_read_to_multi_ack_ll_key.read(); 6835 r_cleanup_to_tgt_rsp_length = r_read_to_multi_ack_length.read(); 6836 r_cleanup_to_tgt_rsp_first_word = r_read_to_multi_ack_first_word.read(); 6837 r_read_to_multi_ack_req = false; 6838 } 6839 else if(r_read_to_cleanup_req.read() and (r_read_to_cleanup_nline.read() == r_cleanup_nline.read())) // rsp for LL or pheriph 6786 6840 { 6787 6841 r_cleanup_to_tgt_rsp_ll_key = r_read_to_cleanup_ll_key.read(); … … 6820 6874 << " <MEMC " << name() 6821 6875 << " CLEANUP_LOCKED_RSP>" 6822 << " type rsp =" << r_cleanup_locked_pktid.read()6823 << " r_read_to_cleanup_req =" << r_read_to_cleanup_req.read()6824 << " r_read_to_cleanup_length =" << r_read_to_cleanup_length.read()6825 << " r_read_to_cleanup_first_word =" << r_read_to_cleanup_first_word.read()6876 << " type rsp =" << r_cleanup_locked_pktid.read() 6877 << " r_read_to_cleanup_req =" << r_read_to_cleanup_req.read() 6878 << " r_read_to_cleanup_length =" << r_read_to_cleanup_length.read() 6879 << " r_read_to_cleanup_first_word =" << r_read_to_cleanup_first_word.read() 6826 6880 << std::endl; 6827 6881 } … … 7267 7321 } 7268 7322 //std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl; 7269 r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read();7323 //r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); 7270 7324 r_cleanup_to_ixr_cmd_index = index; 7271 r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read();7272 r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read();7325 //r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 7326 //r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 7273 7327 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); 7274 7328 r_cleanup_fsm = CLEANUP_SEND_CLACK; … … 9826 9880 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 9827 9881 9828 else if (r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) 9882 else if ((r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) or 9883 (r_multi_ack_fsm.read() == MULTI_ACK_IVT_CHANGE)) 9829 9884 r_alloc_ivt_fsm = ALLOC_IVT_MULTI_ACK; 9830 9885 … … 9853 9908 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 9854 9909 9855 else if (r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) 9910 else if ((r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) or 9911 (r_multi_ack_fsm.read() == MULTI_ACK_IVT_CHANGE)) 9856 9912 r_alloc_ivt_fsm = ALLOC_IVT_MULTI_ACK; 9857 9913 … … 9879 9935 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 9880 9936 9881 else if (r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) 9937 else if ((r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) or 9938 (r_multi_ack_fsm.read() == MULTI_ACK_IVT_CHANGE)) 9882 9939 r_alloc_ivt_fsm = ALLOC_IVT_MULTI_ACK; 9883 9940 … … 9908 9965 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 9909 9966 9910 else if (r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) 9967 else if ((r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) or 9968 (r_multi_ack_fsm.read() == MULTI_ACK_IVT_CHANGE)) 9911 9969 r_alloc_ivt_fsm = ALLOC_IVT_MULTI_ACK; 9912 9970 … … 9934 9992 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 9935 9993 9936 else if (r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) 9994 else if ((r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) or 9995 (r_multi_ack_fsm.read() == MULTI_ACK_IVT_CHANGE)) 9937 9996 r_alloc_ivt_fsm = ALLOC_IVT_MULTI_ACK; 9938 9997 … … 9960 10019 if (r_config_fsm.read() != CONFIG_IVT_LOCK) 9961 10020 { 9962 if (r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) 10021 if ((r_multi_ack_fsm.read() == MULTI_ACK_IVT_LOCK) or 10022 (r_multi_ack_fsm.read() == MULTI_ACK_IVT_CHANGE)) 9963 10023 r_alloc_ivt_fsm = ALLOC_IVT_MULTI_ACK; 9964 10024 … … 9987 10047 ////////////////////////// 9988 10048 case ALLOC_IVT_MULTI_ACK: // allocated to MULTI ACK FSM 9989 if (r_multi_ack_fsm.read() != MULTI_ACK_IVT_LOCK) 10049 if ((r_multi_ack_fsm.read() != MULTI_ACK_IVT_LOCK) and 10050 (r_multi_ack_fsm.read() != MULTI_ACK_IVT_CHANGE)) 9990 10051 { 9991 10052 if ((r_write_fsm.read() == WRITE_INVAL_IVT_LOCK)) … … 11517 11578 11518 11579 DspinDhccpParam::dspin_set( flit, 11519 m_cc_global_id + 0xff,11580 m_cc_global_id, 11520 11581 DspinDhccpParam::BROADCAST_SRCID); 11521 11582 … … 11539 11600 11540 11601 DspinDhccpParam::dspin_set( flit, 11541 m_cc_global_id + 0xff,11602 m_cc_global_id, 11542 11603 DspinDhccpParam::BROADCAST_SRCID); 11543 11604 … … 11558 11619 DspinDhccpParam::BROADCAST_BOX); 11559 11620 11560 DspinDhccpParam::dspin_set( flit,11561 r_read_to_cc_send_srcid.read(), // send the srcid itself which demands the request getM11562 DspinDhccpParam::BROADCAST_SRCID);11563 11564 DspinDhccpParam::dspin_set( flit,11565 r_read_to_cc_send_is_shared.read(), // send the actuel line state in memcache11566 DspinDhccpParam::BRDCAST_IS_SHARED);11621 // DspinDhccpParam::dspin_set( flit, 11622 // r_read_to_cc_send_srcid.read(), // send the srcid itself which demands the request getM 11623 // DspinDhccpParam::BROADCAST_SRCID); 11624 11625 // DspinDhccpParam::dspin_set( flit, 11626 // r_read_to_cc_send_is_shared.read(), // send the actuel line state in memcache 11627 // DspinDhccpParam::BRDCAST_IS_SHARED); 11567 11628 11568 11629 DspinDhccpParam::dspin_set( flit,
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