Changeset 680 for branches/MESI/modules
- Timestamp:
- Apr 17, 2014, 11:12:35 AM (11 years ago)
- Location:
- branches/MESI/modules
- Files:
-
- 4 edited
-
vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (6 diffs)
-
vci_mem_cache/caba/source/include/update_tab.h (modified) (11 diffs)
-
vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (1 diff)
-
vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (36 diffs)
Legend:
- Unmodified
- Added
- Removed
-
branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r677 r680 388 388 r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16), // 2 words depth 389 389 // r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth 390 r_cc_send_data_fifo("r_cc_send_data_fifo", 16),390 r_cc_send_data_fifo("r_cc_send_data_fifo", 2), 391 391 392 392 r_cc_send_fsm("r_cc_send_fsm"), … … 2298 2298 { 2299 2299 2300 #if 12301 // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE2302 if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {2303 std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl;2304 raise(SIGINT);2305 }2306 #endif2300 //#if 1 2301 // // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE 2302 // if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { 2303 // std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; 2304 // raise(SIGINT); 2305 // } 2306 //#endif 2307 2307 2308 2308 if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated … … 5279 5279 ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) 5280 5280 { 5281 5282 if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) 5281 5282 if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and 5283 (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) 5283 5284 { 5284 5285 r_dcache_miss_clack = true; 5285 5286 r_dcache_fsm = DCACHE_CC_INVAL; 5286 5287 } 5288 else if(r_dcache_read_for_modify.read() and (r_dcache_miss_type.read() == PROC_MISS) and 5289 (r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) and (state == CACHE_SLOT_STATE_INVALID) and 5290 (r_cc_receive_dcache_srcid.read() == m_srcid)) 5291 { 5292 r_cc_receive_dcache_req = false; 5293 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5294 } 5287 5295 else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 5288 5296 { … … 5344 5352 std::cout << " <PROC " << name() 5345 5353 << " DCACHE_CC_CHECK> Coherence request matching a pending miss:" 5354 << " state =" << state 5355 << " r_receive_srcid = " << std::hex << r_cc_receive_dcache_srcid.read() 5356 << " m_proc_id = " << std::hex << m_proc_id 5346 5357 << " PADDR = " << std::hex << paddr << std::endl; 5347 5358 } … … 5381 5392 r_dcache_cc_send_multi_ack_miss = false; 5382 5393 } 5383 else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval5394 else if ( r_cc_receive_dcache_type.read() != CC_TYPE_UPDT ) // hit inval 5384 5395 { 5385 5396 r_dcache_fsm = DCACHE_CC_INVAL; … … 6319 6330 r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, 6320 6331 DspinDhccpParam::BROADCAST_NLINE); 6321 r_cc_receive_dcache_type = CC_TYPE_ INVAL;6332 r_cc_receive_dcache_type = CC_TYPE_BRDCAST; 6322 6333 // request icache to handle the BROADCAST 6323 6334 r_cc_receive_icache_req = true; -
branches/MESI/modules/vci_mem_cache/caba/source/include/update_tab.h
r677 r680 27 27 addr_t nline; // The identifier of the cache line 28 28 size_t count; // The number of acknowledge responses to receive 29 bool is_change; // multi ack miss req sends this bit to 1 29 bool type; // for a command read or write 30 bool is_changed; // multi ack miss req sends this bit to 1 30 31 31 32 UpdateTabEntry() … … 41 42 nline = 0; 42 43 count = 0; 43 is_change = 0; 44 type = 0; 45 is_changed = 0; 44 46 } 45 47 … … 54 56 addr_t i_nline, 55 57 size_t i_count, 56 size_t i_is_change) 58 bool i_type, 59 bool i_is_changed) 57 60 { 58 61 valid = i_valid; … … 66 69 nline = i_nline; 67 70 count = i_count; 68 is_change = i_is_change; 71 type = i_type; 72 is_changed = i_is_changed; 69 73 } 70 74 … … 81 85 nline = source.nline; 82 86 count = source.count; 83 is_change = source.is_change; 87 type = source.type; 88 is_changed = source.is_changed; 84 89 } 85 90 … … 99 104 nline = 0; 100 105 count = 0; 101 is_change = 0; 106 type = 0; 107 is_changed = 0; 102 108 } 103 109 … … 119 125 nline = source.nline; 120 126 count = source.count; 121 is_change = source.is_change; 127 type = source.type; 128 is_changed = source.is_changed; 122 129 } 123 130 … … 136 143 << " / trdid = " << trdid 137 144 << " / pktid = " << pktid 145 << " / type = " << type 146 << " / is_changed = " << is_changed 138 147 << " / nline = " << nline << std::endl; 139 148 } … … 227 236 const addr_t nline, 228 237 const size_t count, 238 const bool type, 229 239 size_t &index, 230 const bool is_change =false)240 const bool is_changed=false) 231 241 { 232 242 for ( size_t i=0 ; i<size_tab ; i++ ) … … 244 254 tab[i].nline = (addr_t) nline; 245 255 tab[i].count = (size_t) count; 246 tab[i].is_change = is_change; 256 tab[i].type = type; 257 tab[i].is_changed = is_changed; 247 258 index = i; 248 259 return true; … … 464 475 { 465 476 assert(index<size_tab && "Bad Update Tab Entry"); 466 tab[index].is_change = true; 467 } 468 469 size_t is_change(const size_t index) 470 { 471 assert(index<size_tab && "Bad Update Tab Entry"); 472 return tab[index].is_change; 477 tab[index].is_changed = true; 478 } 479 480 bool is_changed(const size_t index) 481 { 482 assert(index<size_tab && "Bad Update Tab Entry"); 483 return tab[index].is_changed; 484 } 485 486 bool is_read(const size_t index) 487 { 488 assert(index<size_tab && "Bad Update Tab Entry"); 489 return tab[index].type; 473 490 } 474 491 }; -
branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r677 r680 1024 1024 sc_signal<size_t> r_cleanup_locked_index; // ivt index 1025 1025 sc_signal<bool> r_cleanup_locked_is_updt; 1026 sc_signal<bool> r_cleanup_locked_is_change; 1026 sc_signal<bool> r_cleanup_locked_is_changed; 1027 sc_signal<bool> r_cleanup_locked_is_read; 1027 1028 1028 1029 sc_signal<size_t> r_cleanup_miss_srcid; // srcid of write rsp -
branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r678 r680 2844 2844 nline, 2845 2845 nb_copies, 2846 false, 2846 2847 index); 2847 2848 … … 3241 3242 r_read_to_cc_send_brdcast_req = not multi_req; 3242 3243 r_read_to_cc_send_nline = nline; 3243 //r_read_to_cc_send_srcid = m_cmd_read_srcid_fifo.read();3244 r_read_to_cc_send_srcid = m_cmd_read_srcid_fifo.read(); 3244 3245 //r_read_to_cc_send_is_shared = r_read_state.read() == ENTRY_SHARED; 3245 3246 … … 3276 3277 nline, 3277 3278 r_read_count.read(), 3279 true, //is a command read 3278 3280 index); 3279 3281 … … 3449 3451 false, // multi_inval 3450 3452 true, // it needs a read response 3451 false, 3453 false, // acknowledge required 3452 3454 m_cmd_read_srcid_fifo.read(), 3453 3455 m_cmd_read_trdid_fifo.read(), … … 3455 3457 nline, 3456 3458 0x01, 3459 true, // is a command read 3457 3460 index); 3458 3461 … … 4139 4142 else // invalid the line and send multi_inval or brdcast to cache L1, and set trt table to evict the line 4140 4143 { 4141 if(entry.state == ENTRY_EXCLUSIVE)4142 {4143 r_write_inval_trt_send = false;4144 }4145 else4146 {4147 r_write_inval_trt_send = true;4148 }4149 r_write_fsm = WRITE_INVAL_ TRT_LOCK;4144 // if(entry.state == ENTRY_EXCLUSIVE) 4145 // { 4146 // r_write_inval_trt_send = false; 4147 // } 4148 // else 4149 // { 4150 // r_write_inval_trt_send = true; 4151 // } 4152 r_write_fsm = WRITE_INVAL_IVT_LOCK; 4150 4153 4151 4154 } … … 4155 4158 { 4156 4159 // if a miss write matched with a trt wait situation(wait for dirty data), it must block the command write until the dirty data has arrived in memcache 4157 if(r_write_to_cleanup_req.read() and4158 r_write_to_cleanup_nline.read() == nline)4159 {4160 std::cout << "hit write cleanup nline =" << std::hex << nline << std::endl;4161 r_write_fsm = WRITE_WAIT;4162 }4163 else4164 {4160 // if(r_write_to_cleanup_req.read() and 4161 // r_write_to_cleanup_nline.read() == nline) 4162 // { 4163 // std::cout << "hit write cleanup nline =" << std::hex << nline << std::endl; 4164 // r_write_fsm = WRITE_WAIT; 4165 // } 4166 // else 4167 // { 4165 4168 r_write_fsm = WRITE_MISS_TRT_LOCK; 4166 }4169 // } 4167 4170 } 4168 4171 … … 4419 4422 m_heap.write(r_write_next_ptr.read(),last_entry); 4420 4423 4421 r_write_fsm = WRITE_I NVAL_XRAM_REQ; //this is sure that this line is in shared state, it can be send to xram4424 r_write_fsm = WRITE_IDLE; 4422 4425 4423 4426 #if DEBUG_MEMC_XRAM_RSP … … 4904 4907 "MEMC ERROR in WRITE_INVAL_IVT_LOCK state: Bad DIR allocation"); 4905 4908 4906 assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and 4907 "MEMC ERROR in WRITE_INVAL_IVT_LOCK state: Bad TRT allocation"); 4908 4909 size_t set = m_y[(addr_t)(r_write_address.read())]; 4909 //assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and 4910 // "MEMC ERROR in WRITE_INVAL_IVT_LOCK state: Bad TRT allocation"); 4911 4912 size_t set = m_y[(addr_t)(r_write_address.read())]; 4913 size_t way = r_write_way.read(); 4910 4914 4911 4915 bool cc_send_valid = not r_write_to_cc_send_multi_req.read() and 4912 not r_write_to_cc_send_brdcast_req.read() and 4913 (r_write_inval_trt_send.read() or not r_write_to_cleanup_req.read()); 4916 not r_write_to_cc_send_brdcast_req.read() and 4917 not (r_write_state.read() == ENTRY_EXCLUSIVE and r_write_to_cleanup_req.read()); 4918 // (r_write_inval_trt_send.read() or not r_write_to_cleanup_req.read()); 4914 4919 4915 4920 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) … … 4939 4944 nline, 4940 4945 nb_copies, 4946 false, // is a command write 4941 4947 index); 4942 4948 /*// std::cout << " trt wait nline =" << std::hex << nline … … 4948 4954 << " / nb_copies = " << r_write_count.read() << std::endl; 4949 4955 #endif 4956 // for(size_t word=0 ; word<m_words ; word++) 4957 // { 4958 // r_write_to_cleanup_be[word] = r_write_be[word]; 4959 // r_write_to_cleanup_data[word] = r_write_data[word]; 4960 4961 // data_t mask = 0; 4962 // if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF; 4963 // if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00; 4964 // if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000; 4965 // if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000; 4966 4967 // // complete only if mask is not null (for energy consumption) 4968 // r_write_data[word] = 4969 // (r_write_data[word].read() & mask) | 4970 // (m_cache_data.read(r_write_way.read(), set, word) & ~mask); 4971 ///*// std::cout << std::hex 4972 // << ((r_write_data[word].read() & mask) | 4973 // (m_cache_data.read(r_write_way.read(), set, word) & ~mask)) << std::endl;*/ 4974 // } 4975 4976 DirectoryEntry entry; 4977 entry.state = ENTRY_LOCKED; 4978 entry.dirty = true; 4979 entry.tag = r_write_tag.read(); 4980 entry.is_cnt = r_write_is_cnt.read(); 4981 entry.lock = r_write_lock.read(); 4982 entry.owner.srcid = r_write_copy.read(); 4983 entry.owner.inst = r_write_copy_inst.read(); 4984 entry.ptr = 0; 4985 entry.count = r_write_count.read(); 4986 4987 m_cache_directory.write(set, way, entry); 4988 4989 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 4990 { 4991 m_llsc_table.sc(r_write_address.read(), 4992 r_write_sc_key.read()); 4993 } 4994 4950 4995 for(size_t word=0 ; word<m_words ; word++) 4951 4996 { 4952 4997 r_write_to_cleanup_be[word] = r_write_be[word]; 4953 4998 r_write_to_cleanup_data[word] = r_write_data[word]; 4954 4955 data_t mask = 0; 4956 if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF; 4957 if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00; 4958 if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000; 4959 if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000; 4960 4961 // complete only if mask is not null (for energy consumption) 4962 r_write_data[word] = 4963 (r_write_data[word].read() & mask) | 4964 (m_cache_data.read(r_write_way.read(), set, word) & ~mask); 4965 /*// std::cout << std::hex 4966 << ((r_write_data[word].read() & mask) | 4967 (m_cache_data.read(r_write_way.read(), set, word) & ~mask)) << std::endl;*/ 4999 5000 if(r_write_state.read() == ENTRY_SHARED) 5001 { 5002 m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read()); 5003 } 4968 5004 } 4969 r_write_fsm = WRITE_ DIR_INVAL;5005 r_write_fsm = WRITE_INVAL_CC_SEND; 4970 5006 } 4971 5007 else … … 4986 5022 "MEMC ERROR in WRITE_DIR_INVAL state: Bad DIR allocation"); 4987 5023 4988 assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and4989 "MEMC ERROR in WRITE_DIR_INVAL state: Bad TRT allocation");5024 // assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and 5025 // "MEMC ERROR in WRITE_DIR_INVAL state: Bad TRT allocation"); 4990 5026 4991 5027 assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and 4992 5028 "MEMC ERROR in WRITE_DIR_INVAL state: Bad IVT allocation"); 4993 5029 4994 4995 std::vector<data_t> data_vector;4996 data_vector.clear();4997 for(size_t i=0; i<m_words; i++) data_vector.push_back(r_write_data[i].read());4998 4999 m_trt.set( r_write_trt_index.read(),5000 false, // PUT request5001 m_nline[(addr_t)(r_write_address.read())],5002 0, // unused5003 0, // unused5004 0, // unused5005 false, // not a processor read5006 0, // unused5007 0, // unused5008 std::vector<be_t> (m_words,0),5009 data_vector );5030 // register PUT request in TRT 5031 // std::vector<data_t> data_vector; 5032 // data_vector.clear(); 5033 // for(size_t i=0; i<m_words; i++) data_vector.push_back(r_write_data[i].read()); 5034 5035 // m_trt.set( r_write_trt_index.read(), 5036 // false, // PUT request 5037 // m_nline[(addr_t)(r_write_address.read())], 5038 // 0, // unused 5039 // 0, // unused 5040 // 0, // unused 5041 // false, // not a processor read 5042 // 0, // unused 5043 // 0, // unused 5044 // std::vector<be_t> (m_words,0), 5045 // data_vector ); 5010 5046 5011 5047 // invalidate directory entry 5012 5048 DirectoryEntry entry; 5013 entry.state = ENTRY_ INVALID;5014 entry.dirty = false;5015 entry.tag = 0;5016 entry.is_cnt = false;5049 entry.state = ENTRY_LOCKED; 5050 entry.dirty = true; 5051 entry.tag = r_write_tag.read(); 5052 entry.is_cnt = 0; 5017 5053 entry.lock = false; 5018 5054 entry.owner.srcid = 0; … … 5049 5085 bool not_last_multi_inval = (r_write_count.read() != 1) and not r_write_is_cnt.read(); 5050 5086 bool multi_inval = not r_write_is_cnt.read(); 5087 5051 5088 r_write_to_cc_send_multi_req = last_multi_inval; 5052 5089 r_write_to_cc_send_brdcast_req = not multi_inval; … … 5057 5094 r_write_next_ptr = r_write_ptr.read(); 5058 5095 5096 if(r_write_state.read() == ENTRY_EXCLUSIVE) 5097 { 5098 r_write_to_cleanup_req = true; 5099 r_write_to_cleanup_nline = m_nline[(addr_t)(r_write_address.read())]; 5100 } 5101 5059 5102 if( not last_multi_inval and multi_inval) 5060 5103 { … … 5063 5106 else 5064 5107 { 5065 if(r_write_inval_trt_send.read())5066 {5067 r_write_fsm = WRITE_INVAL_XRAM_REQ;5068 }5069 else //the line is in exlusive state, must wait for the5070 //response of multi_inval in reason of receiving the updated data5071 {5108 // if(r_write_inval_trt_send.read()) 5109 // { 5110 // r_write_fsm = WRITE_INVAL_XRAM_REQ; 5111 // } 5112 // else //the line is in exlusive state, must wait for the 5113 // //response of multi_inval in reason of receiving the updated data 5114 // { 5072 5115 r_write_fsm = WRITE_IDLE; 5073 r_write_to_cleanup_req = true; 5074 r_write_to_cleanup_nline = m_nline[(addr_t)(r_write_address.read())]; 5075 } 5116 5117 // } 5076 5118 } 5077 5119 #if DEBUG_MEMC_WRITE … … 5904 5946 r_xram_rsp_victim_nline.read(), 5905 5947 count_copies, 5948 false, //unuse 5906 5949 index); 5907 5950 … … 6642 6685 << " CLEANUP_LOCKED_IVT_LOCK> :" 6643 6686 << "/ is_updt =" << m_ivt.is_update(index) 6644 << "/ is_change =" << m_ivt.is_change(index)6687 << "/ is_changed =" << m_ivt.is_changed(index) 6645 6688 << "/ match =" << match_inval 6646 6689 << "/ need rsp =" << m_ivt.need_rsp(index) … … 6654 6697 r_cleanup_locked_index = index; 6655 6698 r_cleanup_locked_is_updt = m_ivt.is_update(index); 6656 r_cleanup_locked_is_change = m_ivt.is_change(index); 6657 6658 if( m_ivt.is_update(index) and not m_ivt.is_change(index)) 6699 r_cleanup_locked_is_changed = m_ivt.is_changed(index); 6700 r_cleanup_locked_is_read = m_ivt.is_read(index); 6701 6702 if( m_ivt.is_update(index) and not m_ivt.is_changed(index)) 6659 6703 { 6660 6704 r_cleanup_fsm = CLEANUP_LOCKED_IVT_CLEAR; … … 6712 6756 6713 6757 addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; 6714 size_t match_cas_multi_inval = r_cas_to_cleanup_req.read() and 6715 (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); 6758 //size_t match_cas_multi_inval = r_cas_to_cleanup_req.read() and 6759 // (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); 6760 6761 size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; 6716 6762 6717 6763 bool match_ll = ((r_cleanup_locked_pktid.read() & 0x07) == TYPE_LL); 6718 DirectoryEntry entry; 6764 6765 DirectoryEntry entry; 6719 6766 entry.is_cnt = false; 6720 6767 entry.lock = r_cleanup_lock.read(); … … 6739 6786 } 6740 6787 6741 if(r_cleanup_locked_is_updt.read() and not r_cleanup_locked_is_change .read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state.6788 if(r_cleanup_locked_is_updt.read() and not r_cleanup_locked_is_changed.read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state. 6742 6789 { 6743 6790 assert(r_cleanup_count.read() == 1 && " only one copy when cleanup fsm receives a req for is_updt command"); … … 6748 6795 r_cleanup_fsm = CLEANUP_SEND_CLACK; 6749 6796 } 6750 else if(r_cleanup_locked_is_updt.read() and r_cleanup_locked_is_change .read())6797 else if(r_cleanup_locked_is_updt.read() and r_cleanup_locked_is_changed.read()) 6751 6798 { 6752 6799 entry.state = ENTRY_SHARED; … … 6762 6809 } 6763 6810 6764 if((r_cleanup_locked_pktid.read() & 0x7) == 0x03)6811 if((r_cleanup_locked_pktid.read() & 0x7) == TYPE_READ_INS_MISS) 6765 6812 { 6766 6813 entry.owner.inst = true; … … 6776 6823 else // cas, getm, one copy updated in dir 6777 6824 { 6778 if(match_cas_ multi_inval)6825 if(match_cas_inval) 6779 6826 { 6780 6827 entry.state = ENTRY_SHARED; 6781 6828 entry.count = 0; 6782 6829 } 6830 else if(r_cleanup_locked_is_read.read()) 6831 { 6832 entry.state = ENTRY_EXCLUSIVE; 6833 entry.count = 1; 6834 entry.owner.srcid = r_cleanup_locked_srcid.read(); 6835 } 6783 6836 else 6784 6837 { 6785 6838 entry.state = ENTRY_EXCLUSIVE; 6786 entry.count = 1;6787 } 6788 entry.owner.srcid = r_cleanup_locked_srcid.read(); 6839 entry.count = 0; 6840 } 6841 6789 6842 entry.owner.inst = 0; 6790 6843 r_cleanup_fsm = CLEANUP_LOCKED_RSP; … … 6814 6867 if(r_cleanup_to_tgt_rsp_req.read()) break; 6815 6868 6869 size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; 6870 6816 6871 r_cleanup_to_tgt_rsp_req = true; 6817 6872 r_cleanup_to_tgt_rsp_srcid = r_cleanup_locked_srcid.read(); … … 6819 6874 r_cleanup_to_tgt_rsp_nline = r_cleanup_nline.read(); 6820 6875 6821 if(r_cleanup_locked_is_change .read() and r_cleanup_locked_is_updt.read())6876 if(r_cleanup_locked_is_changed.read() and r_cleanup_locked_is_updt.read()) 6822 6877 { 6823 6878 r_cleanup_to_tgt_rsp_pktid = r_cleanup_locked_pktid.read(); // rsp for is_updt in shared state … … 6830 6885 6831 6886 if(r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_cleanup_nline.read()) and // rsp for LL or pheriph 6832 (r_cleanup_locked_is_change .read() and r_cleanup_locked_is_updt.read()))6887 (r_cleanup_locked_is_changed.read() and r_cleanup_locked_is_updt.read())) 6833 6888 { 6834 6889 r_cleanup_to_tgt_rsp_ll_key = r_read_to_multi_ack_ll_key.read(); … … 6851 6906 } 6852 6907 6853 if(r_cas_to_cleanup_req.read()) 6854 { 6855 r_cas_to_cleanup_req = false; 6856 r_cleanup_to_tgt_rsp_type = true; 6857 } 6858 else 6859 { 6860 r_cleanup_to_tgt_rsp_type = false; 6861 } 6908 if(r_write_to_cleanup_req.read()) 6909 r_write_to_cleanup_req = false; 6910 6911 r_cleanup_to_tgt_rsp_type = not r_cleanup_locked_is_read.read(); 6862 6912 6863 6913 for(size_t i = 0; i<m_words; i++) … … 7224 7274 config_rsp_lines_cleanup_decr = true; 7225 7275 } 7226 7276 7277 assert(r_cleanup_miss_need_rsp.read() == false && "THERE IS A CLEANUP MISS NEEDS RSP"); 7227 7278 if (r_cleanup_miss_need_rsp.read()) 7228 7279 { … … 7293 7344 r_cleanup_to_ixr_cmd_req = true; 7294 7345 7295 if( (r_write_to_cleanup_req == true) and (r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) )7296 {7297 r_write_to_cleanup_req = false;7298 }7346 // if( (r_write_to_cleanup_req == true) and (r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) ) 7347 // { 7348 // r_write_to_cleanup_req = false; 7349 // } 7299 7350 7300 7351 if (r_cleanup_contains_data.read()) … … 7685 7736 not r_cas_to_cc_send_multi_req.read() and 7686 7737 not r_cas_to_cc_send_brdcast_req.read() and 7687 not r_cas_to_cleanup_req.read() and7688 7738 m_cas_to_cc_send_inst_fifo.wok()) 7689 7739 { … … 7695 7745 addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 7696 7746 size_t nb_copies_sent = 0; 7697 if(r_cas_state.read() == ENTRY_EXCLUSIVE) 7698 { 7699 nb_copies_sent = 1; 7700 } 7701 else 7702 { 7747 7748 // if(r_cas_state.read() == ENTRY_EXCLUSIVE) 7749 // { 7750 // nb_copies_sent = 1; 7751 // } 7752 // else 7753 // { 7703 7754 nb_copies_sent = r_cas_count.read(); 7704 }7755 // } 7705 7756 // if(m_ivt.search_inval(nline, index) and r_cas_to_cleanup_req.read()) 7706 7757 // { … … 7723 7774 nline, 7724 7775 nb_copies_sent, 7776 false, // is a command write 7725 7777 index); 7726 7778 if(wok) // coherence transaction registered in ivt … … 7773 7825 7774 7826 r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 7775 r_cas_to_cleanup_req = true;7776 r_cas_to_cleanup_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];7827 //r_cas_to_cleanup_req = true; 7828 //r_cas_to_cleanup_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 7777 7829 r_cas_fsm = CAS_IDLE; 7778 7830 cmd_cas_fifo_get = true; … … 7904 7956 if(entry.next == r_cas_next_ptr.read()) // last copy 7905 7957 { 7906 r_cas_to_cleanup_nline = nline;7958 //r_cas_to_cleanup_nline = nline; 7907 7959 r_cas_to_cc_send_multi_req = true; 7908 r_cas_to_cleanup_req = true;7960 //r_cas_to_cleanup_req = true; 7909 7961 r_cas_fsm = CAS_HEAP_LAST; // Response will be sent after receiving 7910 7962 } … … 8020 8072 nline, 8021 8073 nb_copies, 8074 false, // is a command write 8022 8075 index); 8023 8076 … … 11614 11667 11615 11668 DspinDhccpParam::dspin_set( flit, 11616 m_broadcast_boundaries,11617 DspinDhccpParam::BROADCAST_BOX);11618 11619 //DspinDhccpParam::dspin_set( flit,11620 //r_read_to_cc_send_srcid.read(), // send the srcid itself which demands the request getM11621 //DspinDhccpParam::BROADCAST_SRCID);11669 m_broadcast_boundaries, 11670 DspinDhccpParam::BROADCAST_BOX); 11671 11672 DspinDhccpParam::dspin_set( flit, 11673 r_read_to_cc_send_srcid.read(), // send the srcid itself which demands the request getM 11674 DspinDhccpParam::BROADCAST_SRCID); 11622 11675 11623 11676 // DspinDhccpParam::dspin_set( flit,
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