Index: /branches/MESI/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h =================================================================== --- /branches/MESI/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h (revision 679) +++ /branches/MESI/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h (revision 680) @@ -210,4 +210,11 @@ static const uint8_t MULTI_INVAL_IS_CONFIG_SHIFT = 21; static const uint64_t MULTI_INVAL_IS_CONFIG_MASK = 1; + static const uint8_t BRDCAST_IS_CONFIG_SHIFT = 1; + static const uint64_t BRDCAST_IS_CONFIG_MASK = 1; + + static const uint8_t MULTI_INVAL_IS_SHARED_SHIFT = 22; + static const uint64_t MULTI_INVAL_IS_SHARED_MASK = 1; + static const uint8_t BRDCAST_IS_SHARED_SHIFT = 2; + static const uint64_t BRDCAST_IS_SHARED_MASK = 1; static const uint8_t MULTI_UPDT_DEST_SHIFT = MULTI_INVAL_DEST_SHIFT; @@ -306,4 +313,7 @@ MULTI_INVAL_NLINE, MULTI_INVAL_IS_CONFIG, + BRDCAST_IS_CONFIG, + MULTI_INVAL_IS_SHARED, + BRDCAST_IS_SHARED, MULTI_UPDT_DEST, @@ -351,4 +361,7 @@ GET_FIELD(flit,MULTI_INVAL_NLINE); GET_FIELD(flit,MULTI_INVAL_IS_CONFIG); + GET_FIELD(flit,BRDCAST_IS_CONFIG); + GET_FIELD(flit,MULTI_INVAL_IS_SHARED); + GET_FIELD(flit,BRDCAST_IS_SHARED); GET_FIELD(flit,MULTI_UPDT_DEST); GET_FIELD(flit,MULTI_UPDT_SRCID); @@ -395,4 +408,7 @@ SET_FIELD(flit,value,MULTI_INVAL_NLINE); SET_FIELD(flit,value,MULTI_INVAL_IS_CONFIG); + SET_FIELD(flit,value,BRDCAST_IS_CONFIG); + SET_FIELD(flit,value,MULTI_INVAL_IS_SHARED); + SET_FIELD(flit,value,BRDCAST_IS_SHARED); SET_FIELD(flit,value,MULTI_UPDT_DEST); SET_FIELD(flit,value,MULTI_UPDT_SRCID); Index: /branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 679) +++ /branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 680) @@ -388,5 +388,5 @@ r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16), // 2 words depth // r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth - r_cc_send_data_fifo("r_cc_send_data_fifo", 16), + r_cc_send_data_fifo("r_cc_send_data_fifo", 2), r_cc_send_fsm("r_cc_send_fsm"), @@ -2298,11 +2298,11 @@ { -#if 1 - // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE - if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { - std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; - raise(SIGINT); - } -#endif +//#if 1 +// // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE +// if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { +// std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; +// raise(SIGINT); +// } +//#endif if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated @@ -5279,10 +5279,18 @@ ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) { - - if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) + + if(r_dcache_read_for_modify.read() and(r_dcache_miss_type.read() == PROC_MISS) and + (r_cc_receive_dcache_type.read() != CC_TYPE_UPDT) and (state == CACHE_SLOT_STATE_SHARED)) { r_dcache_miss_clack = true; r_dcache_fsm = DCACHE_CC_INVAL; } + else if(r_dcache_read_for_modify.read() and (r_dcache_miss_type.read() == PROC_MISS) and + (r_cc_receive_dcache_type.read() == CC_TYPE_BRDCAST) and (state == CACHE_SLOT_STATE_INVALID) and + (r_cc_receive_dcache_srcid.read() == m_srcid)) + { + r_cc_receive_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) { @@ -5344,4 +5352,7 @@ std::cout << " Coherence request matching a pending miss:" + << " state =" << state + << " r_receive_srcid = " << std::hex << r_cc_receive_dcache_srcid.read() + << " m_proc_id = " << std::hex << m_proc_id << " PADDR = " << std::hex << paddr << std::endl; } @@ -5381,5 +5392,5 @@ r_dcache_cc_send_multi_ack_miss = false; } - else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval + else if ( r_cc_receive_dcache_type.read() != CC_TYPE_UPDT ) // hit inval { r_dcache_fsm = DCACHE_CC_INVAL; @@ -6319,5 +6330,5 @@ r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, DspinDhccpParam::BROADCAST_NLINE); - r_cc_receive_dcache_type = CC_TYPE_INVAL; + r_cc_receive_dcache_type = CC_TYPE_BRDCAST; // request icache to handle the BROADCAST r_cc_receive_icache_req = true; Index: /branches/MESI/modules/vci_mem_cache/caba/source/include/update_tab.h =================================================================== --- /branches/MESI/modules/vci_mem_cache/caba/source/include/update_tab.h (revision 679) +++ /branches/MESI/modules/vci_mem_cache/caba/source/include/update_tab.h (revision 680) @@ -27,5 +27,6 @@ addr_t nline; // The identifier of the cache line size_t count; // The number of acknowledge responses to receive - bool is_change; // multi ack miss req sends this bit to 1 + bool type; // for a command read or write + bool is_changed; // multi ack miss req sends this bit to 1 UpdateTabEntry() @@ -41,5 +42,6 @@ nline = 0; count = 0; - is_change = 0; + type = 0; + is_changed = 0; } @@ -54,5 +56,6 @@ addr_t i_nline, size_t i_count, - size_t i_is_change) + bool i_type, + bool i_is_changed) { valid = i_valid; @@ -66,5 +69,6 @@ nline = i_nline; count = i_count; - is_change = i_is_change; + type = i_type; + is_changed = i_is_changed; } @@ -81,5 +85,6 @@ nline = source.nline; count = source.count; - is_change = source.is_change; + type = source.type; + is_changed = source.is_changed; } @@ -99,5 +104,6 @@ nline = 0; count = 0; - is_change = 0; + type = 0; + is_changed = 0; } @@ -119,5 +125,6 @@ nline = source.nline; count = source.count; - is_change = source.is_change; + type = source.type; + is_changed = source.is_changed; } @@ -136,4 +143,6 @@ << " / trdid = " << trdid << " / pktid = " << pktid + << " / type = " << type + << " / is_changed = " << is_changed << " / nline = " << nline << std::endl; } @@ -227,6 +236,7 @@ const addr_t nline, const size_t count, + const bool type, size_t &index, - const bool is_change=false) + const bool is_changed=false) { for ( size_t i=0 ; i r_cleanup_locked_index; // ivt index sc_signal r_cleanup_locked_is_updt; - sc_signal r_cleanup_locked_is_change; + sc_signal r_cleanup_locked_is_changed; + sc_signal r_cleanup_locked_is_read; sc_signal r_cleanup_miss_srcid; // srcid of write rsp Index: /branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 679) +++ /branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 680) @@ -2844,4 +2844,5 @@ nline, nb_copies, + false, index); @@ -3241,5 +3242,5 @@ r_read_to_cc_send_brdcast_req = not multi_req; r_read_to_cc_send_nline = nline; - //r_read_to_cc_send_srcid = m_cmd_read_srcid_fifo.read(); + r_read_to_cc_send_srcid = m_cmd_read_srcid_fifo.read(); //r_read_to_cc_send_is_shared = r_read_state.read() == ENTRY_SHARED; @@ -3276,4 +3277,5 @@ nline, r_read_count.read(), + true, //is a command read index); @@ -3449,5 +3451,5 @@ false, // multi_inval true, // it needs a read response - false, // acknowledge required + false, // acknowledge required m_cmd_read_srcid_fifo.read(), m_cmd_read_trdid_fifo.read(), @@ -3455,4 +3457,5 @@ nline, 0x01, + true, // is a command read index); @@ -4139,13 +4142,13 @@ else // invalid the line and send multi_inval or brdcast to cache L1, and set trt table to evict the line { - if(entry.state == ENTRY_EXCLUSIVE) - { - r_write_inval_trt_send = false; - } - else - { - r_write_inval_trt_send = true; - } - r_write_fsm = WRITE_INVAL_TRT_LOCK; + // if(entry.state == ENTRY_EXCLUSIVE) + // { + // r_write_inval_trt_send = false; + // } + // else + // { + // r_write_inval_trt_send = true; + // } + r_write_fsm = WRITE_INVAL_IVT_LOCK; } @@ -4155,14 +4158,14 @@ { // if a miss write matched with a trt wait situation(wait for dirty data), it must block the command write until the dirty data has arrived in memcache - if(r_write_to_cleanup_req.read() and - r_write_to_cleanup_nline.read() == nline) - { - std::cout << "hit write cleanup nline =" << std::hex << nline << std::endl; - r_write_fsm = WRITE_WAIT; - } - else - { + // if(r_write_to_cleanup_req.read() and + // r_write_to_cleanup_nline.read() == nline) + // { + // std::cout << "hit write cleanup nline =" << std::hex << nline << std::endl; + // r_write_fsm = WRITE_WAIT; + // } + // else + // { r_write_fsm = WRITE_MISS_TRT_LOCK; - } + // } } @@ -4419,5 +4422,5 @@ m_heap.write(r_write_next_ptr.read(),last_entry); - r_write_fsm = WRITE_INVAL_XRAM_REQ; //this is sure that this line is in shared state, it can be send to xram + r_write_fsm = WRITE_IDLE; #if DEBUG_MEMC_XRAM_RSP @@ -4904,12 +4907,14 @@ "MEMC ERROR in WRITE_INVAL_IVT_LOCK state: Bad DIR allocation"); - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and - "MEMC ERROR in WRITE_INVAL_IVT_LOCK state: Bad TRT allocation"); - - size_t set = m_y[(addr_t)(r_write_address.read())]; + //assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + // "MEMC ERROR in WRITE_INVAL_IVT_LOCK state: Bad TRT allocation"); + + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); bool cc_send_valid = not r_write_to_cc_send_multi_req.read() and - not r_write_to_cc_send_brdcast_req.read() and - (r_write_inval_trt_send.read() or not r_write_to_cleanup_req.read()); + not r_write_to_cc_send_brdcast_req.read() and + not (r_write_state.read() == ENTRY_EXCLUSIVE and r_write_to_cleanup_req.read()); + // (r_write_inval_trt_send.read() or not r_write_to_cleanup_req.read()); if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) @@ -4939,4 +4944,5 @@ nline, nb_copies, + false, // is a command write index); /*// std::cout << " trt wait nline =" << std::hex << nline @@ -4948,24 +4954,54 @@ << " / nb_copies = " << r_write_count.read() << std::endl; #endif + // for(size_t word=0 ; word data_vector; - data_vector.clear(); - for(size_t i=0; i (m_words,0), - data_vector ); + // register PUT request in TRT + // std::vector data_vector; + // data_vector.clear(); + // for(size_t i=0; i (m_words,0), + // data_vector ); // invalidate directory entry DirectoryEntry entry; - entry.state = ENTRY_INVALID; - entry.dirty = false; - entry.tag = 0; - entry.is_cnt = false; + entry.state = ENTRY_LOCKED; + entry.dirty = true; + entry.tag = r_write_tag.read(); + entry.is_cnt = 0; entry.lock = false; entry.owner.srcid = 0; @@ -5049,4 +5085,5 @@ bool not_last_multi_inval = (r_write_count.read() != 1) and not r_write_is_cnt.read(); bool multi_inval = not r_write_is_cnt.read(); + r_write_to_cc_send_multi_req = last_multi_inval; r_write_to_cc_send_brdcast_req = not multi_inval; @@ -5057,4 +5094,10 @@ r_write_next_ptr = r_write_ptr.read(); + if(r_write_state.read() == ENTRY_EXCLUSIVE) + { + r_write_to_cleanup_req = true; + r_write_to_cleanup_nline = m_nline[(addr_t)(r_write_address.read())]; + } + if( not last_multi_inval and multi_inval) { @@ -5063,15 +5106,14 @@ else { - if(r_write_inval_trt_send.read()) - { - r_write_fsm = WRITE_INVAL_XRAM_REQ; - } - else //the line is in exlusive state, must wait for the - //response of multi_inval in reason of receiving the updated data - { + // if(r_write_inval_trt_send.read()) + // { + // r_write_fsm = WRITE_INVAL_XRAM_REQ; + // } + // else //the line is in exlusive state, must wait for the + // //response of multi_inval in reason of receiving the updated data + // { r_write_fsm = WRITE_IDLE; - r_write_to_cleanup_req = true; - r_write_to_cleanup_nline = m_nline[(addr_t)(r_write_address.read())]; - } + + // } } #if DEBUG_MEMC_WRITE @@ -5904,4 +5946,5 @@ r_xram_rsp_victim_nline.read(), count_copies, + false, //unuse index); @@ -6642,5 +6685,5 @@ << " CLEANUP_LOCKED_IVT_LOCK> :" << "/ is_updt =" << m_ivt.is_update(index) - << "/ is_change =" << m_ivt.is_change(index) + << "/ is_changed =" << m_ivt.is_changed(index) << "/ match =" << match_inval << "/ need rsp =" << m_ivt.need_rsp(index) @@ -6654,7 +6697,8 @@ r_cleanup_locked_index = index; r_cleanup_locked_is_updt = m_ivt.is_update(index); - r_cleanup_locked_is_change = m_ivt.is_change(index); - - if( m_ivt.is_update(index) and not m_ivt.is_change(index)) + r_cleanup_locked_is_changed = m_ivt.is_changed(index); + r_cleanup_locked_is_read = m_ivt.is_read(index); + + if( m_ivt.is_update(index) and not m_ivt.is_changed(index)) { r_cleanup_fsm = CLEANUP_LOCKED_IVT_CLEAR; @@ -6712,9 +6756,12 @@ addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; - size_t match_cas_multi_inval = r_cas_to_cleanup_req.read() and - (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); + //size_t match_cas_multi_inval = r_cas_to_cleanup_req.read() and + // (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); + + size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; bool match_ll = ((r_cleanup_locked_pktid.read() & 0x07) == TYPE_LL); - DirectoryEntry entry; + + DirectoryEntry entry; entry.is_cnt = false; entry.lock = r_cleanup_lock.read(); @@ -6739,5 +6786,5 @@ } - if(r_cleanup_locked_is_updt.read() and not r_cleanup_locked_is_change.read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state. + if(r_cleanup_locked_is_updt.read() and not r_cleanup_locked_is_changed.read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state. { assert(r_cleanup_count.read() == 1 && " only one copy when cleanup fsm receives a req for is_updt command"); @@ -6748,5 +6795,5 @@ r_cleanup_fsm = CLEANUP_SEND_CLACK; } - else if(r_cleanup_locked_is_updt.read() and r_cleanup_locked_is_change.read()) + else if(r_cleanup_locked_is_updt.read() and r_cleanup_locked_is_changed.read()) { entry.state = ENTRY_SHARED; @@ -6762,5 +6809,5 @@ } - if((r_cleanup_locked_pktid.read() & 0x7) == 0x03) + if((r_cleanup_locked_pktid.read() & 0x7) == TYPE_READ_INS_MISS) { entry.owner.inst = true; @@ -6776,15 +6823,21 @@ else // cas, getm, one copy updated in dir { - if(match_cas_multi_inval) + if(match_cas_inval) { entry.state = ENTRY_SHARED; entry.count = 0; } + else if(r_cleanup_locked_is_read.read()) + { + entry.state = ENTRY_EXCLUSIVE; + entry.count = 1; + entry.owner.srcid = r_cleanup_locked_srcid.read(); + } else { entry.state = ENTRY_EXCLUSIVE; - entry.count = 1; - } - entry.owner.srcid = r_cleanup_locked_srcid.read(); + entry.count = 0; + } + entry.owner.inst = 0; r_cleanup_fsm = CLEANUP_LOCKED_RSP; @@ -6814,4 +6867,6 @@ if(r_cleanup_to_tgt_rsp_req.read()) break; + size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; + r_cleanup_to_tgt_rsp_req = true; r_cleanup_to_tgt_rsp_srcid = r_cleanup_locked_srcid.read(); @@ -6819,5 +6874,5 @@ r_cleanup_to_tgt_rsp_nline = r_cleanup_nline.read(); - if(r_cleanup_locked_is_change.read() and r_cleanup_locked_is_updt.read()) + if(r_cleanup_locked_is_changed.read() and r_cleanup_locked_is_updt.read()) { r_cleanup_to_tgt_rsp_pktid = r_cleanup_locked_pktid.read(); // rsp for is_updt in shared state @@ -6830,5 +6885,5 @@ if(r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_cleanup_nline.read()) and // rsp for LL or pheriph - (r_cleanup_locked_is_change.read() and r_cleanup_locked_is_updt.read())) + (r_cleanup_locked_is_changed.read() and r_cleanup_locked_is_updt.read())) { r_cleanup_to_tgt_rsp_ll_key = r_read_to_multi_ack_ll_key.read(); @@ -6851,13 +6906,8 @@ } - if(r_cas_to_cleanup_req.read()) - { - r_cas_to_cleanup_req = false; - r_cleanup_to_tgt_rsp_type = true; - } - else - { - r_cleanup_to_tgt_rsp_type = false; - } + if(r_write_to_cleanup_req.read()) + r_write_to_cleanup_req = false; + + r_cleanup_to_tgt_rsp_type = not r_cleanup_locked_is_read.read(); for(size_t i = 0; i