Changeset 682

Timestamp:

Apr 23, 2014, 4:45:19 PM (11 years ago)

Author:

haoliu

Message:

MESI Bug fixed for llsc operation in vci_mem_cache component

Location:

branches/MESI/modules

Files:

• vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (3 diffs)
• vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (10 diffs)

branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -1297 +1297 @@
                     // we request a VCI transaction
                     r_icache_fsm      = ICACHE_MISS_SELECT;
-#if DEBUG_ICACHE
-if ( m_debug_activated or m_ireq.addr == 0x11020 )
-std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 
-          << " : PADDR = " << std::hex << paddr << std::endl;
-#endif
-                   r_icache_miss_req = true;
+                    r_icache_miss_req = true;
                 }
                 else if (cache_state == CACHE_SLOT_STATE_ZOMBI )        // pending cleanup
@@ -2832 +2827 @@
                                     m_drsp.rdata   = cache_rdata;
 #if DEBUG_DCACHE
-if ( m_debug_activated or m_drsp.rdata == 0x11020)
+if ( m_debug_activated )
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
           << " READ HIT in dcache" 
@@ -2978 +2973 @@
                     }
 #if DEBUG_DCACHE
-if ( m_debug_activated or m_dreq.wdata == 0x11020)
+if ( m_debug_activated )
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
       << " WRITE REQ " 

branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -3184 +3184 @@
                             << " / count = " <<std::dec << entry.count
                             << " / copy = " <<std::dec << entry.owner.srcid
+                            << " / is_inst = " << entry.owner.inst 
                             << " / is_cnt = " << entry.is_cnt << std::endl;
                         if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;
@@ -5954 +5955 @@
 
                     }
-                    if (!r_xram_rsp_victim_coherent.read())
-                    {
-                        addr_t min = r_xram_rsp_victim_nline.read()*m_words*4 ;
-                        addr_t max = r_xram_rsp_victim_nline.read()*m_words*4 + (m_words - 1)*4;
-                        m_llsc_table.sw(min, max);
-                    }
+                   // if (!r_xram_rsp_victim_coherent.read())
+                   // {
+                   //     addr_t min = r_xram_rsp_victim_nline.read()*m_words*4 ;
+                   //     addr_t max = r_xram_rsp_victim_nline.read()*m_words*4 + (m_words - 1)*4;
+                   //     m_llsc_table.sw(min, max);
+                   // }
 #if DEBUG_MEMC_XRAM_RSP
                     if(m_debug)
@@ -6759 +6760 @@
                     //                              (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); 
 
-                    size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS;
+                    //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS;
+                    //size_t match_sc_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_SC;
 
                     bool match_ll = ((r_cleanup_locked_pktid.read() & 0x07) == TYPE_LL);
@@ -6772 +6774 @@
                     if( not r_cleanup_contains_data.read() ) 
                     {
+                        if(r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) 
+                        //update the line with the data saved in write_to_cleanup_data table if the cleanup without data
+                        {
+                            for (size_t word = 0; word < m_words; word ++)
+                            {
+                                m_cache_data.write(way, set, word, r_write_to_cleanup_data[word].read(), r_write_to_cleanup_be[word].read());
+                            }
+                            //addr_t min = r_cleanup_nline.read()*m_words*4 ;
+                            //addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;
+                            //m_llsc_table.sw(min, max);
+                        }
+
                         size_t set = m_y[(addr_t)(cleanup_address)];
                         m_cache_data.read_line(way, set, r_cleanup_data); 
@@ -6781 +6795 @@
                             m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF);
                         }
-                        addr_t min = r_cleanup_nline.read()*m_words*4 ;
-                        addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;
-                        m_llsc_table.sw(min, max);
+
+                        if((r_cleanup_locked_pktid.read() & 0x7) != TYPE_SC) 
+                        {
+                            addr_t min = r_cleanup_nline.read()*m_words*4 ;
+                            addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;
+                            m_llsc_table.sw(min, max);
+                        }
                     }
 
@@ -6823 +6841 @@
                     else // cas, getm, one copy updated in dir
                     {
-                        if(match_cas_inval)
-                        {
-                            entry.state     = ENTRY_SHARED;
-                            entry.count     = 0;
-                        }
-                        else if(r_cleanup_locked_is_read.read())
+                       // if(match_cas_inval or match_sc_inval)
+                       // {
+                       //     entry.state     = ENTRY_SHARED;
+                       //     entry.count     = 0;
+                       // }
+                        if(r_cleanup_locked_is_read.read())
                         {
                             entry.state         = ENTRY_EXCLUSIVE;
@@ -6867 +6885 @@
                     if(r_cleanup_to_tgt_rsp_req.read()) break;
 
-                    size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS;
+                    //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS;
 
                     r_cleanup_to_tgt_rsp_req     = true;
@@ -6906 +6924 @@
                     }
 
-                    if(r_write_to_cleanup_req.read())
+                    if(r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read())
                         r_write_to_cleanup_req = false;
 
@@ -7370 +7388 @@
                                           std::vector<be_t> (m_words,0),
                                           data_vector);
+
+                                addr_t min = r_cleanup_nline.read()*m_words*4 ;
+                                addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;
+                                m_llsc_table.sw(min, max);
                             }
                             //std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl;
@@ -11756 +11778 @@
                         DspinDhccpParam::dspin_set(
                                 flit,
-                                DspinDhccpParam::TYPE_MULTI_INVAL_DATA,
+                                multi_inval_type,
                                 DspinDhccpParam::M2P_TYPE);
                     }