Changeset 686 for branches/MESI
- Timestamp:
- May 13, 2014, 12:06:31 PM (11 years ago)
- Location:
- branches/MESI/modules
- Files:
-
- 5 edited
-
vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (4 diffs)
-
vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (27 diffs)
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vci_mem_cache/caba/source/include/mem_cache_directory.h (modified) (1 diff)
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vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (1 diff)
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vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (77 diffs)
Legend:
- Unmodified
- Added
- Removed
-
branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r675 r686 371 371 sc_signal<paddr_t> r_icache_vci_paddr; // physical address 372 372 sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor 373 373 sc_signal<bool> r_icache_read_state; 374 374 // icache miss handling 375 375 sc_signal<size_t> r_icache_miss_way; // selected way for cache update … … 420 420 sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op 421 421 // registers written in P0 stage (used in P1 stage) 422 sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage 423 sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage 422 sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) 424 423 sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) 425 sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc)426 424 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 427 425 sc_signal<paddr_t> r_dcache_save_paddr; // physical address … … 549 547 sc_signal<bool> r_dcache_updt_data_req; 550 548 sc_signal<bool> r_dcache_updt_dir_req; 551 sc_signal<bool> r_dcache_rsp_state;552 549 sc_signal<bool> r_dcache_cas_islocal; // cas is done locally 553 550 … … 561 558 562 559 //MESI 563 sc_signal<bool> r_icache_read_state;564 560 sc_signal<bool> r_dcache_read_state; 565 561 sc_signal<bool> r_dcache_read_for_modify; // a command intent to write 566 sc_signal<bool> r_dcache_r ead_hit; // a command intent to write hit in L1562 sc_signal<bool> r_dcache_rsp_state; 567 563 568 564 /////////////////////////////////// -
branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r682 r686 270 270 r_icache_vci_paddr("r_icache_vci_paddr"), 271 271 r_icache_vaddr_save("r_icache_vaddr_save"), 272 r_icache_read_state("r_icache_read_state"), 272 273 273 274 r_icache_miss_way("r_icache_miss_way"), … … 304 305 r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), 305 306 306 r_dcache_wbuf_req("r_dcache_wbuf_req"), 307 r_dcache_updt_data_req("r_dcache_updt_data_req"), 308 r_dcache_updt_dir_req("r_dcache_updt_dir_req"), 307 r_dcache_save_wdata("r_dcache_save_wdata"), 308 309 309 r_dcache_save_vaddr("r_dcache_save_vaddr"), 310 r_dcache_save_wdata("r_dcache_save_wdata"),311 310 r_dcache_save_be("r_dcache_save_be"), 312 311 r_dcache_save_paddr("r_dcache_save_paddr"), … … 332 331 r_dcache_vci_sc_data("r_dcache_vci_sc_data"), 333 332 333 334 334 335 r_dcache_xtn_way("r_dcache_xtn_way"), 335 336 r_dcache_xtn_set("r_dcache_xtn_set"), … … 354 355 r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), 355 356 r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), 356 // r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),357 // r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),358 // r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),359 357 r_dcache_tlb_way("r_dcache_tlb_way"), 360 358 r_dcache_tlb_set("r_dcache_tlb_set"), … … 374 372 r_dcache_cc_send_way("r_dcache_cc_send_way"), 375 373 r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"), 374 r_dcache_updt_data_req("r_dcache_updt_data_req"), 375 r_dcache_updt_dir_req("r_dcache_updt_dir_req"), 376 r_dcache_read_for_modify("r_dcache_read_for_modify"), 377 r_dcache_rsp_state("r_dcache_rsp_state"), 376 378 377 379 r_vci_cmd_fsm("r_vci_cmd_fsm"), … … 387 389 r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth 388 390 r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16), // 2 words depth 389 // r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth390 391 r_cc_send_data_fifo("r_cc_send_data_fifo", 2), 391 392 … … 409 410 r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"), 410 411 r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"), 412 413 411 414 r_cc_receive_dcache_srcid("r_cc_receive_dcache_srcid"), 412 413 r_icache_read_state("r_icache_read_state"),414 r_dcache_rsp_state("r_dcache_rsp_state"),415 415 416 416 r_iss(this->name(), proc_id), … … 519 519 << " | MMU = " << r_mmu_mode.read(); 520 520 if (r_dcache_updt_data_req.read() ) std::cout << " | P1_UPDT"; 521 if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF";522 521 std::cout << std::endl; 523 522 … … 814 813 r_icache_clack_req = false; 815 814 816 // No pending write in pipeline817 r_dcache_wbuf_req = false;818 819 815 // No request from DCACHE_FSM to CMD_FSM 820 816 r_dcache_vci_miss_req = false; … … 1010 1006 bool vci_rsp_fifo_dcache_put = false; 1011 1007 uint32_t vci_rsp_fifo_dcache_data = 0; 1012 bool vci_rsp_fifo_rpktid_get = false;1013 bool vci_rsp_fifo_rpktid_put = false;1014 bool vci_rsp_fifo_rpktid = false;1015 1008 1016 1009 // FIFO for cleanup data updt … … 1018 1011 bool cleanup_data_updt_fifo_dcache_put = false; 1019 1012 uint32_t cleanup_data_updt_fifo_dcache_data = 0; 1020 1021 // updt fifo1022 bool cc_receive_updt_fifo_get = false;1023 bool cc_receive_updt_fifo_put = false;1024 uint32_t cc_receive_updt_fifo_be = 0;1025 uint32_t cc_receive_updt_fifo_data = 0;1026 bool cc_receive_updt_fifo_eop = false;1027 1013 1028 1014 #ifdef INSTRUMENTATION … … 2283 2269 2284 2270 bool tlb_inval_required = false; // request TLB inval after cache update 2285 bool wbuf_write_miss = false; // miss a WBUF write request2286 2271 bool updt_data_request = false; // request DCACHE update in P1 stage 2287 2272 bool updt_dir_request = false; // request DCACHE update in P1 stage 2288 bool wbuf_request = false; // request WBUF write in P1 stage2289 2290 2273 2291 2274 // physical address computation : systematic DTLB access (if activated) … … 2293 2276 { 2294 2277 2295 //#if 1 2296 //// @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE2297 //if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {2298 //std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl;2299 //raise(SIGINT);2300 //}2301 //#endif2278 #if 0 2279 // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE 2280 if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { 2281 std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; 2282 raise(SIGINT); 2283 } 2284 #endif 2302 2285 2303 2286 if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated … … 2938 2921 r_dcache_vci_miss_req = true; 2939 2922 r_dcache_read_for_modify = true; 2940 r_dcache_read_hit = true;2941 2923 r_dcache_miss_type = PROC_MISS; 2942 2924 r_dcache_fsm = DCACHE_MISS_WAIT; … … 2965 2947 r_dcache_fsm = DCACHE_MISS_SELECT; 2966 2948 r_dcache_read_for_modify = true; 2967 r_dcache_read_hit = false;2968 2949 } 2969 2950 else … … 3727 3708 } 3728 3709 #endif 3710 // checking llsc reservation buffer 3711 if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) 3712 r_dcache_llsc_valid = false; 3729 3713 3730 3714 if (r_cas_cache_state.read() == CACHE_SLOT_STATE_EXCLUSIVE or … … 3776 3760 // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set 3777 3761 r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); 3778 3779 // checking llsc reservation buffer3780 if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )3781 r_dcache_llsc_valid = false;3782 3783 3762 // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state 3784 3763 r_dcache_vci_cas_req = true; … … 4706 4685 vci_rsp_fifo_dcache_get = true; 4707 4686 4708 // r_dcache_rsp_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid4709 vci_rsp_fifo_rpktid_get = true;4710 4711 4712 4687 r_dcache_miss_word = r_dcache_miss_word.read() + 1; 4713 4688 … … 4789 4764 #endif 4790 4765 4791 r_dcache_fsm = DCACHE_MISS_BACKOFF;4766 //r_dcache_fsm = DCACHE_MISS_BACKOFF; 4792 4767 r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; 4793 4768 r_dcache_count_begin = 0; … … 4805 4780 #endif 4806 4781 r_dcache_count_backoff = 0; 4807 size_t way = r_dcache_miss_way.read(); 4808 size_t set = r_dcache_miss_set.read(); 4782 4809 4783 if ( r_dcache_rsp_state.read()) 4810 4784 { … … 4831 4805 << " / SET = " << r_dcache_miss_set.read() << std::endl; 4832 4806 #endif 4833 // reset directory extension4834 if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;4835 else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;4836 else r_dcache_fsm = DCACHE_IDLE;4837 }4807 } 4808 // reset directory extension 4809 if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; 4810 else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; 4811 else r_dcache_fsm = DCACHE_IDLE; 4838 4812 } 4839 4813 break; … … 5290 5264 else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) 5291 5265 { 5292 assert(( state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI) && " CC_UPDT WITH A NO INVALID STATE");5266 assert(((state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI)) && " CC_UPDT WITH A NO INVALID STATE"); 5293 5267 5294 5268 r_dcache_cc_send_multi_ack_miss = true; … … 5304 5278 // signaling matching 5305 5279 5306 // if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)5307 // {5308 // if(r_dcache_read_for_modify.read() and (r_dcache_miss_type == PROC_MISS))5309 // {5310 // r_dcache_miss_inval = false;5311 // r_dcache_miss_updt = true;5312 // r_dcache_fsm = r_dcache_fsm_cc_save.read();5313 // }5314 // else5315 // {5316 // // r_dcache_cc_send_multi_ack_miss = true;5317 // r_dcache_cc_send_multi_ack_miss = false;5318 // r_dcache_miss_inval = false;5319 // r_dcache_cc_state = CACHE_SLOT_STATE_INVALID;5320 // r_dcache_fsm = DCACHE_CC_UPDT;5321 // }5322 // }5323 // else5324 // {5325 // if(r_cc_receive_dcache_srcid.read() == m_srcid and r_cc_receive_brdcast.read() and (r_dcache_miss_type == PROC_MISS))5326 // {5327 // assert(r_dcache_read_for_modify.read() && "miss inval for a miss getm in type of brdcast, this is impossible!!");5328 // r_dcache_miss_inval = false;5329 // r_cc_receive_dcache_req = false;5330 // }5331 // else if(not r_cc_receive_brdcast.read() and r_dcache_read_for_modify.read() and (r_dcache_miss_type == PROC_MISS))5332 // {5333 // r_dcache_miss_inval = false;5334 // r_dcache_miss_updt = true;5335 // }5336 // else5337 // {5338 // r_cc_receive_dcache_req = false;5339 // r_dcache_miss_inval = true;5340 // }5341 // r_dcache_fsm = r_dcache_fsm_cc_save.read();5342 // }5343 5344 5280 #if DEBUG_DCACHE 5345 5281 if ( m_debug_activated ) … … 5360 5296 5361 5297 // CC request handler 5362 5363 5364 5365 5298 #ifdef INSTRUMENTATION 5366 5299 m_cpt_dcache_dir_read++; … … 5542 5475 // after possible invalidation of copies in TLBs 5543 5476 { 5544 size_t word = r_dcache_cc_word.read();5545 5477 size_t way = r_dcache_cc_way.read(); 5546 5478 size_t set = r_dcache_cc_set.read(); … … 6523 6455 vci_rsp_fifo_dcache_put, 6524 6456 vci_rsp_fifo_dcache_data); 6525 //BUG pktid 6526 // r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get, 6527 // vci_rsp_fifo_rpktid_put, 6528 // vci_rsp_fifo_rpktid); 6529 // 6457 6530 6458 r_cc_send_data_fifo.update(cleanup_data_updt_fifo_dcache_get, 6531 6459 cleanup_data_updt_fifo_dcache_put, … … 6614 6542 p_vci.be = 0xF; 6615 6543 p_vci.trdid = 0; 6616 if(r_dcache_read_for_modify.read() and r_dcache_read_hit.read()) 6617 p_vci.pktid = TYPE_WRITE + 0x8; 6618 else if(r_dcache_read_for_modify.read() and not r_dcache_read_hit.read()) 6544 if(r_dcache_read_for_modify.read()) 6619 6545 p_vci.pktid = TYPE_WRITE; 6620 6546 else -
branches/MESI/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
r670 r686 361 361 // - way : (return argument) the way to evince 362 362 ///////////////////////////////////////////////////////////////////// 363 DirectoryEntry select(const size_t &set, size_t &way)363 DirectoryEntry select(const size_t &set, int &way) 364 364 { 365 365 assert( (set < m_sets) -
branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r680 r686 225 225 WRITE_MISS_TRT_DATA, 226 226 WRITE_MISS_XRAM_REQ, 227 WRITE_INVAL_TRT_LOCK,228 227 WRITE_INVAL_IVT_LOCK, 229 WRITE_DIR_INVAL, 230 WRITE_INVAL_CC_SEND, 231 WRITE_INVAL_XRAM_REQ 228 WRITE_INVAL_CC_SEND 232 229 }; 233 230 -
branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r682 r686 193 193 "WRITE_MISS_TRT_DATA", 194 194 "WRITE_MISS_XRAM_REQ", 195 "WRITE_INVAL_TRT_LOCK",196 195 "WRITE_INVAL_IVT_LOCK", 197 "WRITE_DIR_INVAL", 198 "WRITE_INVAL_CC_SEND", 199 "WRITE_INVAL_XRAM_REQ" 196 "WRITE_INVAL_CC_SEND" 200 197 }; 201 198 const char *ixr_rsp_fsm_str[] = … … 465 462 466 463 r_read_fsm( "r_read_fsm" ), 464 m_read_to_cc_send_inst_fifo("m_read_to_cc_send_inst_fifo",8), 465 m_read_to_cc_send_srcid_fifo("m_read_to_cc_send_srcid_fifo",8), 467 466 468 467 r_write_fsm( "r_write_fsm" ), … … 479 478 m_cas_to_cc_send_inst_fifo("m_cas_to_cc_send_inst_fifo",8), 480 479 m_cas_to_cc_send_srcid_fifo("m_cas_to_cc_send_srcid_fifo",8), 481 482 m_read_to_cc_send_inst_fifo("m_read_to_cc_send_inst_fifo",8),483 m_read_to_cc_send_srcid_fifo("m_read_to_cc_send_srcid_fifo",8),484 485 480 r_ixr_rsp_fsm("r_ixr_rsp_fsm"), 486 481 r_xram_rsp_fsm("r_xram_rsp_fsm"), … … 2160 2155 assert(((entry.count == 1) or (entry.count == 0)) && "multi ack for a ll request, count is 1"); 2161 2156 r_multi_ack_fsm = MULTI_ACK_DIR_UPDT; 2162 //r_multi_ack_rsp_shared = false;2163 2157 } 2164 2158 else 2165 2159 { 2166 2160 r_multi_ack_fsm = MULTI_ACK_HEAP_REQ; 2167 //r_multi_ack_rsp_shared = true;2168 2161 } 2169 2162 break; … … 2172 2165 case MULTI_ACK_IVT_CHANGE: // release all locks and retry from beginning 2173 2166 { 2174 //if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break;2175 2167 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK ) 2176 2168 { … … 2217 2209 r_multi_ack_data[word]); 2218 2210 } 2211 // addr_t min = r_multi_ack_nline.read()*m_words*4 ; 2212 // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4; 2213 // m_llsc_table.sw(min, max); 2214 2219 2215 } 2220 2216 else … … 2364 2360 r_multi_ack_data[word]); 2365 2361 } 2362 2363 // addr_t min = r_multi_ack_nline.read()*m_words*4 ; 2364 // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4; 2365 // m_llsc_table.sw(min, max); 2366 2366 2367 } 2367 2368 else … … 3146 3147 r_read_fsm = READ_IVT_INVAL_LOCK; 3147 3148 } 3149 3150 addr_t min = m_cmd_read_addr_fifo.read(); 3151 addr_t max = m_cmd_read_addr_fifo.read() + m_cmd_read_length_fifo.read()*4; 3152 m_llsc_table.sw(min, max); 3148 3153 } 3149 3154 else // a read miss request … … 3254 3259 r_read_to_cleanup_req = true; 3255 3260 } 3261 3256 3262 r_read_to_cc_send_type = true; //CC_INVAL 3257 3258 // if(not match_send) 3259 // { 3260 read_to_cc_send_fifo_srcid = r_read_copy.read(); 3261 read_to_cc_send_fifo_inst = r_read_copy_inst.read(); 3262 read_to_cc_send_fifo_put = multi_req; 3263 // } 3264 r_read_next_ptr = r_read_ptr.read(); 3265 3266 // if(((m_cmd_read_pktid_fifo.read() & 0x8) == 0x8) and (r_read_state.read() == ENTRY_SHARED)) 3267 // ivt_send_count = r_read_count.read() - 1; 3268 // else 3269 // ivt_send_count = r_read_count.read(); 3270 3263 read_to_cc_send_fifo_srcid = r_read_copy.read(); 3264 read_to_cc_send_fifo_inst = r_read_copy_inst.read(); 3265 read_to_cc_send_fifo_put = multi_req; 3266 r_read_next_ptr = r_read_ptr.read(); 3267 3271 3268 m_ivt.set(false, // it's an inval transaction 3272 3269 not multi_req, // multi_inval or brdcast … … 3326 3323 HeapEntry entry = m_heap.read(r_read_next_ptr.read()); 3327 3324 3328 // bool match_send = ( entry.owner.srcid == m_cmd_read_srcid_fifo.read()) and3329 // ( entry.owner.inst == 0);3330 // if(not match_send)3331 // {3332 3325 read_to_cc_send_fifo_srcid = entry.owner.srcid; 3333 3326 read_to_cc_send_fifo_inst = entry.owner.inst; 3334 3327 read_to_cc_send_fifo_put = true; 3335 // } 3336 // if(read_to_cc_send_inst_fifo.wok()) always not full 3337 r_read_next_ptr = entry.next; 3328 r_read_next_ptr = entry.next; 3329 3338 3330 if(entry.next == r_read_next_ptr.read()) // last copy 3339 3331 { … … 3404 3396 r_read_to_cc_send_multi_req.read() or 3405 3397 r_read_to_cc_send_brdcast_req.read() or 3406 (r_read_to_multi_ack_req.read() and r_read_need_block.read())) // ll or read not align block the request3398 (r_read_to_multi_ack_req.read() and r_read_need_block.read())) // ll request or the read request is not align a cache line 3407 3399 { 3408 3400 r_read_fsm = READ_WAIT; … … 3462 3454 3463 3455 r_read_to_cc_send_ivt_index = index; 3464 r_read_fsm = READ_IDLE;3465 cmd_read_fifo_get = true;3456 r_read_fsm = READ_IDLE; 3457 cmd_read_fifo_get = true; 3466 3458 3467 3459 #if DEBUG_MEMC_READ … … 4112 4104 DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); 4113 4105 4114 size_t set = m_y[(addr_t)(r_write_address.read())];4115 addr_t nline = m_nline[(addr_t)(r_write_address.read())];4116 4106 if(entry.state != ENTRY_INVALID) // hit 4117 4107 { … … 4143 4133 else // invalid the line and send multi_inval or brdcast to cache L1, and set trt table to evict the line 4144 4134 { 4145 // if(entry.state == ENTRY_EXCLUSIVE)4146 // {4147 // r_write_inval_trt_send = false;4148 // }4149 // else4150 // {4151 // r_write_inval_trt_send = true;4152 // }4153 4135 r_write_fsm = WRITE_INVAL_IVT_LOCK; 4154 4155 4136 } 4156 4137 } … … 4158 4139 else // miss 4159 4140 { 4160 // if a miss write matched with a trt wait situation(wait for dirty data), it must block the command write until the dirty data has arrived in memcache 4161 // if(r_write_to_cleanup_req.read() and 4162 // r_write_to_cleanup_nline.read() == nline) 4163 // { 4164 // std::cout << "hit write cleanup nline =" << std::hex << nline << std::endl; 4165 // r_write_fsm = WRITE_WAIT; 4166 // } 4167 // else 4168 // { 4169 r_write_fsm = WRITE_MISS_TRT_LOCK; 4170 // } 4141 r_write_fsm = WRITE_MISS_TRT_LOCK; 4171 4142 } 4172 4143 … … 4187 4158 break; 4188 4159 } 4189 ////////////////////4190 // case WRITE_IVT_LOCK_HIT_WB:4191 // {4192 // if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)4193 // {4194 //4195 // size_t index = 0;4196 // bool match_inval;4197 // addr_t nline = m_nline[(addr_t)(r_write_address.read())];4198 //4199 // //std::cout << "WRITE on NCC on line" << std::hex << nline << std::dec << std::endl;4200 // //if there is a matched updt req, we should wait until it is over. Because4201 // //we need the lastest updt data.4202 // match_inval = m_ivt.search_inval(nline, index);4203 //4204 // assert ((r_write_count.read() == 1) and "NCC to CC req without copy");4205 //4206 // if( not match_inval and4207 // not r_write_to_cc_send_multi_req.read() and4208 // not r_write_to_cc_send_brdcast_req.read() )4209 // {4210 // r_write_to_cc_send_multi_req = true;4211 // r_write_to_cc_send_dest = r_write_copy;4212 // r_write_to_cc_send_nline = nline;4213 // r_write_to_cleanup_req = true;4214 // r_write_to_cleanup_nline = nline;4215 // write_to_cc_send_fifo_put = true;4216 // write_to_cc_send_fifo_inst = r_write_copy_inst.read();4217 // write_to_cc_send_fifo_srcid = r_write_copy.read();4218 //4219 // m_ivt.set(false, // it's an inval transaction4220 // false, // it's not a broadcast4221 // false, // it needs no response4222 // false, // no acknowledge required4223 // m_cmd_write_srcid_fifo.read(), //never read, used for debug4224 // m_cmd_write_trdid_fifo.read(), //never read, used for debug4225 // m_cmd_write_pktid_fifo.read(), //never read, used for debug4226 // nline,4227 // 0x1, //Expect only one answer4228 // index);4229 // }4230 // r_write_fsm = WRITE_WAIT;4231 //#if DEBUG_MEMC_WRITE4232 // if(m_debug)4233 // {4234 // std::cout << " <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> get access to the UPT: "4235 // << " Inval requested = " << (not match_inval and not r_write_to_cc_send_req.read())4236 // << std::endl;4237 // }4238 //#endif4239 // break;4240 // }4241 //#if DEBUG_MEMC_WRITE4242 // if(m_debug)4243 // {4244 // std::cout << " <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> failed to access to the IVT: "4245 // << std::endl;4246 // }4247 //#endif4248 // break;4249 // }4250 //4251 4160 /////////////////// 4252 4161 case WRITE_DIR_HIT: … … 4276 4185 r_write_fsm = WRITE_RSP; 4277 4186 4278 // owner is true when the the first registered copy is the writer itself4279 //bool owner = (((r_write_copy.read() == r_write_srcid.read())4280 // ) and not r_write_copy_inst.read());4281 4282 // no_update is true when there is no need for coherence transaction4283 // bool no_update = ( (r_write_count.read() == 0) or4284 // (owner and (r_write_count.read() == 1) and4285 // ((r_write_pktid.read() & 0x7) != TYPE_SC)));4286 4287 // write data in the cache if no coherence transaction4288 //if(no_update)4289 //{4290 // SC command but zero copies4291 4187 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 4292 4188 { … … 4300 4196 4301 4197 } 4302 //}4303 4304 //if (owner and not no_update and ((r_write_pktid.read() & 0x7) != TYPE_SC))4305 //{4306 // r_write_count = r_write_count.read() - 1;4307 //}4308 4309 //if(no_update)4310 // // Write transaction completed4311 //{4312 // r_write_fsm = WRITE_RSP;4313 //}4314 //else4315 // // coherence update required4316 //{4317 // if( not r_write_to_cc_send_multi_req.read() and4318 // not r_write_to_cc_send_brdcast_req.read() and4319 // not r_write_to_cc_send_req.read() )4320 // {4321 // r_write_fsm = WRITE_UPT_LOCK;4322 // }4323 // else4324 // {4325 // r_write_fsm = WRITE_WAIT;4326 // }4327 //}4328 4198 4329 4199 #if DEBUG_MEMC_WRITE … … 4432 4302 break; 4433 4303 } 4434 4435 //////////////////4436 // case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM4437 // // and write the first copy in the FIFO4438 // // send the request if only one copy4439 // {4440 // assert( not r_write_to_cc_send_multi_req.read() and4441 // not r_write_to_cc_send_brdcast_req.read() and4442 // not r_write_to_cc_send_req.read() and4443 // "Error in VCI_MEM_CACHE : pending multicast or broadcast\n"4444 // "transaction in WRITE_UPT_REQ state"4445 // );4446 //4447 //4448 // r_write_to_cc_send_brdcast_req = false;4449 // r_write_to_cc_send_trdid = r_write_ivt_index.read();4450 // r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())];4451 // r_write_to_cc_send_index = r_write_word_index.read();4452 // r_write_to_cc_send_count = r_write_word_count.read();4453 //4454 // for(size_t i=0; i<m_words ; i++) r_write_to_cleanup_be[i]=r_write_be[i].read();4455 //4456 // size_t min = r_write_word_index.read();4457 // size_t max = r_write_word_index.read() + r_write_word_count.read();4458 // for(size_t i=min ; i<=max ; i++) r_write_to_cleanup_data[i] = r_write_data[i];4459 //4460 // if ((r_write_copy.read() != r_write_srcid.read()) or4461 // ((r_write_pktid.read() & 0x7) == TYPE_SC) or4462 // r_write_copy_inst.read())4463 // {4464 // // put the first srcid in the fifo4465 // write_to_cc_send_fifo_put = true;4466 // write_to_cc_send_fifo_inst = r_write_copy_inst.read();4467 // write_to_cc_send_fifo_srcid = r_write_copy.read();4468 // if(r_write_count.read() == 1)4469 // {4470 // r_write_fsm = WRITE_IDLE;4471 // r_write_to_cc_send_multi_req = true;4472 // }4473 // else4474 // {4475 // r_write_fsm = WRITE_UPT_NEXT;4476 // r_write_to_dec = false;4477 //4478 // }4479 // }4480 // else4481 // {4482 // r_write_fsm = WRITE_UPT_NEXT;4483 // r_write_to_dec = false;4484 // }4485 //4486 //#if DEBUG_MEMC_WRITE4487 // if(m_debug)4488 // {4489 // std::cout4490 // << " <MEMC " << name()4491 // << " WRITE_UPT_REQ> Post first request to CC_SEND FSM"4492 // << " / srcid = " << std::dec << r_write_copy.read()4493 // << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl;4494 //4495 // if(r_write_count.read() == 1)4496 // std::cout << " ... and this is the last" << std::endl;4497 // }4498 //#endif4499 // break;4500 // }4501 //4502 // ///////////////////4503 // case WRITE_UPT_NEXT:4504 // {4505 // // continue the multi-update request to CC_SEND fsm4506 // // when there is copies in the heap.4507 // // if one copy in the heap is the writer itself4508 // // the corresponding SRCID should not be written in the fifo,4509 // // but the UPT counter must be decremented.4510 // // As this decrement is done in the WRITE_UPT_DEC state,4511 // // after the last copy has been found, the decrement request4512 // // must be registered in the r_write_to_dec flip-flop.4513 //4514 // HeapEntry entry = m_heap.read(r_write_ptr.read());4515 //4516 // bool dec_upt_counter;4517 //4518 // // put the next srcid in the fifo4519 // if ((entry.owner.srcid != r_write_srcid.read()) or4520 // ((r_write_pktid.read() & 0x7) == TYPE_SC) or4521 // entry.owner.inst)4522 // {4523 // dec_upt_counter = false;4524 // write_to_cc_send_fifo_put = true;4525 // write_to_cc_send_fifo_inst = entry.owner.inst;4526 // write_to_cc_send_fifo_srcid = entry.owner.srcid;4527 //4528 //#if DEBUG_MEMC_WRITE4529 // if(m_debug)4530 // {4531 // std::cout << " <MEMC " << name() << " WRITE_UPT_NEXT> Post another request to CC_SEND FSM"4532 // << " / heap_index = " << std::dec << r_write_ptr.read()4533 // << " / srcid = " << std::dec << r_write_copy.read()4534 // << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl;4535 // if(entry.next == r_write_ptr.read())4536 // std::cout << " ... and this is the last" << std::endl;4537 // }4538 //#endif4539 // }4540 // else // the UPT counter must be decremented4541 // {4542 // dec_upt_counter = true;4543 //4544 //#if DEBUG_MEMC_WRITE4545 // if(m_debug)4546 // {4547 // std::cout << " <MEMC " << name() << " WRITE_UPT_NEXT> Skip one entry in heap matching the writer"4548 // << " / heap_index = " << std::dec << r_write_ptr.read()4549 // << " / srcid = " << std::dec << r_write_copy.read()4550 // << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl;4551 // if(entry.next == r_write_ptr.read())4552 // std::cout << " ... and this is the last" << std::endl;4553 // }4554 //#endif4555 // }4556 //4557 // // register the possible UPT decrement request4558 // r_write_to_dec = dec_upt_counter or r_write_to_dec.read();4559 //4560 // if(not m_write_to_cc_send_inst_fifo.wok())4561 // {4562 // std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl4563 // << "The write_to_cc_send_fifo should not be full" << std::endl4564 // << "as the depth should be larger than the max number of copies" << std::endl;4565 // exit(0);4566 // }4567 //4568 // r_write_ptr = entry.next;4569 //4570 // if(entry.next == r_write_ptr.read()) // last copy4571 // {4572 // r_write_to_cc_send_multi_req = true;4573 // if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC;4574 // else r_write_fsm = WRITE_IDLE;4575 // }4576 // break;4577 // }4578 //4579 // //////////////////4580 // case WRITE_UPT_DEC:4581 // {4582 // // If the initial writer has a copy, it should not4583 // // receive an update request, but the counter in the4584 // // update table must be decremented by the MULTI_ACK FSM.4585 //4586 // if(!r_write_to_multi_ack_req.read())4587 // {4588 // r_write_to_multi_ack_req = true;4589 // r_write_to_multi_ack_upt_index = r_write_upt_index.read();4590 // r_write_fsm = WRITE_IDLE;4591 // }4592 // break;4593 // }4594 //4595 4304 /////////////// 4596 4305 case WRITE_RSP: … … 4678 4387 break; 4679 4388 } 4680 // case WRITE_MISS_IVT_LOCK:4681 // {4682 // if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)4683 // {4684 // size_t index;4685 // if(m_ivt.search_inval(m_nline[(addr_t)(r_write_address.read())], index))4686 // {4687 // r_write_fsm = WRITE_WAIT;4688 // }4689 // else4690 // {4691 // r_write_fsm = WRITE_MISS_TRT_LOCK;4692 // }4693 // }4694 // break;4695 // }4696 //4697 4389 ///////////////////////// 4698 4390 case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table … … 4845 4537 break; 4846 4538 } 4847 4848 // ///////////////////////4849 // case WRITE_INVAL_DIR_READ: // enter this state if a broadcast-inval is required4850 // // the cache line must be erased in mem-cache, and written4851 // // into XRAM.4852 // {4853 // assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and4854 // "MEMC ERROR in WRITE_INVAL_DIR_READ state: Bad DIR allocation");4855 //4856 // // write enable signal for data buffer.4857 // r_write_bc_data_we = true;4858 //4859 // r_write_fsm = WRITE_INVAL_TRT_LOCK;4860 //4861 //#if DEBUG_MEMC_WRITE4862 // if (m_debug)4863 // std::cout << " <MEMC " << name() << " WRITE_INVAL_DIR_READ>"4864 // << " Read the cache to complete local buffer" << std::endl;4865 //#endif4866 // break;4867 // }4868 ///////////////////////4869 case WRITE_INVAL_TRT_LOCK: // get TRT lock to check TRT not full4870 {4871 assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and4872 "MEMC ERROR in WRITE_INVAL_TRT_LOCK state: Bad DIR allocation");4873 4874 if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE)4875 break;4876 4877 // We read the cache and complete the buffer. As the DATA cache uses a4878 // synchronous RAM, the read DATA request has been performed in the4879 // WRITE_INVAL_DIR_READ state but the data is available in this state.4880 size_t wok_index = 0;4881 bool wok = not m_trt.full(wok_index);4882 if(wok) // set a new entry in TRT4883 {4884 r_write_trt_index = wok_index;4885 r_write_fsm = WRITE_INVAL_IVT_LOCK;4886 }4887 else // wait an empty entry in TRT4888 {4889 r_write_fsm = WRITE_WAIT;4890 }4891 4892 #if DEBUG_MEMC_WRITE4893 if(m_debug)4894 std::cout << " <MEMC " << name()4895 << " WRITE_INVAL_TRT_LOCK> Check TRT : wok = " << wok4896 << " / index = " << wok_index << std::endl;4897 #endif4898 4899 m_cpt_write_fsm_trt_lock++;4900 4901 break;4902 }4903 4904 4539 ////////////////////// 4905 4540 case WRITE_INVAL_IVT_LOCK: // register BC transaction in IVT … … 4955 4590 << " / nb_copies = " << r_write_count.read() << std::endl; 4956 4591 #endif 4957 // for(size_t word=0 ; word<m_words ; word++)4958 // {4959 // r_write_to_cleanup_be[word] = r_write_be[word];4960 // r_write_to_cleanup_data[word] = r_write_data[word];4961 4962 // data_t mask = 0;4963 // if(r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;4964 // if(r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;4965 // if(r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;4966 // if(r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;4967 4968 // // complete only if mask is not null (for energy consumption)4969 // r_write_data[word] =4970 // (r_write_data[word].read() & mask) |4971 // (m_cache_data.read(r_write_way.read(), set, word) & ~mask);4972 ///*// std::cout << std::hex4973 // << ((r_write_data[word].read() & mask) |4974 // (m_cache_data.read(r_write_way.read(), set, word) & ~mask)) << std::endl;*/4975 // }4976 4977 4592 DirectoryEntry entry; 4978 4593 entry.state = ENTRY_LOCKED; … … 5016 4631 break; 5017 4632 } 5018 5019 ////////////////////////5020 case WRITE_DIR_INVAL:5021 {5022 assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and5023 "MEMC ERROR in WRITE_DIR_INVAL state: Bad DIR allocation");5024 5025 // assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and5026 // "MEMC ERROR in WRITE_DIR_INVAL state: Bad TRT allocation");5027 5028 assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and5029 "MEMC ERROR in WRITE_DIR_INVAL state: Bad IVT allocation");5030 5031 // register PUT request in TRT5032 // std::vector<data_t> data_vector;5033 // data_vector.clear();5034 // for(size_t i=0; i<m_words; i++) data_vector.push_back(r_write_data[i].read());5035 5036 // m_trt.set( r_write_trt_index.read(),5037 // false, // PUT request5038 // m_nline[(addr_t)(r_write_address.read())],5039 // 0, // unused5040 // 0, // unused5041 // 0, // unused5042 // false, // not a processor read5043 // 0, // unused5044 // 0, // unused5045 // std::vector<be_t> (m_words,0),5046 // data_vector );5047 5048 // invalidate directory entry5049 DirectoryEntry entry;5050 entry.state = ENTRY_LOCKED;5051 entry.dirty = true;5052 entry.tag = r_write_tag.read();5053 entry.is_cnt = 0;5054 entry.lock = false;5055 entry.owner.srcid = 0;5056 entry.owner.inst = false;5057 entry.ptr = 0;5058 entry.count = 0;5059 size_t set = m_y[(addr_t)(r_write_address.read())];5060 size_t way = r_write_way.read();5061 5062 m_cache_directory.write(set, way, entry);5063 5064 if ((r_write_pktid.read() & 0x7) == TYPE_SC)5065 {5066 m_llsc_table.sc(r_write_address.read(),5067 r_write_sc_key.read());5068 }5069 5070 #if DEBUG_MEMC_WRITE5071 if(m_debug)5072 std::cout << " <MEMC " << name() << " WRITE_DIR_INVAL> Invalidate the directory entry: @ = "5073 << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;5074 #endif5075 r_write_fsm = WRITE_INVAL_CC_SEND;5076 break;5077 }5078 5079 4633 ////////////////////// 5080 4634 case WRITE_INVAL_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM … … 5084 4638 { 5085 4639 bool last_multi_inval = (r_write_count.read() == 1) and not r_write_is_cnt.read(); 5086 bool not_last_multi_inval = (r_write_count.read() != 1) and not r_write_is_cnt.read();5087 4640 bool multi_inval = not r_write_is_cnt.read(); 5088 4641 … … 5107 4660 else 5108 4661 { 5109 // if(r_write_inval_trt_send.read()) 5110 // { 5111 // r_write_fsm = WRITE_INVAL_XRAM_REQ; 5112 // } 5113 // else //the line is in exlusive state, must wait for the 5114 // //response of multi_inval in reason of receiving the updated data 5115 // { 5116 r_write_fsm = WRITE_IDLE; 5117 5118 // } 4662 r_write_fsm = WRITE_IDLE; 5119 4663 } 5120 4664 #if DEBUG_MEMC_WRITE … … 5127 4671 { 5128 4672 assert( false && "CC SEND FLAGS IS TURE in WRITE_INVAL_CC_SEND state"); 5129 }5130 break;5131 }5132 5133 ///////////////////////5134 case WRITE_INVAL_XRAM_REQ: // Post a put request to IXR_CMD FSM5135 {5136 if( not r_write_to_ixr_cmd_req.read() )5137 {5138 if((r_write_state.read() == ENTRY_EXCLUSIVE) and (r_write_count.read() == 1))5139 {5140 std::cout << "can't send a trt req when the line state is exlusive"<< std::endl;5141 exit(0);5142 }5143 5144 r_write_to_ixr_cmd_req = true;5145 r_write_to_ixr_cmd_index = r_write_trt_index.read();5146 r_write_fsm = WRITE_IDLE;5147 5148 #if DEBUG_MEMC_WRITE5149 if(m_debug)5150 std::cout << " <MEMC " << name()5151 << " WRITE_INVAL_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;5152 #endif5153 4673 } 5154 4674 break; … … 5755 5275 5756 5276 // selects & extracts a victim line from cache 5757 size_t way = 0;5277 int way = 0; 5758 5278 size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)]; 5759 5279 5760 5280 DirectoryEntry victim(m_cache_directory.select(set, way)); 5281 5282 if( way == -1) 5283 { 5284 #if DEBUG_MEMC_XRAM_RSP 5285 if(m_debug) 5286 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 5287 << " not a disponible victim" 5288 << std::endl; 5289 #endif 5290 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 5291 break; 5292 } 5761 5293 5762 5294 bool inval = (victim.count != 0) and (victim.state != ENTRY_INVALID) ; … … 5782 5314 else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; 5783 5315 5784 if( way == -1) r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;5785 5786 5316 #if DEBUG_MEMC_XRAM_RSP 5787 5317 if(m_debug) … … 6435 5965 (r_write_to_cleanup_data[r_cleanup_data_index.read()].read() & mask) | 6436 5966 (data & ~mask); 6437 6438 int data_out = (r_write_to_cleanup_data[r_cleanup_data_index.read()].read() & mask) |6439 (data & ~mask);6440 6441 /*// std::cout << "receive write nline " << std::hex << r_cleanup_nline.read()6442 << "word " << r_cleanup_data_index.read()6443 << "data "6444 << data_out << std::endl;*/6445 6446 5967 } 6447 5968 else … … 6504 6025 exit(0); 6505 6026 } 6506 //std::cout << " MEM_CACHE : CLEANUP_DIR_LOCK" << std::endl;6507 6508 6027 // Read the directory 6509 6028 size_t way = 0; … … 6521 6040 r_cleanup_copy_inst = entry.owner.inst; 6522 6041 r_cleanup_state = entry.state; 6523 6524 //size_t set = m_y[(addr_t)(cleanup_address)];6525 //m_cache_data.read_line(way, set, r_cleanup_old_data);6526 6042 6527 6043 if(entry.state == ENTRY_LOCKED) … … 6627 6143 if( entry.count == 0) 6628 6144 { 6629 //entry.state = ENTRY_EXCLUSIVE; 6630 entry.is_cnt = 0; 6145 entry.is_cnt = 0; 6631 6146 } 6632 6147 else 6633 6148 { 6634 //entry.state = ENTRY_SHARED; 6635 entry.is_cnt = r_cleanup_is_cnt.read(); 6149 entry.is_cnt = r_cleanup_is_cnt.read(); 6636 6150 } 6637 6151 … … 6642 6156 m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF); 6643 6157 } 6644 addr_t min = r_cleanup_nline.read()*m_words*4 ;6645 addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;6646 m_llsc_table.sw(min, max);6158 // addr_t min = r_cleanup_nline.read()*m_words*4 ; 6159 // addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; 6160 // m_llsc_table.sw(min, max); 6647 6161 } 6648 6162 … … 6757 6271 6758 6272 addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; 6759 //size_t match_cas_multi_inval = r_cas_to_cleanup_req.read() and6760 // (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read());6761 6762 //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS;6763 //size_t match_sc_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_SC;6764 6273 6765 6274 bool match_ll = ((r_cleanup_locked_pktid.read() & 0x07) == TYPE_LL); … … 6781 6290 m_cache_data.write(way, set, word, r_write_to_cleanup_data[word].read(), r_write_to_cleanup_be[word].read()); 6782 6291 } 6783 //addr_t min = r_cleanup_nline.read()*m_words*4 ;6784 //addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;6785 //m_llsc_table.sw(min, max);6786 6292 } 6787 6293 … … 6798 6304 if((r_cleanup_locked_pktid.read() & 0x7) != TYPE_SC) 6799 6305 { 6800 addr_t min = r_cleanup_nline.read()*m_words*4 ;6801 addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;6802 m_llsc_table.sw(min, max);6306 // addr_t min = r_cleanup_nline.read()*m_words*4 ; 6307 // addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; 6308 // m_llsc_table.sw(min, max); 6803 6309 } 6804 6310 } … … 6841 6347 else // cas, getm, one copy updated in dir 6842 6348 { 6843 // if(match_cas_inval or match_sc_inval)6844 // {6845 // entry.state = ENTRY_SHARED;6846 // entry.count = 0;6847 // }6848 6349 if(r_cleanup_locked_is_read.read()) 6849 6350 { … … 6884 6385 { 6885 6386 if(r_cleanup_to_tgt_rsp_req.read()) break; 6886 6887 //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS;6888 6387 6889 6388 r_cleanup_to_tgt_rsp_req = true; … … 7362 6861 r_cleanup_to_ixr_cmd_req = true; 7363 6862 7364 // if( (r_write_to_cleanup_req == true) and (r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) )7365 // {7366 // r_write_to_cleanup_req = false;7367 // }7368 7369 6863 if (r_cleanup_contains_data.read()) 7370 6864 { … … 7389 6883 data_vector); 7390 6884 7391 addr_t min = r_cleanup_nline.read()*m_words*4 ;7392 addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4;7393 m_llsc_table.sw(min, max);6885 // addr_t min = r_cleanup_nline.read()*m_words*4 ; 6886 // addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; 6887 // m_llsc_table.sw(min, max); 7394 6888 } 7395 //std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl; 7396 //r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); 7397 r_cleanup_to_ixr_cmd_index = index; 7398 //r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); 7399 //r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); 7400 //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); 7401 r_cleanup_fsm = CLEANUP_SEND_CLACK; 6889 r_cleanup_to_ixr_cmd_index = index; 6890 r_cleanup_fsm = CLEANUP_SEND_CLACK; 7402 6891 #if DEBUG_MEMC_CLEANUP 7403 6892 if(m_debug) … … 7693 7182 7694 7183 } 7695 // else if(r_cas_is_cnt.read() and r_cas_state.read() == ENTRY_SHARED)7696 // {7697 // r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required7698 //#if DEBUG_MEMC_CAS7699 // if(m_debug)7700 // std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>"7701 // << " Broacast Inval required"7702 // << " / copies = " << r_cas_count.read() << std::endl;7703 //#endif7704 //7705 // }7706 7184 else 7707 7185 { … … 7714 7192 #endif 7715 7193 } 7716 // else7717 // {7718 // r_cas_fsm = CAS_WAIT;7719 //#if DEBUG_MEMC_CAS7720 // if(m_debug)7721 // std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>"7722 // << " CC_SEND FSM busy: release all locks and retry" << std::endl;7723 //#endif7724 // }7725 7194 } 7726 7195 else // no copies or multi_inval finished … … 7766 7235 size_t pktid = m_cmd_cas_pktid_fifo.read(); 7767 7236 addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 7768 size_t nb_copies_sent = 0; 7769 7770 // if(r_cas_state.read() == ENTRY_EXCLUSIVE) 7771 // { 7772 // nb_copies_sent = 1; 7773 // } 7774 // else 7775 // { 7776 nb_copies_sent = r_cas_count.read(); 7777 // } 7778 // if(m_ivt.search_inval(nline, index) and r_cas_to_cleanup_req.read()) 7779 // { 7780 //#if DEBUG_MEMC_CAS 7781 // if(m_debug) 7782 // std::cout << " <MEMC " << name() 7783 // << " CAS_MULTI_INVAL_IVT_LOCK> pending ivt " 7784 // << std::endl; 7785 //#endif 7786 // r_cas_fsm = CAS_WAIT; 7787 // break; 7788 // } 7237 7789 7238 wok = m_ivt.set(false, // it's an invalid transaction 7790 7239 false, // it's not a broadcast … … 7795 7244 pktid, 7796 7245 nline, 7797 nb_copies_sent,7246 r_cas_count.read(), 7798 7247 false, // is a command write 7799 7248 index); … … 7862 7311 << " / way = " << way 7863 7312 << " / nline = " << std::hex << nline 7864 << " / count = " << nb_copies_sent<< std::endl;7313 << " / count = " << r_cas_count.read() << std::endl; 7865 7314 #endif 7866 7315 } … … 7914 7363 "VCI_MEM_CACHE ERROR : bad HEAP allocation"); 7915 7364 7916 bool match_srcid = r_cas_copy.read() == m_cmd_cas_srcid_fifo.read();7917 7918 7365 assert(not r_cas_copy_inst.read() && "cas fsm: cas has a copy inst"); 7919 7366 … … 7922 7369 r_cas_next_ptr = r_cas_ptr.read(); 7923 7370 r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 7924 //r_cas_to_cc_send_trdid = r_cas_ivt_index.read();7925 //r_cas_to_cc_send_index = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];7926 //r_cas_to_cc_send_wdata = r_cas_wdata.read();7927 7371 7928 7372 cas_to_cc_send_fifo_put = true; … … 7963 7407 7964 7408 HeapEntry entry = m_heap.read(r_cas_next_ptr.read()); 7965 7966 bool match_srcid = (entry.owner.srcid == m_cmd_cas_srcid_fifo.read());7967 7968 addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];7969 7409 7970 7410 assert(not entry.owner.inst && "cas fsm: cas has a copy inst"); … … 7978 7418 if(entry.next == r_cas_next_ptr.read()) // last copy 7979 7419 { 7980 //r_cas_to_cleanup_nline = nline;7981 7420 r_cas_to_cc_send_multi_req = true; 7982 //r_cas_to_cleanup_req = true;7983 7421 r_cas_fsm = CAS_HEAP_LAST; // Response will be sent after receiving 7984 7422 } … … 7991 7429 << " / wdata = " << std::hex << r_cas_wdata.read() 7992 7430 << " / srcid = " << std::dec << entry.owner.srcid 7993 << " / match srcid = " << match_srcid7994 7431 << " / inst = " << std::dec << entry.owner.inst << std::endl; 7995 7432 } … … 8007 7444 } 8008 7445 size_t free_pointer = m_heap.next_free_ptr(); 8009 8010 addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];8011 7446 8012 7447 HeapEntry last_entry; … … 8200 7635 r_cas_to_cc_send_multi_req = false; 8201 7636 r_cas_to_cc_send_brdcast_req = true; 8202 //r_cas_to_cc_send_trdid = r_cas_ivt_index.read();8203 7637 r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 8204 //r_cas_to_cc_send_index = 0;8205 //r_cas_to_cc_send_wdata = 0;8206 7638 8207 7639 r_cas_fsm = CAS_BC_XRAM_REQ; … … 8449 7881 8450 7882 // WRITE 8451 // if(r_write_to_cc_send_req.read())8452 // {8453 // r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;8454 // break;8455 // }8456 8457 7883 if(m_write_to_cc_send_inst_fifo.rok() or 8458 7884 r_write_to_cc_send_multi_req.read()) … … 8533 7959 } 8534 7960 // WRITE 8535 // if(r_write_to_cc_send_req.read())8536 // {8537 // r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;8538 // break;8539 // }8540 7961 if(m_write_to_cc_send_inst_fifo.rok() or 8541 7962 r_write_to_cc_send_multi_req.read()) … … 8756 8177 case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) 8757 8178 { 8758 8759 8179 if(m_config_to_cc_send_inst_fifo.rok()) 8760 8180 { … … 8939 8359 break; 8940 8360 } 8941 // case CC_SEND_WRITE_INVAL_HEADER:8942 // {8943 // if(not p_dspin_m2p.read) break;8944 //8945 // r_cc_send_fsm = CC_SEND_WRITE_INVAL_NLINE;8946 // break;8947 // }8948 //8949 // case CC_SEND_WRITE_INVAL_NLINE:8950 // {8951 // if(not p_dspin_m2p.read) break;8952 //8953 // r_write_to_cc_send_req = false;8954 // r_cc_send_fsm = CC_SEND_WRITE_IDLE;8955 //8956 //#if DEBUG_MEMC_CC_SEND8957 // if(m_debug)8958 // {8959 // std::cout8960 // << " <MEMC " << name()8961 // << " CC_SEND_WRITE_INVAL_HEADER> Inval for line "8962 // << r_write_to_cc_send_nline.read()8963 // << std::endl;8964 // }8965 //#endif8966 // break;8967 // }8968 //8969 8970 8361 ////////////////////////////////// 8971 8362 case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) … … 9001 8392 { 9002 8393 if(not p_dspin_m2p.read) break; 9003 // // <Activity Counters>9004 // if (is_local_req(m_write_to_cc_send_srcid_fifo.read()))9005 // {9006 // m_cpt_update_local++;9007 // }9008 // else9009 // {9010 // m_cpt_update_remote++;9011 // m_cpt_update_cost += req_distance(m_write_to_cc_send_srcid_fifo.read());9012 // }9013 // // </Activity Counters>9014 9015 8394 r_cc_send_fsm = CC_SEND_WRITE_INVAL_NLINE; 9016 8395 break; … … 9043 8422 break; 9044 8423 } 9045 /////////////////////////////9046 // case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM)9047 // {9048 // if(not p_dspin_m2p.read) break;9049 // if(r_cc_send_cpt.read() == r_write_to_cc_send_count.read())9050 // {9051 // write_to_cc_send_fifo_get = true;9052 // r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;9053 // break;9054 // }9055 //9056 // r_cc_send_cpt = r_cc_send_cpt.read() + 1;9057 // break;9058 // }9059 8424 //////////////////////////////// 9060 8425 case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) … … 9089 8454 { 9090 8455 if(not p_dspin_m2p.read) break; 9091 // <Activity Counters>9092 // if (is_local_req(m_cas_to_cc_send_srcid_fifo.read()))9093 // {9094 // m_cpt_update_local++;9095 // }9096 // else9097 // {9098 // m_cpt_update_remote++;9099 // m_cpt_update_cost += req_distance(m_cas_to_cc_send_srcid_fifo.read());9100 // }9101 // // </Activity Counters>9102 8456 r_cc_send_fsm = CC_SEND_CAS_INVAL_NLINE; 9103 8457 break; … … 9110 8464 } 9111 8465 9112 // <Activity Counters>9113 // m_cpt_update++;9114 // </Activity Counters>9115 8466 r_cc_send_fsm = CC_SEND_CAS_IDLE; 9116 8467 break; … … 9131 8482 break; 9132 8483 } 9133 ///////////////////////////9134 // case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM)9135 // {9136 // if(not p_dspin_m2p.read) break;9137 //9138 // if(r_cas_to_cc_send_is_long.read())9139 // {9140 // r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH;9141 // break;9142 // }9143 //9144 // cas_to_cc_send_fifo_get = true;9145 // r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;9146 // break;9147 // }9148 ////////////////////////////////9149 // case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM)9150 // {9151 // if(not p_dspin_m2p.read) break;9152 // cas_to_cc_send_fifo_get = true;9153 // r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;9154 // break;9155 // }9156 8484 } 9157 8485 // end switch r_cc_send_fsm … … 9857 9185 } 9858 9186 } // end switch tgt_rsp_fsm 9859 9860 ////////////////////////////////////////////////////////////////////////////////////9861 // ALLOC_UPT FSM9862 ////////////////////////////////////////////////////////////////////////////////////9863 // The ALLOC_UPT FSM allocates the access to the Update Table (UPT),9864 // with a round robin priority between three FSMs, with the following order:9865 // WRITE -> CAS -> MULTI_ACK9866 // - The WRITE FSM initiates update transaction and sets a new entry in UPT.9867 // - The CAS FSM does the same thing as the WRITE FSM.9868 // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry.9869 // The resource is always allocated.9870 /////////////////////////////////////////////////////////////////////////////////////9871 // switch(r_alloc_upt_fsm.read())9872 // {9873 // /////////////////////////9874 // case ALLOC_UPT_WRITE: // allocated to WRITE FSM9875 // if (r_write_fsm.read() != WRITE_UPT_LOCK)9876 // {9877 // if (r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK)9878 // r_alloc_upt_fsm = ALLOC_UPT_CAS;9879 //9880 // else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)9881 // r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;9882 // else9883 // m_cpt_upt_unused++;9884 // }9885 // break;9886 //9887 // /////////////////////////9888 // case ALLOC_UPT_CAS: // allocated to CAS FSM9889 // if (r_cas_fsm.read() != CAS_MULTI_INVAL_IVT_LOCK)9890 // {9891 // if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK)9892 // r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK;9893 //9894 // else if (r_write_fsm.read() == WRITE_UPT_LOCK)9895 // r_alloc_upt_fsm = ALLOC_UPT_WRITE;9896 //9897 // else9898 // m_cpt_upt_unused++;9899 // }9900 // break;9901 //9902 // /////////////////////////9903 // case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM9904 // if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and9905 // (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR))9906 // {9907 // if (r_write_fsm.read() == WRITE_UPT_LOCK)9908 // r_alloc_upt_fsm = ALLOC_UPT_WRITE;9909 //9910 // else if (r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK)9911 // r_alloc_upt_fsm = ALLOC_UPT_CAS;9912 // else9913 // m_cpt_upt_unused++;9914 // }9915 // break;9916 // } // end switch r_alloc_upt_fsm9917 //9918 9187 //////////////////////////////////////////////////////////////////////////////////// 9919 9188 // ALLOC_IVT FSM … … 10253 9522 (r_write_fsm.read() != WRITE_HEAP_REQ) and 10254 9523 (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 10255 (r_write_fsm.read() != WRITE_INVAL_TRT_LOCK) and10256 9524 (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) 10257 9525 or … … 10449 9717 if(r_read_fsm.read() != READ_TRT_LOCK) 10450 9718 { 10451 if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 10452 (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) 9719 if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10453 9720 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10454 9721 … … 10489 9756 case ALLOC_TRT_WRITE: 10490 9757 if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 10491 (r_write_fsm.read() != WRITE_INVAL_TRT_LOCK) and 10492 (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) 9758 (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) 10493 9759 { 10494 9760 if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or … … 10559 9825 r_alloc_trt_fsm = ALLOC_TRT_READ; 10560 9826 10561 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 10562 (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) 9827 else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10563 9828 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10564 9829 … … 10595 9860 r_alloc_trt_fsm = ALLOC_TRT_READ; 10596 9861 10597 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 10598 (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) 9862 else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10599 9863 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10600 9864 … … 10626 9890 r_alloc_trt_fsm = ALLOC_TRT_READ; 10627 9891 10628 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 10629 (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) 9892 else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10630 9893 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10631 9894 … … 10663 9926 r_alloc_trt_fsm = ALLOC_TRT_READ; 10664 9927 10665 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || 10666 (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) 9928 else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10667 9929 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10668 9930 … … 10701 9963 r_alloc_trt_fsm = ALLOC_TRT_READ; 10702 9964 10703 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 10704 (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) 9965 else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10705 9966 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10706 9967 … … 10734 9995 r_alloc_trt_fsm = ALLOC_TRT_READ; 10735 9996 10736 else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or 10737 (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) 9997 else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10738 9998 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10739 9999 … … 11696 10956 DspinDhccpParam::BROADCAST_SRCID); 11697 10957 11698 // DspinDhccpParam::dspin_set( flit,11699 // r_read_to_cc_send_is_shared.read(), // send the actuel line state in memcache11700 // DspinDhccpParam::BRDCAST_IS_SHARED);11701 11702 10958 DspinDhccpParam::dspin_set( flit, 11703 10959 1ULL, … … 11819 11075 } 11820 11076 11821 // case CC_SEND_WRITE_INVAL_HEADER:11822 // {11823 // uint64_t flit = 0;11824 //11825 // DspinDhccpParam::dspin_set(11826 // flit,11827 // r_write_to_cc_send_dest.read(),11828 // DspinDhccpParam::MULTI_INVAL_DEST);11829 //11830 // DspinDhccpParam::dspin_set(11831 // flit,11832 // m_cc_global_id,11833 // DspinDhccpParam::MULTI_INVAL_SRCID);11834 //11835 // DspinDhccpParam::dspin_set(11836 // flit,11837 // DspinDhccpParam::TYPE_MULTI_INVAL_DATA,11838 // DspinDhccpParam::M2P_TYPE);11839 //11840 // p_dspin_m2p.write = true;11841 // p_dspin_m2p.data = flit;11842 //11843 // break;11844 //11845 // }11846 //11847 // case CC_SEND_WRITE_NCC_INVAL_NLINE:11848 // {11849 // uint64_t flit = 0;11850 //11851 // DspinDhccpParam::dspin_set(11852 // flit,11853 // r_write_to_cc_send_nline.read(),11854 // DspinDhccpParam::MULTI_INVAL_NLINE);11855 //11856 //11857 // p_dspin_m2p.write = true;11858 // p_dspin_m2p.data = flit;11859 // p_dspin_m2p.eop = true;11860 //11861 // break;11862 //11863 // }11864 //11865 //11866 11077 case CC_SEND_WRITE_BRDCAST_NLINE: 11867 11078 { … … 11932 11143 uint64_t flit = 0; 11933 11144 11934 // DspinDhccpParam::dspin_set(11935 // flit,11936 // r_write_to_cc_send_index.read(),11937 // DspinDhccpParam::MULTI_UPDT_WORD_INDEX);11938 11939 11145 DspinDhccpParam::dspin_set( 11940 11146 flit, … … 11949 11155 break; 11950 11156 } 11951 // /////////////////////////////11952 // case CC_SEND_WRITE_UPDT_DATA:11953 // {11954 //11955 // uint8_t multi_updt_cpt =11956 // r_cc_send_cpt.read() + r_write_to_cc_send_index.read();11957 //11958 // uint8_t multi_updt_be = r_write_to_cleanup_be[multi_updt_cpt].read();11959 // uint32_t multi_updt_data = r_write_to_cleanup_data[multi_updt_cpt].read();11960 //11961 // uint64_t flit = 0;11962 //11963 // DspinDhccpParam::dspin_set(11964 // flit,11965 // multi_updt_be,11966 // DspinDhccpParam::MULTI_UPDT_BE);11967 //11968 // DspinDhccpParam::dspin_set(11969 // flit,11970 // multi_updt_data,11971 // DspinDhccpParam::MULTI_UPDT_DATA);11972 //11973 // p_dspin_m2p.write = true;11974 // p_dspin_m2p.eop = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read());11975 // p_dspin_m2p.data = flit;11976 //11977 // break;11978 // }11979 11157 //////////////////////////// 11980 11158 case CC_SEND_CAS_INVAL_HEADER: … … 12022 11200 uint64_t flit = 0; 12023 11201 12024 // DspinDhccpParam::dspin_set(12025 // flit,12026 // r_cas_to_cc_send_index.read(),12027 // DspinDhccpParam::MULTI_UPDT_WORD_INDEX);12028 12029 11202 DspinDhccpParam::dspin_set( 12030 11203 flit, … … 12038 11211 break; 12039 11212 } 12040 ///////////////////////////12041 // case CC_SEND_CAS_UPDT_DATA:12042 // {12043 // uint64_t flit = 0;12044 //12045 // DspinDhccpParam::dspin_set(12046 // flit,12047 // 0xF,12048 // DspinDhccpParam::MULTI_UPDT_BE);12049 //12050 // DspinDhccpParam::dspin_set(12051 // flit,12052 // r_cas_to_cc_send_wdata.read(),12053 // DspinDhccpParam::MULTI_UPDT_DATA);12054 //12055 // p_dspin_m2p.write = true;12056 // p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read();12057 // p_dspin_m2p.data = flit;12058 //12059 // break;12060 // }12061 // ////////////////////////////////12062 // case CC_SEND_CAS_UPDT_DATA_HIGH:12063 // {12064 // uint64_t flit = 0;12065 //12066 // DspinDhccpParam::dspin_set(12067 // flit,12068 // 0xF,12069 // DspinDhccpParam::MULTI_UPDT_BE);12070 //12071 // DspinDhccpParam::dspin_set(12072 // flit,12073 // r_cas_to_cc_send_wdata_high.read(),12074 // DspinDhccpParam::MULTI_UPDT_DATA);12075 //12076 // p_dspin_m2p.write = true;12077 // p_dspin_m2p.eop = true;12078 // p_dspin_m2p.data = flit;12079 //12080 // break;12081 // }12082 11213 } 12083 11214
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