- Timestamp:
- May 13, 2014, 12:06:31 PM (11 years ago)
- File:
-
- 1 edited
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branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r675 r686 371 371 sc_signal<paddr_t> r_icache_vci_paddr; // physical address 372 372 sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor 373 373 sc_signal<bool> r_icache_read_state; 374 374 // icache miss handling 375 375 sc_signal<size_t> r_icache_miss_way; // selected way for cache update … … 420 420 sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op 421 421 // registers written in P0 stage (used in P1 stage) 422 sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage 423 sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage 422 sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) 424 423 sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) 425 sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc)426 424 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 427 425 sc_signal<paddr_t> r_dcache_save_paddr; // physical address … … 549 547 sc_signal<bool> r_dcache_updt_data_req; 550 548 sc_signal<bool> r_dcache_updt_dir_req; 551 sc_signal<bool> r_dcache_rsp_state;552 549 sc_signal<bool> r_dcache_cas_islocal; // cas is done locally 553 550 … … 561 558 562 559 //MESI 563 sc_signal<bool> r_icache_read_state;564 560 sc_signal<bool> r_dcache_read_state; 565 561 sc_signal<bool> r_dcache_read_for_modify; // a command intent to write 566 sc_signal<bool> r_dcache_r ead_hit; // a command intent to write hit in L1562 sc_signal<bool> r_dcache_rsp_state; 567 563 568 564 ///////////////////////////////////
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