Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 682) +++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 686) @@ -371,5 +371,5 @@ sc_signal r_icache_vci_paddr; // physical address sc_signal r_icache_vaddr_save; // virtual address from processor - + sc_signal r_icache_read_state; // icache miss handling sc_signal r_icache_miss_way; // selected way for cache update @@ -420,8 +420,6 @@ sc_signal r_dcache_fsm_scan_save; // return state for tlb scan op // registers written in P0 stage (used in P1 stage) - sc_signal r_dcache_wbuf_req; // WBUF must be written in P1 stage - sc_signal r_dcache_updt_req; // DCACHE must be updated in P1 stage + sc_signal r_dcache_save_wdata; // write data (from proc) sc_signal r_dcache_save_vaddr; // virtual address (from proc) - sc_signal r_dcache_save_wdata; // write data (from proc) sc_signal r_dcache_save_be; // byte enable (from proc) sc_signal r_dcache_save_paddr; // physical address @@ -549,5 +547,4 @@ sc_signal r_dcache_updt_data_req; sc_signal r_dcache_updt_dir_req; - sc_signal r_dcache_rsp_state; sc_signal r_dcache_cas_islocal; // cas is done locally @@ -561,8 +558,7 @@ //MESI - sc_signal r_icache_read_state; sc_signal r_dcache_read_state; sc_signal r_dcache_read_for_modify; // a command intent to write - sc_signal r_dcache_read_hit; // a command intent to write hit in L1 + sc_signal r_dcache_rsp_state; /////////////////////////////////// Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 682) +++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 686) @@ -270,4 +270,5 @@ r_icache_vci_paddr("r_icache_vci_paddr"), r_icache_vaddr_save("r_icache_vaddr_save"), + r_icache_read_state("r_icache_read_state"), r_icache_miss_way("r_icache_miss_way"), @@ -304,9 +305,7 @@ r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), - r_dcache_wbuf_req("r_dcache_wbuf_req"), - r_dcache_updt_data_req("r_dcache_updt_data_req"), - r_dcache_updt_dir_req("r_dcache_updt_dir_req"), + r_dcache_save_wdata("r_dcache_save_wdata"), + r_dcache_save_vaddr("r_dcache_save_vaddr"), - r_dcache_save_wdata("r_dcache_save_wdata"), r_dcache_save_be("r_dcache_save_be"), r_dcache_save_paddr("r_dcache_save_paddr"), @@ -332,4 +331,6 @@ r_dcache_vci_sc_data("r_dcache_vci_sc_data"), + + r_dcache_xtn_way("r_dcache_xtn_way"), r_dcache_xtn_set("r_dcache_xtn_set"), @@ -354,7 +355,4 @@ r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), -// r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), -// r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), -// r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), r_dcache_tlb_way("r_dcache_tlb_way"), r_dcache_tlb_set("r_dcache_tlb_set"), @@ -374,4 +372,8 @@ r_dcache_cc_send_way("r_dcache_cc_send_way"), r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"), + r_dcache_updt_data_req("r_dcache_updt_data_req"), + r_dcache_updt_dir_req("r_dcache_updt_dir_req"), + r_dcache_read_for_modify("r_dcache_read_for_modify"), + r_dcache_rsp_state("r_dcache_rsp_state"), r_vci_cmd_fsm("r_vci_cmd_fsm"), @@ -387,5 +389,4 @@ r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 16), // 2 words depth -// r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth r_cc_send_data_fifo("r_cc_send_data_fifo", 2), @@ -409,8 +410,7 @@ r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"), r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"), + + r_cc_receive_dcache_srcid("r_cc_receive_dcache_srcid"), - - r_icache_read_state("r_icache_read_state"), - r_dcache_rsp_state("r_dcache_rsp_state"), r_iss(this->name(), proc_id), @@ -519,5 +519,4 @@ << " | MMU = " << r_mmu_mode.read(); if (r_dcache_updt_data_req.read() ) std::cout << " | P1_UPDT"; - if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; std::cout << std::endl; @@ -814,7 +813,4 @@ r_icache_clack_req = false; - // No pending write in pipeline - r_dcache_wbuf_req = false; - // No request from DCACHE_FSM to CMD_FSM r_dcache_vci_miss_req = false; @@ -1010,7 +1006,4 @@ bool vci_rsp_fifo_dcache_put = false; uint32_t vci_rsp_fifo_dcache_data = 0; - bool vci_rsp_fifo_rpktid_get = false; - bool vci_rsp_fifo_rpktid_put = false; - bool vci_rsp_fifo_rpktid = false; // FIFO for cleanup data updt @@ -1018,11 +1011,4 @@ bool cleanup_data_updt_fifo_dcache_put = false; uint32_t cleanup_data_updt_fifo_dcache_data = 0; - - // updt fifo - bool cc_receive_updt_fifo_get = false; - bool cc_receive_updt_fifo_put = false; - uint32_t cc_receive_updt_fifo_be = 0; - uint32_t cc_receive_updt_fifo_data = 0; - bool cc_receive_updt_fifo_eop = false; #ifdef INSTRUMENTATION @@ -2283,9 +2269,6 @@ bool tlb_inval_required = false; // request TLB inval after cache update - bool wbuf_write_miss = false; // miss a WBUF write request bool updt_data_request = false; // request DCACHE update in P1 stage bool updt_dir_request = false; // request DCACHE update in P1 stage - bool wbuf_request = false; // request WBUF write in P1 stage - // physical address computation : systematic DTLB access (if activated) @@ -2293,11 +2276,11 @@ { -//#if 1 -// // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE -// if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { -// std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; -// raise(SIGINT); -// } -//#endif +#if 0 + // @@@ DO NOT COMMIT: ALMOS KILLING SIMU PURPOSE + if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) { + std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl; + raise(SIGINT); + } +#endif if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated @@ -2938,5 +2921,4 @@ r_dcache_vci_miss_req = true; r_dcache_read_for_modify = true; - r_dcache_read_hit = true; r_dcache_miss_type = PROC_MISS; r_dcache_fsm = DCACHE_MISS_WAIT; @@ -2965,5 +2947,4 @@ r_dcache_fsm = DCACHE_MISS_SELECT; r_dcache_read_for_modify = true; - r_dcache_read_hit = false; } else @@ -3727,4 +3708,7 @@ } #endif + // checking llsc reservation buffer + if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) + r_dcache_llsc_valid = false; if (r_cas_cache_state.read() == CACHE_SLOT_STATE_EXCLUSIVE or @@ -3776,9 +3760,4 @@ // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); - - // checking llsc reservation buffer - if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) - r_dcache_llsc_valid = false; - // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state r_dcache_vci_cas_req = true; @@ -4706,8 +4685,4 @@ vci_rsp_fifo_dcache_get = true; - // r_dcache_rsp_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid - vci_rsp_fifo_rpktid_get = true; - - r_dcache_miss_word = r_dcache_miss_word.read() + 1; @@ -4789,5 +4764,5 @@ #endif - r_dcache_fsm = DCACHE_MISS_BACKOFF; + //r_dcache_fsm = DCACHE_MISS_BACKOFF; r_dcache_count_backoff = r_dcache_count_backoff.read() + 1; r_dcache_count_begin = 0; @@ -4805,6 +4780,5 @@ #endif r_dcache_count_backoff = 0; - size_t way = r_dcache_miss_way.read(); - size_t set = r_dcache_miss_set.read(); + if ( r_dcache_rsp_state.read()) { @@ -4831,9 +4805,9 @@ << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif - // reset directory extension - if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; - else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; - else r_dcache_fsm = DCACHE_IDLE; - } + } + // reset directory extension + if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; + else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; + else r_dcache_fsm = DCACHE_IDLE; } break; @@ -5290,5 +5264,5 @@ else if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) { - assert((state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI) && " CC_UPDT WITH A NO INVALID STATE"); + assert(((state == CACHE_SLOT_STATE_INVALID) or (state == CACHE_SLOT_STATE_ZOMBI)) && " CC_UPDT WITH A NO INVALID STATE"); r_dcache_cc_send_multi_ack_miss = true; @@ -5304,42 +5278,4 @@ // signaling matching - // if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) - // { - // if(r_dcache_read_for_modify.read() and (r_dcache_miss_type == PROC_MISS)) - // { - // r_dcache_miss_inval = false; - // r_dcache_miss_updt = true; - // r_dcache_fsm = r_dcache_fsm_cc_save.read(); - // } - // else - // { - // // r_dcache_cc_send_multi_ack_miss = true; - // r_dcache_cc_send_multi_ack_miss = false; - // r_dcache_miss_inval = false; - // r_dcache_cc_state = CACHE_SLOT_STATE_INVALID; - // r_dcache_fsm = DCACHE_CC_UPDT; - // } - // } - // else - // { - // if(r_cc_receive_dcache_srcid.read() == m_srcid and r_cc_receive_brdcast.read() and (r_dcache_miss_type == PROC_MISS)) - // { - // assert(r_dcache_read_for_modify.read() && "miss inval for a miss getm in type of brdcast, this is impossible!!"); - // r_dcache_miss_inval = false; - // r_cc_receive_dcache_req = false; - // } - // else if(not r_cc_receive_brdcast.read() and r_dcache_read_for_modify.read() and (r_dcache_miss_type == PROC_MISS)) - // { - // r_dcache_miss_inval = false; - // r_dcache_miss_updt = true; - // } - // else - // { - // r_cc_receive_dcache_req = false; - // r_dcache_miss_inval = true; - // } - // r_dcache_fsm = r_dcache_fsm_cc_save.read(); - // } - #if DEBUG_DCACHE if ( m_debug_activated ) @@ -5360,7 +5296,4 @@ // CC request handler - - - #ifdef INSTRUMENTATION m_cpt_dcache_dir_read++; @@ -5542,5 +5475,4 @@ // after possible invalidation of copies in TLBs { - size_t word = r_dcache_cc_word.read(); size_t way = r_dcache_cc_way.read(); size_t set = r_dcache_cc_set.read(); @@ -6523,9 +6455,5 @@ vci_rsp_fifo_dcache_put, vci_rsp_fifo_dcache_data); - //BUG pktid -// r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get, -// vci_rsp_fifo_rpktid_put, -// vci_rsp_fifo_rpktid); -// + r_cc_send_data_fifo.update(cleanup_data_updt_fifo_dcache_get, cleanup_data_updt_fifo_dcache_put, @@ -6614,7 +6542,5 @@ p_vci.be = 0xF; p_vci.trdid = 0; - if(r_dcache_read_for_modify.read() and r_dcache_read_hit.read()) - p_vci.pktid = TYPE_WRITE + 0x8; - else if(r_dcache_read_for_modify.read() and not r_dcache_read_hit.read()) + if(r_dcache_read_for_modify.read()) p_vci.pktid = TYPE_WRITE; else Index: branches/MESI/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- branches/MESI/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 682) +++ branches/MESI/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 686) @@ -361,5 +361,5 @@ // - way : (return argument) the way to evince ///////////////////////////////////////////////////////////////////// - DirectoryEntry select(const size_t &set, size_t &way) + DirectoryEntry select(const size_t &set, int &way) { assert( (set < m_sets) Index: branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 682) +++ branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 686) @@ -225,9 +225,6 @@ WRITE_MISS_TRT_DATA, WRITE_MISS_XRAM_REQ, - WRITE_INVAL_TRT_LOCK, WRITE_INVAL_IVT_LOCK, - WRITE_DIR_INVAL, - WRITE_INVAL_CC_SEND, - WRITE_INVAL_XRAM_REQ + WRITE_INVAL_CC_SEND }; Index: branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 682) +++ branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 686) @@ -193,9 +193,6 @@ "WRITE_MISS_TRT_DATA", "WRITE_MISS_XRAM_REQ", - "WRITE_INVAL_TRT_LOCK", "WRITE_INVAL_IVT_LOCK", - "WRITE_DIR_INVAL", - "WRITE_INVAL_CC_SEND", - "WRITE_INVAL_XRAM_REQ" + "WRITE_INVAL_CC_SEND" }; const char *ixr_rsp_fsm_str[] = @@ -465,4 +462,6 @@ r_read_fsm( "r_read_fsm" ), + m_read_to_cc_send_inst_fifo("m_read_to_cc_send_inst_fifo",8), + m_read_to_cc_send_srcid_fifo("m_read_to_cc_send_srcid_fifo",8), r_write_fsm( "r_write_fsm" ), @@ -479,8 +478,4 @@ m_cas_to_cc_send_inst_fifo("m_cas_to_cc_send_inst_fifo",8), m_cas_to_cc_send_srcid_fifo("m_cas_to_cc_send_srcid_fifo",8), - - m_read_to_cc_send_inst_fifo("m_read_to_cc_send_inst_fifo",8), - m_read_to_cc_send_srcid_fifo("m_read_to_cc_send_srcid_fifo",8), - r_ixr_rsp_fsm("r_ixr_rsp_fsm"), r_xram_rsp_fsm("r_xram_rsp_fsm"), @@ -2160,10 +2155,8 @@ assert(((entry.count == 1) or (entry.count == 0)) && "multi ack for a ll request, count is 1"); r_multi_ack_fsm = MULTI_ACK_DIR_UPDT; - //r_multi_ack_rsp_shared = false; } else { r_multi_ack_fsm = MULTI_ACK_HEAP_REQ; - //r_multi_ack_rsp_shared = true; } break; @@ -2172,5 +2165,4 @@ case MULTI_ACK_IVT_CHANGE: // release all locks and retry from beginning { - //if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break; if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK ) { @@ -2217,4 +2209,8 @@ r_multi_ack_data[word]); } + // addr_t min = r_multi_ack_nline.read()*m_words*4 ; + // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4; + // m_llsc_table.sw(min, max); + } else @@ -2364,4 +2360,9 @@ r_multi_ack_data[word]); } + + // addr_t min = r_multi_ack_nline.read()*m_words*4 ; + // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4; + // m_llsc_table.sw(min, max); + } else @@ -3146,4 +3147,8 @@ r_read_fsm = READ_IVT_INVAL_LOCK; } + + addr_t min = m_cmd_read_addr_fifo.read(); + addr_t max = m_cmd_read_addr_fifo.read() + m_cmd_read_length_fifo.read()*4; + m_llsc_table.sw(min, max); } else // a read miss request @@ -3254,19 +3259,11 @@ r_read_to_cleanup_req = true; } + r_read_to_cc_send_type = true; //CC_INVAL - - // if(not match_send) - // { - read_to_cc_send_fifo_srcid = r_read_copy.read(); - read_to_cc_send_fifo_inst = r_read_copy_inst.read(); - read_to_cc_send_fifo_put = multi_req; - // } - r_read_next_ptr = r_read_ptr.read(); - - // if(((m_cmd_read_pktid_fifo.read() & 0x8) == 0x8) and (r_read_state.read() == ENTRY_SHARED)) - // ivt_send_count = r_read_count.read() - 1; - // else - // ivt_send_count = r_read_count.read(); - + read_to_cc_send_fifo_srcid = r_read_copy.read(); + read_to_cc_send_fifo_inst = r_read_copy_inst.read(); + read_to_cc_send_fifo_put = multi_req; + r_read_next_ptr = r_read_ptr.read(); + m_ivt.set(false, // it's an inval transaction not multi_req, // multi_inval or brdcast @@ -3326,14 +3323,9 @@ HeapEntry entry = m_heap.read(r_read_next_ptr.read()); - // bool match_send = ( entry.owner.srcid == m_cmd_read_srcid_fifo.read()) and - // ( entry.owner.inst == 0); - // if(not match_send) - // { read_to_cc_send_fifo_srcid = entry.owner.srcid; read_to_cc_send_fifo_inst = entry.owner.inst; read_to_cc_send_fifo_put = true; - // } - // if(read_to_cc_send_inst_fifo.wok()) always not full - r_read_next_ptr = entry.next; + r_read_next_ptr = entry.next; + if(entry.next == r_read_next_ptr.read()) // last copy { @@ -3404,5 +3396,5 @@ r_read_to_cc_send_multi_req.read() or r_read_to_cc_send_brdcast_req.read() or - (r_read_to_multi_ack_req.read() and r_read_need_block.read())) // ll or read not align block the request + (r_read_to_multi_ack_req.read() and r_read_need_block.read())) // ll request or the read request is not align a cache line { r_read_fsm = READ_WAIT; @@ -3462,6 +3454,6 @@ r_read_to_cc_send_ivt_index = index; - r_read_fsm = READ_IDLE; - cmd_read_fifo_get = true; + r_read_fsm = READ_IDLE; + cmd_read_fifo_get = true; #if DEBUG_MEMC_READ @@ -4112,6 +4104,4 @@ DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); - size_t set = m_y[(addr_t)(r_write_address.read())]; - addr_t nline = m_nline[(addr_t)(r_write_address.read())]; if(entry.state != ENTRY_INVALID) // hit { @@ -4143,14 +4133,5 @@ else // invalid the line and send multi_inval or brdcast to cache L1, and set trt table to evict the line { - // if(entry.state == ENTRY_EXCLUSIVE) - // { - // r_write_inval_trt_send = false; - // } - // else - // { - // r_write_inval_trt_send = true; - // } r_write_fsm = WRITE_INVAL_IVT_LOCK; - } } @@ -4158,15 +4139,5 @@ else // miss { - // if a miss write matched with a trt wait situation(wait for dirty data), it must block the command write until the dirty data has arrived in memcache - // if(r_write_to_cleanup_req.read() and - // r_write_to_cleanup_nline.read() == nline) - // { - // std::cout << "hit write cleanup nline =" << std::hex << nline << std::endl; - // r_write_fsm = WRITE_WAIT; - // } - // else - // { - r_write_fsm = WRITE_MISS_TRT_LOCK; - // } + r_write_fsm = WRITE_MISS_TRT_LOCK; } @@ -4187,66 +4158,4 @@ break; } - //////////////////// -// case WRITE_IVT_LOCK_HIT_WB: -// { -// if(r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) -// { -// -// size_t index = 0; -// bool match_inval; -// addr_t nline = m_nline[(addr_t)(r_write_address.read())]; -// -// //std::cout << "WRITE on NCC on line" << std::hex << nline << std::dec << std::endl; -// //if there is a matched updt req, we should wait until it is over. Because -// //we need the lastest updt data. -// match_inval = m_ivt.search_inval(nline, index); -// -// assert ((r_write_count.read() == 1) and "NCC to CC req without copy"); -// -// if( not match_inval and -// not r_write_to_cc_send_multi_req.read() and -// not r_write_to_cc_send_brdcast_req.read() ) -// { -// r_write_to_cc_send_multi_req = true; -// r_write_to_cc_send_dest = r_write_copy; -// r_write_to_cc_send_nline = nline; -// r_write_to_cleanup_req = true; -// r_write_to_cleanup_nline = nline; -// write_to_cc_send_fifo_put = true; -// write_to_cc_send_fifo_inst = r_write_copy_inst.read(); -// write_to_cc_send_fifo_srcid = r_write_copy.read(); -// -// m_ivt.set(false, // it's an inval transaction -// false, // it's not a broadcast -// false, // it needs no response -// false, // no acknowledge required -// m_cmd_write_srcid_fifo.read(), //never read, used for debug -// m_cmd_write_trdid_fifo.read(), //never read, used for debug -// m_cmd_write_pktid_fifo.read(), //never read, used for debug -// nline, -// 0x1, //Expect only one answer -// index); -// } -// r_write_fsm = WRITE_WAIT; -//#if DEBUG_MEMC_WRITE -// if(m_debug) -// { -// std::cout << " get access to the UPT: " -// << " Inval requested = " << (not match_inval and not r_write_to_cc_send_req.read()) -// << std::endl; -// } -//#endif -// break; -// } -//#if DEBUG_MEMC_WRITE -// if(m_debug) -// { -// std::cout << " failed to access to the IVT: " -// << std::endl; -// } -//#endif -// break; -// } -// /////////////////// case WRITE_DIR_HIT: @@ -4276,17 +4185,4 @@ r_write_fsm = WRITE_RSP; - // owner is true when the the first registered copy is the writer itself - //bool owner = (((r_write_copy.read() == r_write_srcid.read()) - // ) and not r_write_copy_inst.read()); - - // no_update is true when there is no need for coherence transaction - // bool no_update = ( (r_write_count.read() == 0) or - // (owner and (r_write_count.read() == 1) and - // ((r_write_pktid.read() & 0x7) != TYPE_SC))); - - // write data in the cache if no coherence transaction - //if(no_update) - //{ - // SC command but zero copies if ((r_write_pktid.read() & 0x7) == TYPE_SC) { @@ -4300,30 +4196,4 @@ } - //} - - //if (owner and not no_update and ((r_write_pktid.read() & 0x7) != TYPE_SC)) - //{ - // r_write_count = r_write_count.read() - 1; - //} - - //if(no_update) - // // Write transaction completed - //{ - // r_write_fsm = WRITE_RSP; - //} - //else - // // coherence update required - //{ - // if( not r_write_to_cc_send_multi_req.read() and - // not r_write_to_cc_send_brdcast_req.read() and - // not r_write_to_cc_send_req.read() ) - // { - // r_write_fsm = WRITE_UPT_LOCK; - // } - // else - // { - // r_write_fsm = WRITE_WAIT; - // } - //} #if DEBUG_MEMC_WRITE @@ -4432,165 +4302,4 @@ break; } - - ////////////////// -// case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM -// // and write the first copy in the FIFO -// // send the request if only one copy -// { -// assert( not r_write_to_cc_send_multi_req.read() and -// not r_write_to_cc_send_brdcast_req.read() and -// not r_write_to_cc_send_req.read() and -// "Error in VCI_MEM_CACHE : pending multicast or broadcast\n" -// "transaction in WRITE_UPT_REQ state" -// ); -// -// -// r_write_to_cc_send_brdcast_req = false; -// r_write_to_cc_send_trdid = r_write_ivt_index.read(); -// r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; -// r_write_to_cc_send_index = r_write_word_index.read(); -// r_write_to_cc_send_count = r_write_word_count.read(); -// -// for(size_t i=0; i Post first request to CC_SEND FSM" -// << " / srcid = " << std::dec << r_write_copy.read() -// << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; -// -// if(r_write_count.read() == 1) -// std::cout << " ... and this is the last" << std::endl; -// } -//#endif -// break; -// } -// -// /////////////////// -// case WRITE_UPT_NEXT: -// { -// // continue the multi-update request to CC_SEND fsm -// // when there is copies in the heap. -// // if one copy in the heap is the writer itself -// // the corresponding SRCID should not be written in the fifo, -// // but the UPT counter must be decremented. -// // As this decrement is done in the WRITE_UPT_DEC state, -// // after the last copy has been found, the decrement request -// // must be registered in the r_write_to_dec flip-flop. -// -// HeapEntry entry = m_heap.read(r_write_ptr.read()); -// -// bool dec_upt_counter; -// -// // put the next srcid in the fifo -// if ((entry.owner.srcid != r_write_srcid.read()) or -// ((r_write_pktid.read() & 0x7) == TYPE_SC) or -// entry.owner.inst) -// { -// dec_upt_counter = false; -// write_to_cc_send_fifo_put = true; -// write_to_cc_send_fifo_inst = entry.owner.inst; -// write_to_cc_send_fifo_srcid = entry.owner.srcid; -// -//#if DEBUG_MEMC_WRITE -// if(m_debug) -// { -// std::cout << " Post another request to CC_SEND FSM" -// << " / heap_index = " << std::dec << r_write_ptr.read() -// << " / srcid = " << std::dec << r_write_copy.read() -// << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; -// if(entry.next == r_write_ptr.read()) -// std::cout << " ... and this is the last" << std::endl; -// } -//#endif -// } -// else // the UPT counter must be decremented -// { -// dec_upt_counter = true; -// -//#if DEBUG_MEMC_WRITE -// if(m_debug) -// { -// std::cout << " Skip one entry in heap matching the writer" -// << " / heap_index = " << std::dec << r_write_ptr.read() -// << " / srcid = " << std::dec << r_write_copy.read() -// << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; -// if(entry.next == r_write_ptr.read()) -// std::cout << " ... and this is the last" << std::endl; -// } -//#endif -// } -// -// // register the possible UPT decrement request -// r_write_to_dec = dec_upt_counter or r_write_to_dec.read(); -// -// if(not m_write_to_cc_send_inst_fifo.wok()) -// { -// std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl -// << "The write_to_cc_send_fifo should not be full" << std::endl -// << "as the depth should be larger than the max number of copies" << std::endl; -// exit(0); -// } -// -// r_write_ptr = entry.next; -// -// if(entry.next == r_write_ptr.read()) // last copy -// { -// r_write_to_cc_send_multi_req = true; -// if(r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; -// else r_write_fsm = WRITE_IDLE; -// } -// break; -// } -// -// ////////////////// -// case WRITE_UPT_DEC: -// { -// // If the initial writer has a copy, it should not -// // receive an update request, but the counter in the -// // update table must be decremented by the MULTI_ACK FSM. -// -// if(!r_write_to_multi_ack_req.read()) -// { -// r_write_to_multi_ack_req = true; -// r_write_to_multi_ack_upt_index = r_write_upt_index.read(); -// r_write_fsm = WRITE_IDLE; -// } -// break; -// } -// /////////////// case WRITE_RSP: @@ -4678,21 +4387,4 @@ break; } -// case WRITE_MISS_IVT_LOCK: -// { -// if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) -// { -// size_t index; -// if(m_ivt.search_inval(m_nline[(addr_t)(r_write_address.read())], index)) -// { -// r_write_fsm = WRITE_WAIT; -// } -// else -// { -// r_write_fsm = WRITE_MISS_TRT_LOCK; -// } -// } -// break; -// } -// ///////////////////////// case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table @@ -4845,61 +4537,4 @@ break; } - -// /////////////////////// -// case WRITE_INVAL_DIR_READ: // enter this state if a broadcast-inval is required -// // the cache line must be erased in mem-cache, and written -// // into XRAM. -// { -// assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and -// "MEMC ERROR in WRITE_INVAL_DIR_READ state: Bad DIR allocation"); -// -// // write enable signal for data buffer. -// r_write_bc_data_we = true; -// -// r_write_fsm = WRITE_INVAL_TRT_LOCK; -// -//#if DEBUG_MEMC_WRITE -// if (m_debug) -// std::cout << " " -// << " Read the cache to complete local buffer" << std::endl; -//#endif -// break; -// } - /////////////////////// - case WRITE_INVAL_TRT_LOCK: // get TRT lock to check TRT not full - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and - "MEMC ERROR in WRITE_INVAL_TRT_LOCK state: Bad DIR allocation"); - - if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) - break; - - // We read the cache and complete the buffer. As the DATA cache uses a - // synchronous RAM, the read DATA request has been performed in the - // WRITE_INVAL_DIR_READ state but the data is available in this state. - size_t wok_index = 0; - bool wok = not m_trt.full(wok_index); - if(wok) // set a new entry in TRT - { - r_write_trt_index = wok_index; - r_write_fsm = WRITE_INVAL_IVT_LOCK; - } - else // wait an empty entry in TRT - { - r_write_fsm = WRITE_WAIT; - } - -#if DEBUG_MEMC_WRITE - if(m_debug) - std::cout << " Check TRT : wok = " << wok - << " / index = " << wok_index << std::endl; -#endif - - m_cpt_write_fsm_trt_lock++; - - break; - } - ////////////////////// case WRITE_INVAL_IVT_LOCK: // register BC transaction in IVT @@ -4955,24 +4590,4 @@ << " / nb_copies = " << r_write_count.read() << std::endl; #endif - // for(size_t word=0 ; word data_vector; - // data_vector.clear(); - // for(size_t i=0; i (m_words,0), - // data_vector ); - - // invalidate directory entry - DirectoryEntry entry; - entry.state = ENTRY_LOCKED; - entry.dirty = true; - entry.tag = r_write_tag.read(); - entry.is_cnt = 0; - entry.lock = false; - entry.owner.srcid = 0; - entry.owner.inst = false; - entry.ptr = 0; - entry.count = 0; - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - m_cache_directory.write(set, way, entry); - - if ((r_write_pktid.read() & 0x7) == TYPE_SC) - { - m_llsc_table.sc(r_write_address.read(), - r_write_sc_key.read()); - } - -#if DEBUG_MEMC_WRITE - if(m_debug) - std::cout << " Invalidate the directory entry: @ = " - << r_write_address.read() << " / register the put transaction in TRT:" << std::endl; -#endif - r_write_fsm = WRITE_INVAL_CC_SEND; - break; - } - ////////////////////// case WRITE_INVAL_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM @@ -5084,5 +4638,4 @@ { bool last_multi_inval = (r_write_count.read() == 1) and not r_write_is_cnt.read(); - bool not_last_multi_inval = (r_write_count.read() != 1) and not r_write_is_cnt.read(); bool multi_inval = not r_write_is_cnt.read(); @@ -5107,14 +4660,5 @@ else { - // if(r_write_inval_trt_send.read()) - // { - // r_write_fsm = WRITE_INVAL_XRAM_REQ; - // } - // else //the line is in exlusive state, must wait for the - // //response of multi_inval in reason of receiving the updated data - // { - r_write_fsm = WRITE_IDLE; - - // } + r_write_fsm = WRITE_IDLE; } #if DEBUG_MEMC_WRITE @@ -5127,28 +4671,4 @@ { assert( false && "CC SEND FLAGS IS TURE in WRITE_INVAL_CC_SEND state"); - } - break; - } - - /////////////////////// - case WRITE_INVAL_XRAM_REQ: // Post a put request to IXR_CMD FSM - { - if( not r_write_to_ixr_cmd_req.read() ) - { - if((r_write_state.read() == ENTRY_EXCLUSIVE) and (r_write_count.read() == 1)) - { - std::cout << "can't send a trt req when the line state is exlusive"<< std::endl; - exit(0); - } - - r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_index = r_write_trt_index.read(); - r_write_fsm = WRITE_IDLE; - -#if DEBUG_MEMC_WRITE - if(m_debug) - std::cout << " Post a put request to IXR_CMD FSM" << std::endl; -#endif } break; @@ -5755,8 +5275,20 @@ // selects & extracts a victim line from cache - size_t way = 0; + int way = 0; size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)]; DirectoryEntry victim(m_cache_directory.select(set, way)); + + if( way == -1) + { +#if DEBUG_MEMC_XRAM_RSP + if(m_debug) + std::cout << " " + << " not a disponible victim" + << std::endl; +#endif + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + break; + } bool inval = (victim.count != 0) and (victim.state != ENTRY_INVALID) ; @@ -5782,6 +5314,4 @@ else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; - if( way == -1) r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; - #if DEBUG_MEMC_XRAM_RSP if(m_debug) @@ -6435,13 +5965,4 @@ (r_write_to_cleanup_data[r_cleanup_data_index.read()].read() & mask) | (data & ~mask); - - int data_out = (r_write_to_cleanup_data[r_cleanup_data_index.read()].read() & mask) | - (data & ~mask); - - /*// std::cout << "receive write nline " << std::hex << r_cleanup_nline.read() - << "word " << r_cleanup_data_index.read() - << "data " - << data_out << std::endl;*/ - } else @@ -6504,6 +6025,4 @@ exit(0); } - //std::cout << " MEM_CACHE : CLEANUP_DIR_LOCK" << std::endl; - // Read the directory size_t way = 0; @@ -6521,7 +6040,4 @@ r_cleanup_copy_inst = entry.owner.inst; r_cleanup_state = entry.state; - - //size_t set = m_y[(addr_t)(cleanup_address)]; - //m_cache_data.read_line(way, set, r_cleanup_old_data); if(entry.state == ENTRY_LOCKED) @@ -6627,11 +6143,9 @@ if( entry.count == 0) { - //entry.state = ENTRY_EXCLUSIVE; - entry.is_cnt = 0; + entry.is_cnt = 0; } else { - //entry.state = ENTRY_SHARED; - entry.is_cnt = r_cleanup_is_cnt.read(); + entry.is_cnt = r_cleanup_is_cnt.read(); } @@ -6642,7 +6156,7 @@ m_cache_data.write(way, set, word, r_cleanup_data[word].read(), 0xF); } - addr_t min = r_cleanup_nline.read()*m_words*4 ; - addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; - m_llsc_table.sw(min, max); + // addr_t min = r_cleanup_nline.read()*m_words*4 ; + // addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; + // m_llsc_table.sw(min, max); } @@ -6757,9 +6271,4 @@ addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; - //size_t match_cas_multi_inval = r_cas_to_cleanup_req.read() and - // (r_cas_to_cleanup_nline.read() == r_cleanup_nline.read()); - - //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; - //size_t match_sc_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_SC; bool match_ll = ((r_cleanup_locked_pktid.read() & 0x07) == TYPE_LL); @@ -6781,7 +6290,4 @@ m_cache_data.write(way, set, word, r_write_to_cleanup_data[word].read(), r_write_to_cleanup_be[word].read()); } - //addr_t min = r_cleanup_nline.read()*m_words*4 ; - //addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; - //m_llsc_table.sw(min, max); } @@ -6798,7 +6304,7 @@ if((r_cleanup_locked_pktid.read() & 0x7) != TYPE_SC) { - addr_t min = r_cleanup_nline.read()*m_words*4 ; - addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; - m_llsc_table.sw(min, max); + // addr_t min = r_cleanup_nline.read()*m_words*4 ; + // addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; + // m_llsc_table.sw(min, max); } } @@ -6841,9 +6347,4 @@ else // cas, getm, one copy updated in dir { - // if(match_cas_inval or match_sc_inval) - // { - // entry.state = ENTRY_SHARED; - // entry.count = 0; - // } if(r_cleanup_locked_is_read.read()) { @@ -6884,6 +6385,4 @@ { if(r_cleanup_to_tgt_rsp_req.read()) break; - - //size_t match_cas_inval = (r_cleanup_locked_pktid.read() & 0x7) == TYPE_CAS; r_cleanup_to_tgt_rsp_req = true; @@ -7362,9 +6861,4 @@ r_cleanup_to_ixr_cmd_req = true; - // if( (r_write_to_cleanup_req == true) and (r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) ) - // { - // r_write_to_cleanup_req = false; - // } - if (r_cleanup_contains_data.read()) { @@ -7389,15 +6883,10 @@ data_vector); - addr_t min = r_cleanup_nline.read()*m_words*4 ; - addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; - m_llsc_table.sw(min, max); + // addr_t min = r_cleanup_nline.read()*m_words*4 ; + // addr_t max = r_cleanup_nline.read()*m_words*4 + (m_words - 1)*4; + // m_llsc_table.sw(min, max); } - //std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl; - //r_cleanup_to_ixr_cmd_srcid = r_cleanup_srcid.read(); - r_cleanup_to_ixr_cmd_index = index; - //r_cleanup_to_ixr_cmd_pktid = r_cleanup_pktid.read(); - //r_cleanup_to_ixr_cmd_nline = r_cleanup_nline.read(); - //r_cleanup_to_ixr_cmd_l1_dirty_ncc = r_cleanup_contains_data.read(); - r_cleanup_fsm = CLEANUP_SEND_CLACK; + r_cleanup_to_ixr_cmd_index = index; + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP if(m_debug) @@ -7693,15 +7182,4 @@ } -// else if(r_cas_is_cnt.read() and r_cas_state.read() == ENTRY_SHARED) -// { -// r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required -//#if DEBUG_MEMC_CAS -// if(m_debug) -// std::cout << " " -// << " Broacast Inval required" -// << " / copies = " << r_cas_count.read() << std::endl; -//#endif -// -// } else { @@ -7714,13 +7192,4 @@ #endif } -// else -// { -// r_cas_fsm = CAS_WAIT; -//#if DEBUG_MEMC_CAS -// if(m_debug) -// std::cout << " " -// << " CC_SEND FSM busy: release all locks and retry" << std::endl; -//#endif -// } } else // no copies or multi_inval finished @@ -7766,25 +7235,5 @@ size_t pktid = m_cmd_cas_pktid_fifo.read(); addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t nb_copies_sent = 0; - - // if(r_cas_state.read() == ENTRY_EXCLUSIVE) - // { - // nb_copies_sent = 1; - // } - // else - // { - nb_copies_sent = r_cas_count.read(); - // } -// if(m_ivt.search_inval(nline, index) and r_cas_to_cleanup_req.read()) -// { -//#if DEBUG_MEMC_CAS -// if(m_debug) -// std::cout << " pending ivt " -// << std::endl; -//#endif -// r_cas_fsm = CAS_WAIT; -// break; -// } + wok = m_ivt.set(false, // it's an invalid transaction false, // it's not a broadcast @@ -7795,5 +7244,5 @@ pktid, nline, - nb_copies_sent, + r_cas_count.read(), false, // is a command write index); @@ -7862,5 +7311,5 @@ << " / way = " << way << " / nline = " << std::hex << nline - << " / count = " << nb_copies_sent << std::endl; + << " / count = " << r_cas_count.read() << std::endl; #endif } @@ -7914,6 +7363,4 @@ "VCI_MEM_CACHE ERROR : bad HEAP allocation"); - bool match_srcid = r_cas_copy.read() == m_cmd_cas_srcid_fifo.read(); - assert(not r_cas_copy_inst.read() && "cas fsm: cas has a copy inst"); @@ -7922,7 +7369,4 @@ r_cas_next_ptr = r_cas_ptr.read(); r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - //r_cas_to_cc_send_trdid = r_cas_ivt_index.read(); - //r_cas_to_cc_send_index = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - //r_cas_to_cc_send_wdata = r_cas_wdata.read(); cas_to_cc_send_fifo_put = true; @@ -7963,8 +7407,4 @@ HeapEntry entry = m_heap.read(r_cas_next_ptr.read()); - - bool match_srcid = (entry.owner.srcid == m_cmd_cas_srcid_fifo.read()); - - addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; assert(not entry.owner.inst && "cas fsm: cas has a copy inst"); @@ -7978,7 +7418,5 @@ if(entry.next == r_cas_next_ptr.read()) // last copy { - //r_cas_to_cleanup_nline = nline; r_cas_to_cc_send_multi_req = true; - //r_cas_to_cleanup_req = true; r_cas_fsm = CAS_HEAP_LAST; // Response will be sent after receiving } @@ -7991,5 +7429,4 @@ << " / wdata = " << std::hex << r_cas_wdata.read() << " / srcid = " << std::dec << entry.owner.srcid - << " / match srcid = " << match_srcid << " / inst = " << std::dec << entry.owner.inst << std::endl; } @@ -8007,6 +7444,4 @@ } size_t free_pointer = m_heap.next_free_ptr(); - - addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; HeapEntry last_entry; @@ -8200,8 +7635,5 @@ r_cas_to_cc_send_multi_req = false; r_cas_to_cc_send_brdcast_req = true; - //r_cas_to_cc_send_trdid = r_cas_ivt_index.read(); r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - //r_cas_to_cc_send_index = 0; - //r_cas_to_cc_send_wdata = 0; r_cas_fsm = CAS_BC_XRAM_REQ; @@ -8449,10 +7881,4 @@ // WRITE -// if(r_write_to_cc_send_req.read()) -// { -// r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; -// break; -// } - if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -8533,9 +7959,4 @@ } // WRITE -// if(r_write_to_cc_send_req.read()) -// { -// r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER; -// break; -// } if(m_write_to_cc_send_inst_fifo.rok() or r_write_to_cc_send_multi_req.read()) @@ -8756,5 +8177,4 @@ case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) { - if(m_config_to_cc_send_inst_fifo.rok()) { @@ -8939,33 +8359,4 @@ break; } -// case CC_SEND_WRITE_INVAL_HEADER: -// { -// if(not p_dspin_m2p.read) break; -// -// r_cc_send_fsm = CC_SEND_WRITE_INVAL_NLINE; -// break; -// } -// -// case CC_SEND_WRITE_INVAL_NLINE: -// { -// if(not p_dspin_m2p.read) break; -// -// r_write_to_cc_send_req = false; -// r_cc_send_fsm = CC_SEND_WRITE_IDLE; -// -//#if DEBUG_MEMC_CC_SEND -// if(m_debug) -// { -// std::cout -// << " Inval for line " -// << r_write_to_cc_send_nline.read() -// << std::endl; -// } -//#endif -// break; -// } -// - ////////////////////////////////// case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) @@ -9001,16 +8392,4 @@ { if(not p_dspin_m2p.read) break; -// // -// if (is_local_req(m_write_to_cc_send_srcid_fifo.read())) -// { -// m_cpt_update_local++; -// } -// else -// { -// m_cpt_update_remote++; -// m_cpt_update_cost += req_distance(m_write_to_cc_send_srcid_fifo.read()); -// } -// // - r_cc_send_fsm = CC_SEND_WRITE_INVAL_NLINE; break; @@ -9043,18 +8422,4 @@ break; } - ///////////////////////////// -// case CC_SEND_WRITE_UPDT_DATA: // send N data flits for a multi-update (from WRITE FSM) -// { -// if(not p_dspin_m2p.read) break; -// if(r_cc_send_cpt.read() == r_write_to_cc_send_count.read()) -// { -// write_to_cc_send_fifo_get = true; -// r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; -// break; -// } -// -// r_cc_send_cpt = r_cc_send_cpt.read() + 1; -// break; -// } //////////////////////////////// case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) @@ -9089,15 +8454,4 @@ { if(not p_dspin_m2p.read) break; - // -// if (is_local_req(m_cas_to_cc_send_srcid_fifo.read())) -// { -// m_cpt_update_local++; -// } -// else -// { -// m_cpt_update_remote++; -// m_cpt_update_cost += req_distance(m_cas_to_cc_send_srcid_fifo.read()); -// } -// // r_cc_send_fsm = CC_SEND_CAS_INVAL_NLINE; break; @@ -9110,7 +8464,4 @@ } - // -// m_cpt_update++; - // r_cc_send_fsm = CC_SEND_CAS_IDLE; break; @@ -9131,27 +8482,4 @@ break; } - /////////////////////////// -// case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) -// { -// if(not p_dspin_m2p.read) break; -// -// if(r_cas_to_cc_send_is_long.read()) -// { -// r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH; -// break; -// } -// -// cas_to_cc_send_fifo_get = true; -// r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; -// break; -// } - //////////////////////////////// -// case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for a multi-update (from CAS FSM) -// { -// if(not p_dspin_m2p.read) break; -// cas_to_cc_send_fifo_get = true; -// r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; -// break; -// } } // end switch r_cc_send_fsm @@ -9857,63 +9185,4 @@ } } // end switch tgt_rsp_fsm - - //////////////////////////////////////////////////////////////////////////////////// - // ALLOC_UPT FSM - //////////////////////////////////////////////////////////////////////////////////// - // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), - // with a round robin priority between three FSMs, with the following order: - // WRITE -> CAS -> MULTI_ACK - // - The WRITE FSM initiates update transaction and sets a new entry in UPT. - // - The CAS FSM does the same thing as the WRITE FSM. - // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. - // The resource is always allocated. - ///////////////////////////////////////////////////////////////////////////////////// -// switch(r_alloc_upt_fsm.read()) -// { -// ///////////////////////// -// case ALLOC_UPT_WRITE: // allocated to WRITE FSM -// if (r_write_fsm.read() != WRITE_UPT_LOCK) -// { -// if (r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) -// r_alloc_upt_fsm = ALLOC_UPT_CAS; -// -// else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) -// r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; -// else -// m_cpt_upt_unused++; -// } -// break; -// -// ///////////////////////// -// case ALLOC_UPT_CAS: // allocated to CAS FSM -// if (r_cas_fsm.read() != CAS_MULTI_INVAL_IVT_LOCK) -// { -// if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) -// r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; -// -// else if (r_write_fsm.read() == WRITE_UPT_LOCK) -// r_alloc_upt_fsm = ALLOC_UPT_WRITE; -// -// else -// m_cpt_upt_unused++; -// } -// break; -// -// ///////////////////////// -// case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM -// if ((r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK ) and -// (r_multi_ack_fsm.read() != MULTI_ACK_UPT_CLEAR)) -// { -// if (r_write_fsm.read() == WRITE_UPT_LOCK) -// r_alloc_upt_fsm = ALLOC_UPT_WRITE; -// -// else if (r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) -// r_alloc_upt_fsm = ALLOC_UPT_CAS; -// else -// m_cpt_upt_unused++; -// } -// break; -// } // end switch r_alloc_upt_fsm -// //////////////////////////////////////////////////////////////////////////////////// // ALLOC_IVT FSM @@ -10253,5 +9522,4 @@ (r_write_fsm.read() != WRITE_HEAP_REQ) and (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and - (r_write_fsm.read() != WRITE_INVAL_TRT_LOCK) and (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) or @@ -10449,6 +9717,5 @@ if(r_read_fsm.read() != READ_TRT_LOCK) { - if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) + if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -10489,6 +9756,5 @@ case ALLOC_TRT_WRITE: if((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and - (r_write_fsm.read() != WRITE_INVAL_TRT_LOCK) and - (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) + (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) { if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or @@ -10559,6 +9825,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) + else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -10595,6 +9860,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) + else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -10626,6 +9890,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) + else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -10663,6 +9926,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) || - (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) + else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -10701,6 +9963,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) + else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -10734,6 +9995,5 @@ r_alloc_trt_fsm = ALLOC_TRT_READ; - else if((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or - (r_write_fsm.read() == WRITE_INVAL_TRT_LOCK)) + else if(r_write_fsm.read() == WRITE_MISS_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_WRITE; @@ -11696,8 +10956,4 @@ DspinDhccpParam::BROADCAST_SRCID); - // DspinDhccpParam::dspin_set( flit, - // r_read_to_cc_send_is_shared.read(), // send the actuel line state in memcache - // DspinDhccpParam::BRDCAST_IS_SHARED); - DspinDhccpParam::dspin_set( flit, 1ULL, @@ -11819,49 +11075,4 @@ } -// case CC_SEND_WRITE_INVAL_HEADER: -// { -// uint64_t flit = 0; -// -// DspinDhccpParam::dspin_set( -// flit, -// r_write_to_cc_send_dest.read(), -// DspinDhccpParam::MULTI_INVAL_DEST); -// -// DspinDhccpParam::dspin_set( -// flit, -// m_cc_global_id, -// DspinDhccpParam::MULTI_INVAL_SRCID); -// -// DspinDhccpParam::dspin_set( -// flit, -// DspinDhccpParam::TYPE_MULTI_INVAL_DATA, -// DspinDhccpParam::M2P_TYPE); -// -// p_dspin_m2p.write = true; -// p_dspin_m2p.data = flit; -// -// break; -// -// } -// -// case CC_SEND_WRITE_NCC_INVAL_NLINE: -// { -// uint64_t flit = 0; -// -// DspinDhccpParam::dspin_set( -// flit, -// r_write_to_cc_send_nline.read(), -// DspinDhccpParam::MULTI_INVAL_NLINE); -// -// -// p_dspin_m2p.write = true; -// p_dspin_m2p.data = flit; -// p_dspin_m2p.eop = true; -// -// break; -// -// } -// -// case CC_SEND_WRITE_BRDCAST_NLINE: { @@ -11932,9 +11143,4 @@ uint64_t flit = 0; - // DspinDhccpParam::dspin_set( - // flit, - // r_write_to_cc_send_index.read(), - // DspinDhccpParam::MULTI_UPDT_WORD_INDEX); - DspinDhccpParam::dspin_set( flit, @@ -11949,32 +11155,4 @@ break; } -// ///////////////////////////// -// case CC_SEND_WRITE_UPDT_DATA: -// { -// -// uint8_t multi_updt_cpt = -// r_cc_send_cpt.read() + r_write_to_cc_send_index.read(); -// -// uint8_t multi_updt_be = r_write_to_cleanup_be[multi_updt_cpt].read(); -// uint32_t multi_updt_data = r_write_to_cleanup_data[multi_updt_cpt].read(); -// -// uint64_t flit = 0; -// -// DspinDhccpParam::dspin_set( -// flit, -// multi_updt_be, -// DspinDhccpParam::MULTI_UPDT_BE); -// -// DspinDhccpParam::dspin_set( -// flit, -// multi_updt_data, -// DspinDhccpParam::MULTI_UPDT_DATA); -// -// p_dspin_m2p.write = true; -// p_dspin_m2p.eop = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()); -// p_dspin_m2p.data = flit; -// -// break; -// } //////////////////////////// case CC_SEND_CAS_INVAL_HEADER: @@ -12022,9 +11200,4 @@ uint64_t flit = 0; - // DspinDhccpParam::dspin_set( - // flit, - // r_cas_to_cc_send_index.read(), - // DspinDhccpParam::MULTI_UPDT_WORD_INDEX); - DspinDhccpParam::dspin_set( flit, @@ -12038,46 +11211,4 @@ break; } - /////////////////////////// -// case CC_SEND_CAS_UPDT_DATA: -// { -// uint64_t flit = 0; -// -// DspinDhccpParam::dspin_set( -// flit, -// 0xF, -// DspinDhccpParam::MULTI_UPDT_BE); -// -// DspinDhccpParam::dspin_set( -// flit, -// r_cas_to_cc_send_wdata.read(), -// DspinDhccpParam::MULTI_UPDT_DATA); -// -// p_dspin_m2p.write = true; -// p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); -// p_dspin_m2p.data = flit; -// -// break; -// } -// //////////////////////////////// -// case CC_SEND_CAS_UPDT_DATA_HIGH: -// { -// uint64_t flit = 0; -// -// DspinDhccpParam::dspin_set( -// flit, -// 0xF, -// DspinDhccpParam::MULTI_UPDT_BE); -// -// DspinDhccpParam::dspin_set( -// flit, -// r_cas_to_cc_send_wdata_high.read(), -// DspinDhccpParam::MULTI_UPDT_DATA); -// -// p_dspin_m2p.write = true; -// p_dspin_m2p.eop = true; -// p_dspin_m2p.data = flit; -// -// break; -// } }