Changeset 695 for branches

Timestamp:

May 18, 2014, 8:33:04 PM (11 years ago)

Author:

cfuguet

Message:

branches/fault-tolerance/tsar_generic_iob:

• Introducing multi-tty component in all clusters for debug. Number of channels is set by a proprocessor contant in the tsar_iob_cluster.h file. Number of channels can be 0 if tty isn't needed.

• Reducing number of parameters for cluster class. Using constants defined in hard_config.h instead.

Location:

branches/fault_tolerance/platform/tsar_generic_iob

Files:

• top.cpp (modified) (38 diffs)
• tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (modified) (5 diffs)
• tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (7 diffs)
• tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (modified) (45 diffs)

branches/fault_tolerance/platform/tsar_generic_iob/top.cpp

@@ -118 +118 @@
 #include <cstdarg>
 #include <stdint.h>
+#include <string>
 
 #include "gdbserver.h"
@@ -131 +132 @@
 
 #include "alloc_elems.h"
-
-///////////////////////////////////////////////////
-//      OS
-///////////////////////////////////////////////////
-#define USE_ALMOS 0
-
-#define almos_bootloader_pathname "bootloader.bin"
-#define almos_kernel_pathname     "kernel-soclib.bin@0xbfc10000:D"
-#define almos_archinfo_pathname   "arch-info.bin@0xBFC08000:D"
-
-///////////////////////////////////////////////////
-//               Parallelisation
-///////////////////////////////////////////////////
+#include "hard_config.h"
+
+////////////////////////////////////////////////////////////////////////
+//               Parallelization
+////////////////////////////////////////////////////////////////////////
+
 #define USE_OPENMP 0
 
@@ -150 +144 @@
 #endif
 
-///////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
 //          DSPIN parameters
-///////////////////////////////////////////////////////////
-
-#define dspin_int_cmd_width   39
-#define dspin_int_rsp_width   32
-
-#define dspin_ram_cmd_width   64
-#define dspin_ram_rsp_width   64
-
-///////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+#define dspin_int_cmd_width 39
+#define dspin_int_rsp_width 32
+
+#define dspin_ram_cmd_width 64
+#define dspin_ram_rsp_width 64
+
+////////////////////////////////////////////////////////////////////////
 //         VCI fields width  for the 3 VCI networks
-///////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
 
 #define vci_cell_width_int 4
@@ -177 +171 @@
 #define vci_wrplen_width   1
 
-////////////////////////////////////////////////////////////
-//    Main Hardware Parameters values
-//////////////////////i/////////////////////////////////////
-
-#define X_WIDTH   4
-#define Y_WIDTH   4
-#define X_MAX     (1<<X_WIDTH)
-#define Y_MAX     (1<<Y_WIDTH)
-
-////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
 //    Secondary Hardware Parameters values
-//////////////////////i/////////////////////////////////////
-
-#define XRAM_LATENCY       0
-
-#define MEMC_WAYS          16
-#define MEMC_SETS          256
-
-#define L1_IWAYS           4
-#define L1_ISETS           64
-
-#define L1_DWAYS           4
-#define L1_DSETS           64
-
-#define FBUF_X_SIZE        128
-#define FBUF_Y_SIZE        128
-
-#define BDEV_SECTOR_SIZE   512
-#define BDEV_IMAGE_NAME    "../../../giet_vm/hdd/virt_hdd.dmg"
-
-#define NIC_RX_NAME        "giet_vm/nic/rx_packets.txt"
-#define NIC_TX_NAME        "giet_vm/nic/tx_packets.txt"
-#define NIC_TIMEOUT        10000
-
-#define cluster(x,y)       ((y) + ((x)<<4))
-
-////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+#define XRAM_LATENCY     0
+
+#define MEMC_WAYS        16
+#define MEMC_SETS        256
+
+#define L1_IWAYS         4
+#define L1_ISETS         64
+
+#define L1_DWAYS         4
+#define L1_DSETS         64
+
+#define FBUF_X_SIZE      128
+#define FBUF_Y_SIZE      128
+
+#define BDEV_SECTOR_SIZE 512
+#define BDEV_IMAGE_NAME  "/dev/null"
+
+#define NIC_RX_NAME      "/dev/null"
+#define NIC_TX_NAME      "/dev/null"
+#define NIC_TIMEOUT      10000
+
+#define cluster(x,y)     TsarIobClusterType::clusterId((x),(y))
+
+////////////////////////////////////////////////////////////////////////
 //    Software to be loaded in ROM & RAM
-//////////////////////i/////////////////////////////////////
-
-#define BOOT_SOFT_NAME     "../../softs/tsar_boot/preloader.elf"
-
-////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+#define BOOT_SOFT_NAME "/dev/null"
+
+////////////////////////////////////////////////////////////////////////
 //     DEBUG Parameters default values
-//////////////////////i/////////////////////////////////////
-
-#define MAX_FROZEN_CYCLES  10000
-
-/////////////////////////////////////////////////////////
-//    Physical segments definition
-/////////////////////////////////////////////////////////
-
-// Non replicated peripherals (must be in cluster 0)
-
-#define BROM_BASE 0x00BFC00000
-#define BROM_SIZE 0x0000010000 // 64 Kbytes
-
-#define IOBX_BASE 0x00BE000000
-#define IOBX_SIZE 0x0000001000 // 4  Kbytes
-
-#define BDEV_BASE 0x00B3000000
-#define BDEV_SIZE 0x0000008000 // 4  Kbytes
-
-#define MTTY_BASE 0x00B4000000
-#define MTTY_SIZE (0x0000001000 * 16)  // 4 Kbytes
-
-#define MNIC_BASE 0x00B5000000
-#define MNIC_SIZE 0x0000080000 // 512 Kbytes
-
-#define CDMA_BASE 0x00B6000000
-#define CDMA_SIZE (0x0000001000 * 2)  // 4 Kbytes per channel
-
-#define FBUF_BASE 0x00B7000000
-#define FBUF_SIZE (800 * 600 * 2)
-
-// Replicated peripherals : address is incremented by a cluster offset
-//    offset  = cluster(x,y) << (address_width-x_width-y_width);
-
-#define XRAM_BASE 0x0000000000
-#define XRAM_SIZE 0x0010000000 // 256 Mbytes
-
-#define XICU_BASE 0x00B0000000
-#define XICU_SIZE 0x0000001000 // 4 Kbytes
-
-#define MDMA_BASE 0x00B1000000
-#define MDMA_SIZE 0x0000001000 * 4 // 4 Kbytes per channel
-
-// Replicated mem segments (XRAM) : address is incremented by a cluster offset
-//    offset = cluster(x,y) << (address_width-x_width-y_width);
-
-#define MEMC_BASE 0x00B2000000
-#define MEMC_SIZE 0x0000001000 // 4 Kbytes
+////////////////////////////////////////////////////////////////////////
+
+#define MAX_FROZEN_CYCLES 10000
 
 ////////////////////////////////////////////////////////////////////////
@@ -291 +231 @@
 ////////////////////////////////////////////////////////////////////////
 
-#define PROC_LOCAL_SRCID   0x0 // from 0 to 7
-#define MDMA_LOCAL_SRCID   0x8
-#define IOBX_LOCAL_SRCID   0x9
-#define MEMC_LOCAL_SRCID   0xA
-#define CDMA_LOCAL_SRCID   0xE // hard-coded in dspin_tsar
-#define BDEV_LOCAL_SRCID   0xF // hard-coded in dspin_tsar
-
-///////////////////////////////////////////////////////////////////////
-//     TGT_ID and INI_ID port indexing for INT local interconnect
-///////////////////////////////////////////////////////////////////////
-
-#define INT_MEMC_TGT_ID 0
-#define INT_XICU_TGT_ID 1
-#define INT_BROM_TGT_ID 2
-#define INT_MDMA_TGT_ID 3
-#define INT_IOBX_TGT_ID 4
-
-#define INT_PROC_INI_ID 0 // from 0 to 7
-#define INT_MDMA_INI_ID nb_procs
-#define INT_IOBX_INI_ID (nb_procs + 1)
-
-///////////////////////////////////////////////////////////////////////
-//     TGT_ID and INI_ID port indexing for RAM local interconnect
-///////////////////////////////////////////////////////////////////////
-
-#define RAM_XRAM_TGT_ID 0
-
-#define RAM_MEMC_INI_ID 0
-#define RAM_IOBX_INI_ID 1
+#define PROC_LOCAL_SRCID 0x0 // from 0 to 7
+#define MDMA_LOCAL_SRCID 0x8
+#define IOBX_LOCAL_SRCID 0x9
+#define MEMC_LOCAL_SRCID 0xA
+#define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar
+#define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar
 
 ///////////////////////////////////////////////////////////////////////
@@ -339 +256 @@
 
 ////////////////////////////////////////////////////////////////////////
-int _main(int argc, char *argv[])
-////////////////////////////////////////////////////////////////////////
-{
+int _main(int argc, char *argv[]) {
    using namespace sc_core;
    using namespace soclib::caba;
    using namespace soclib::common;
 
-   char     soft_name[256]   = BOOT_SOFT_NAME;    // pathname: binary code
-   size_t   ncycles          = 1000000000;        // simulated cycles
-   char     disk_name[256]   = BDEV_IMAGE_NAME;   // pathname: disk image
-   char     nic_rx_name[256] = NIC_RX_NAME;       // pathname: rx packets file
-   char     nic_tx_name[256] = NIC_TX_NAME;       // pathname: tx packets file
-   ssize_t  threads_nr       = 1;                 // simulator's threads number
+   char     soft_name[256]   = BOOT_SOFT_NAME;    // path: binary code
+   uint64_t ncycles          = 1000000000;        // simulated cycles
+   char     disk_name[256]   = BDEV_IMAGE_NAME;   // path: disk image
+   char     nic_rx_name[256] = NIC_RX_NAME;       // path: rx packets file
+   char     nic_tx_name[256] = NIC_TX_NAME;       // path: tx packets file
+   ssize_t  threads_nr       = 1;                 // simulator's threads
    bool     debug_ok         = false;             // trace activated
    size_t   debug_period     = 1;                 // trace period
@@ -359 +274 @@
    uint32_t debug_from       = 0;                 // trace start cycle
    uint32_t frozen_cycles    = MAX_FROZEN_CYCLES; // monitoring frozen procs
-   size_t   block_size       = BDEV_SECTOR_SIZE;  // disk block size
-   size_t   nb_procs         = 1;
-   size_t   x_size           = 2;
-   size_t   y_size           = 2;
-   size_t   nb_tty_channels  = 1;
-   size_t   nb_nic_channels  = 1;
+   const size_t block_size   = BDEV_SECTOR_SIZE;  // disk block size
+   const size_t x_size       = X_SIZE;
+   const size_t y_size       = Y_SIZE;
 
    assert((X_WIDTH == 4) and (Y_WIDTH == 4));
-      
+
    ////////////// command line arguments //////////////////////
-   if (argc > 1)
-   {
-      for (int n = 1; n < argc; n = n + 2)
-      {
-         if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
-         {
-            ncycles = atoi(argv[n+1]);
+   if (argc > 1) {
+      for (int n = 1; n < argc; n = n + 2) {
+         if ((strcmp(argv[n],"-NCYCLES") == 0) && ((n+1) < argc)) {
+            ncycles = strtoll(argv[n+1], NULL, 0);
             continue;
          }
-         if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
-         {
+         if ((strcmp(argv[n],"-SOFT") == 0) && ((n+1) < argc) ) {
             strcpy(soft_name, argv[n+1]);
             continue;
          }
-         if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
-         {
+         if ((strcmp(argv[n],"-DISK") == 0) && ((n+1) < argc) ) {
             strcpy(disk_name, argv[n+1]);
             continue;
          }
-         if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc))
-         {
-            nb_procs = atoi(argv[n+1]);
-            assert((nb_procs > 0) && (nb_procs < 5));
+         if ((strcmp(argv[n],"-DEBUG") == 0) && ((n+1) < argc) ) {
+            debug_ok   = true;
+            debug_from = strtol(argv[n+1], NULL, 0);
             continue;
          }
-         if ((strcmp(argv[n],"-XSIZE") == 0) && (n+1<argc))
-         {
-            x_size = atoi(argv[n+1]);
-            assert((x_size > 0) && (x_size < X_MAX));
-            continue;
-         }
-         if ((strcmp(argv[n],"-YSIZE") == 0) && (n+1<argc))
-         {
-            y_size = atoi(argv[n+1]);
-            assert((y_size > 0) && (y_size < Y_MAX));
-            continue;
-         }
-         if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
-         {
-            debug_ok   = true;
-            debug_from = atoi(argv[n+1]);
-            continue;
-         }
-         if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
-         {
-            debug_memc_id = atoi(argv[n+1]);
+         if ((strcmp(argv[n],"-MEMCID") == 0) && ((n+1) < argc) ) {
+            debug_memc_id = strtol(argv[n+1], NULL, 0);
             size_t x = debug_memc_id >> Y_WIDTH;
             size_t y = debug_memc_id  & ((1 << Y_WIDTH) - 1);
@@ -420 +307 @@
             continue;
          }
-         if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) )
-         {
-            debug_iob = (atoi(argv[n+1]) != 0) ? 1 : 0;
+         if ((strcmp(argv[n],"-IOB") == 0) && ((n+1) < argc) ) {
+            debug_iob = (strtol(argv[n+1], NULL, 0) != 0) ? 1 : 0;
             continue;
          }
-         if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
-         {
-            debug_proc_id     = atoi(argv[n+1]);
-            size_t cluster_xy = debug_proc_id / nb_procs ;
+         if ((strcmp(argv[n],"-PROCID") == 0) && ((n+1) < argc) ) {
+            debug_proc_id     = strtol(argv[n+1], NULL, 0);
+            size_t cluster_xy = debug_proc_id / NB_PROCS ;
             size_t x          = cluster_xy >> Y_WIDTH;
             size_t y          = cluster_xy  & ((1 << Y_WIDTH) - 1);
@@ -434 +319 @@
             continue;
          }
-         if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
-         {
-            threads_nr = atoi(argv[n+1]);
+         if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) {
+            threads_nr = strtol(argv[n+1], NULL, 0);
             assert(threads_nr > 0);
             continue;
          }
-         if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
-         {
-            frozen_cycles = atoi(argv[n+1]);
+         if ((strcmp(argv[n], "-FROZEN") == 0) && ((n+1) < argc)) {
+            frozen_cycles = strtol(argv[n+1], NULL, 0);
             assert(frozen_cycles > 0);
             continue;
          }
-         if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
-         {
-            debug_period = atoi(argv[n+1]);
+         if ((strcmp(argv[n], "-PERIOD") == 0) && ((n+1) < argc)) {
+            debug_period = strtol(argv[n+1], NULL, 0);
             assert(debug_period > 0);
             continue;
@@ -454 +336 @@
 
          std::cout << "   Arguments are (key,value) couples.\n"
-                   << "   The order is not important.\n"
-                   << "   Accepted arguments are :\n\n"
-                   << "     -NCYCLES number of simulated_cycles\n"
-                   << "     -SOFT    pathname for embedded soft\n"
-                   << "     -DISK    pathname for disk image\n"
-                   << "     -NPROCS  number of processors per cluster\n"
-                   << "     -XSIZE   number of clusters on X\n"
-                   << "     -YSIZE   number of clusters on Y\n"
-                   << "     -DEBUG   debug start cycle\n"
-                   << "     -MEMCID  index of memc to trace\n"
-                   << "     -IOB     debug IOBs if non_zero_value\n\n"
-                   << "     -PROCID  index of proc to trace\n"
-                   << "     -THREADS simulator's threads number\n"
-                   << "     -FROZEN  max number of frozen cycles\n"
-                   << "     -PERIOD  number of cycles between trace\n\n";
+            << "   The order is not important.\n"
+            << "   Accepted arguments are :\n\n"
+            << "     -NCYCLES number of simulated_cycles\n"
+            << "     -SOFT    pathname for embedded soft\n"
+            << "     -DISK    pathname for disk image\n"
+            << "     -DEBUG   debug start cycle\n"
+            << "     -MEMCID  index of memc to trace\n"
+            << "     -IOB     debug IOBs if non_zero_value\n\n"
+            << "     -PROCID  index of proc to trace\n"
+            << "     -THREADS simulator's threads number\n"
+            << "     -FROZEN  max number of frozen cycles\n"
+            << "     -PERIOD  number of cycles between trace\n\n";
          exit(0);
       }
    }
 
-   // one DMA channel per proc
-   size_t nb_dma_channels = nb_procs;
-
-   // clusters containing IOB0 and IOB1
-   size_t cluster_iob0 = cluster(0,0);
-   size_t cluster_iob1 = cluster(x_size - 1, y_size - 1);
-
-   assert( (nb_tty_channels < 16) and
-           "The NB_TTY_CHANNELS parameter must be smaller than 16" );
-
-   assert( (nb_nic_channels == 1) and
-           "The NB_NIC_CHANNELS parameter must be 1" );
+   assert( (NB_TTY_CHANNELS < 16) and
+         "The NB_TTY_CHANNELS parameter must be smaller than 16" );
+
+   assert( (NB_NIC_CHANNELS == 1) and
+         "The NB_NIC_CHANNELS parameter must be 1" );
 
    std::cout << std::endl;
    std::cout << " - X_SIZE          = " << x_size          << std::endl;
    std::cout << " - Y_SIZE          = " << y_size          << std::endl;
-   std::cout << " - NB_PROCS        = " << nb_procs        << std::endl;
-   std::cout << " - NB_DMA_CHANNELS = " << nb_dma_channels << std::endl;
-   std::cout << " - NB_TTY_CHANNELS = " << nb_tty_channels << std::endl;
-   std::cout << " - NB_NIC_CHANNELS = " << nb_nic_channels << std::endl;
+   std::cout << " - NB_PROCS        = " << NB_PROCS        << std::endl;
+   std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
+   std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
+   std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
    std::cout << " - MEMC_WAYS       = " << MEMC_WAYS       << std::endl;
    std::cout << " - MEMC_SETS       = " << MEMC_SETS       << std::endl;
@@ -508 +380 @@
    // Define VciParams objects
    typedef soclib::caba::VciParams<vci_cell_width_int,
-                                   vci_plen_width,
-                                   vci_address_width,
-                                   vci_rerror_width,
-                                   vci_clen_width,
-                                   vci_rflag_width,
-                                   vci_srcid_width,
-                                   vci_pktid_width,
-                                   vci_trdid_width,
-                                   vci_wrplen_width> vci_param_int;
+           vci_plen_width,
+           vci_address_width,
+           vci_rerror_width,
+           vci_clen_width,
+           vci_rflag_width,
+           vci_srcid_width,
+           vci_pktid_width,
+           vci_trdid_width,
+           vci_wrplen_width> vci_param_int;
 
    typedef soclib::caba::VciParams<vci_cell_width_ext,
-                                   vci_plen_width,
-                                   vci_address_width,
-                                   vci_rerror_width,
-                                   vci_clen_width,
-                                   vci_rflag_width,
-                                   vci_srcid_width,
-                                   vci_pktid_width,
-                                   vci_trdid_width,
-                                   vci_wrplen_width> vci_param_ext;
+           vci_plen_width,
+           vci_address_width,
+           vci_rerror_width,
+           vci_clen_width,
+           vci_rflag_width,
+           vci_srcid_width,
+           vci_pktid_width,
+           vci_trdid_width,
+           vci_wrplen_width> vci_param_ext;
+
+   // Clusters
+   typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width,
+           dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width>
+              TsarIobClusterType;
+
+   // clusters containing IOB0 and IOB1
+   size_t cluster_iob0 = cluster(0, 0);
+   size_t cluster_iob1 = cluster(x_size - 1, y_size - 1);
 
    /////////////////////////////////////////////////////////////////////
@@ -539 +420 @@
          vci_address_width,
          IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
-         IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
+         IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH),
          0x00FF000000);
 
-   for (size_t x = 0; x < x_size; x++)
-   {
-      for (size_t y = 0; y < y_size; y++)
-      {
+   for (size_t x = 0; x < x_size; x++) {
+      for (size_t y = 0; y < y_size; y++) {
          uint64_t offset = ((uint64_t)cluster(x,y))
             << (vci_address_width - X_WIDTH - Y_WIDTH);
-         bool config    = true;
-         bool cacheable = true;
+         const bool config    = true;
+         const bool cacheable = true;
 
          // the five following segments are defined in all clusters
@@ -556 +435 @@
          smemc_conf << "int_seg_memc_conf_" << x << "_" << y;
          maptab_int.add(Segment(smemc_conf.str(), MEMC_BASE+offset, MEMC_SIZE,
-                                IntTab(cluster(x,y),INT_MEMC_TGT_ID),
-                                not cacheable, config ));
+                  IntTab(cluster(x,y),INT_MEMC_TGT_ID),
+                  not cacheable, config ));
 
          std::ostringstream smemc_xram;
          smemc_xram << "int_seg_memc_xram_" << x << "_" << y;
          maptab_int.add(Segment(smemc_xram.str(), XRAM_BASE+offset, XRAM_SIZE,
-                                IntTab(cluster(x,y),INT_MEMC_TGT_ID),
-                                cacheable));
+                  IntTab(cluster(x,y),INT_MEMC_TGT_ID),
+                  cacheable));
 
          std::ostringstream sxicu;
          sxicu << "int_seg_xicu_" << x << "_" << y;
          maptab_int.add(Segment(sxicu.str(), XICU_BASE+offset, XICU_SIZE,
-                                IntTab(cluster(x,y),INT_XICU_TGT_ID),
-                                not cacheable));
+                  IntTab(cluster(x,y),INT_XICU_TGT_ID),
+                  not cacheable));
 
          std::ostringstream sbrom;
          sbrom << "int_seg_brom_" << x << "_" << y;
          maptab_int.add(Segment(sbrom.str(), BROM_BASE+offset, BROM_SIZE,
-                                IntTab(cluster(x,y),INT_BROM_TGT_ID),
-                                cacheable));
+                  IntTab(cluster(x,y),INT_BROM_TGT_ID),
+                  cacheable));
+
+         std::ostringstream smtty;
+         smtty << "int_seg_mtty_" << x << "_" << y;
+         maptab_int.add(Segment(smtty.str(), MTTY_BASE+offset, MTTY_SIZE,
+                  IntTab(cluster(x,y),INT_MTTY_TGT_ID),
+                  not cacheable));
 
          std::ostringstream smdma;
          smdma << "int_seg_mdma_" << x << "_" << y;
          maptab_int.add(Segment(smdma.str(), MDMA_BASE+offset, MDMA_SIZE,
-                                IntTab(cluster(x,y),INT_MDMA_TGT_ID),
-                                not cacheable));
+                  IntTab(cluster(x,y),INT_MDMA_TGT_ID),
+                  not cacheable));
 
          // the following segments are only defined in cluster_iob0 or in
          // cluster_iob1
-         if ((cluster(x,y) == cluster_iob0) || (cluster(x,y) == cluster_iob1))
-         {
+         if ((cluster(x,y) == cluster_iob0) ||
+             (cluster(x,y) == cluster_iob1)) {
             std::ostringstream siobx;
             siobx << "int_seg_iobx_" << x << "_" << y;
             maptab_int.add(Segment(siobx.str(), IOBX_BASE+offset, IOBX_SIZE,
-                                   IntTab(cluster(x,y), INT_IOBX_TGT_ID),
-                                   not cacheable, config ));
+                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
+                     not cacheable, config ));
 
             std::ostringstream stty;
             stty << "int_seg_mtty_" << x << "_" << y;
-            maptab_int.add(Segment(stty.str(), MTTY_BASE+offset, MTTY_SIZE,
-                                   IntTab(cluster(x,y), INT_IOBX_TGT_ID),
-                                   not cacheable));
+            maptab_int.add(Segment(stty.str(), XTTY_BASE+offset, XTTY_SIZE,
+                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
+                     not cacheable));
 
             std::ostringstream sfbf;
             sfbf << "int_seg_fbuf_" << x << "_" << y;
             maptab_int.add(Segment(sfbf.str(), FBUF_BASE+offset, FBUF_SIZE,
-                                   IntTab(cluster(x,y), INT_IOBX_TGT_ID),
-                                   not cacheable));
+                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
+                     not cacheable));
 
             std::ostringstream sbdv;
             sbdv << "int_seg_bdev_" << x << "_" << y;
             maptab_int.add(Segment(sbdv.str(), BDEV_BASE+offset, BDEV_SIZE,
-                                   IntTab(cluster(x,y), INT_IOBX_TGT_ID),
-                                   not cacheable));
+                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
+                     not cacheable));
 
             std::ostringstream snic;
             snic << "int_seg_mnic_" << x << "_" << y;
             maptab_int.add(Segment(snic.str(), MNIC_BASE+offset, MNIC_SIZE,
-                                   IntTab(cluster(x,y), INT_IOBX_TGT_ID),
-                                   not cacheable));
+                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
+                     not cacheable));
 
             std::ostringstream sdma;
             sdma << "int_seg_cdma_" << x << "_" << y;
             maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE,
-                                   IntTab(cluster(x,y), INT_IOBX_TGT_ID),
-                                   not cacheable));
+                     IntTab(cluster(x,y), INT_IOBX_TGT_ID),
+                     not cacheable));
          }
 
@@ -628 +513 @@
 
          maptab_int.srcid_map(IntTab(cluster(x,y), MDMA_LOCAL_SRCID),
-                              IntTab(cluster(x,y), INT_MDMA_INI_ID));
+               IntTab(cluster(x,y), INT_MDMA_INI_ID));
          maptab_int.srcid_map(IntTab(cluster(x,y), IOBX_LOCAL_SRCID),
-                              IntTab(cluster(x,y), INT_IOBX_INI_ID));
-
-         for ( size_t p = 0 ; p < nb_procs ; p++ )
-         {
+               IntTab(cluster(x,y), INT_IOBX_INI_ID));
+
+         for ( size_t p = 0 ; p < NB_PROCS ; p++ ) {
             maptab_int.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p),
-                                 IntTab(cluster(x,y), INT_PROC_INI_ID  + p));
+                  IntTab(cluster(x,y), INT_PROC_INI_ID  + p));
          }
       }
@@ -641 +525 @@
    std::cout << "INT network " << maptab_int << std::endl;
 
-    /////////////////////////////////////////////////////////////////////////
-    // RAM network mapping table
-    // - two levels address decoding for commands
-    // - two levels srcid decoding for responses
-    // - 2 local initiators (MEMC, IOBX) per cluster
-    //   (IOBX component only in cluster_iob0 and cluster_iob1)
-    // - 1 local target (XRAM) per cluster
-    ////////////////////////////////////////////////////////////////////////
-    MappingTable maptab_ram(
-          vci_address_width,
-          IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
-          IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
-          0x00FF000000);
-
-    for (size_t x = 0; x < x_size; x++)
-    {
-        for (size_t y = 0; y < y_size ; y++)
-        {
-           uint64_t offset = ((uint64_t)cluster(x,y))
-              << (vci_address_width - X_WIDTH - Y_WIDTH);
-
-            std::ostringstream sxram;
-            sxram << "ext_seg_xram_" << x << "_" << y;
-            maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset,
-                                   XRAM_SIZE, IntTab(cluster(x,y), 0), false));
-        }
-    }
-
-    // This define the mapping between the initiators SRCID
-    // and the port index on the RAM local interconnect.
-    // External initiator have two alias SRCID (iob0 / iob1)
-
-    maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
-                         IntTab(cluster_iob0, RAM_IOBX_INI_ID));
-    maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
-                         IntTab(cluster_iob1, RAM_IOBX_INI_ID));
-    maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
-                         IntTab(cluster_iob0, RAM_IOBX_INI_ID));
-    maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
-                         IntTab(cluster_iob1, RAM_IOBX_INI_ID));
-    maptab_ram.srcid_map(IntTab(cluster_iob1, MEMC_LOCAL_SRCID),
-                         IntTab(cluster_iob1, RAM_MEMC_INI_ID));
-
-    std::cout << "RAM network " << maptab_ram << std::endl;
-
-    ///////////////////////////////////////////////////////////////////////
-    // IOX network mapping table
-    // - two levels address decoding for commands
-    // - two levels srcid decoding for responses
-    // - 4 initiators (IOB0, IOB1, BDEV, CDMA)
-    // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC)
-    ///////////////////////////////////////////////////////////////////////
-    MappingTable maptab_iox(
-          vci_address_width,
-          IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
-          IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
-          0x00FF000000);
-
-    // compute base addresses for cluster_iob0 and cluster_iob1
-    uint64_t iob0_base = ((uint64_t)cluster_iob0)
-       << (vci_address_width - X_WIDTH - Y_WIDTH);
-    uint64_t iob1_base = ((uint64_t)cluster_iob1)
-       << (vci_address_width - X_WIDTH - Y_WIDTH);
-
-    // Each peripheral can be accessed through two segments,
-    // depending on the used IOB (IOB0 or IOB1).
-    maptab_iox.add(Segment("iox_seg_mtty_0", MTTY_BASE + iob0_base, MTTY_SIZE,
-                           IntTab(cluster_iob0, IOX_MTTY_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE,
-                           IntTab(cluster_iob1, IOX_MTTY_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE,
-                           IntTab(cluster_iob0, IOX_FBUF_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE,
-                           IntTab(cluster_iob1, IOX_FBUF_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE,
-                           IntTab(cluster_iob0, IOX_BDEV_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE,
-                           IntTab(cluster_iob1, IOX_BDEV_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE,
-                           IntTab(cluster_iob0, IOX_MNIC_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE,
-                           IntTab(cluster_iob1, IOX_MNIC_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE,
-                           IntTab(cluster_iob0, IOX_CDMA_TGT_ID), false));
-    maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE,
-                           IntTab(cluster_iob1, IOX_CDMA_TGT_ID), false));
-
-    // Each physical RAM can be accessed through IOB0, or through IOB1.
-    // if IOMMU is not activated, addresses are 40 bits (physical addresses),
-    // and the choice depends on on address bit A[39].
-    // if IOMMU is activated the addresses use only 32 bits (virtual
-    // addresses), and the choice depends on address bit A[31].
-    for (size_t x = 0; x < x_size; x++)
-    {
-        for (size_t y = 0; y < y_size ; y++)
-        {
-            uint64_t offset = ((uint64_t)cluster(x,y))
-               << (vci_address_width - X_WIDTH - Y_WIDTH);
-
-            // send command to XRAM through IOB0
-            if ( x < (x_size/2) )
-            {
-                std::ostringstream siob0;
-                siob0 << "iox_seg_xram_" << x << "_" << y;
-                maptab_iox.add(Segment(siob0.str(), offset, 0x80000000,
-                                       IntTab(cluster_iob0,IOX_IOB0_TGT_ID),
-                                       false));
-            }
-            // send command to XRAM through IOB1
-            else
-            {
-                std::ostringstream siob1;
-                siob1 << "iox_seg_xram_" << x << "_" << y;
-                maptab_iox.add(Segment(siob1.str(), offset, 0x80000000,
-                                       IntTab(cluster_iob1,IOX_IOB1_TGT_ID),
-                                       false));
-            }
-        }
-    }
-    // useful when IOMMU activated
-    maptab_iox.add(Segment("iox_seg_xram", 0xc0000000, 0x40000000,
-                           IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false));
-
-    // This define the mapping between the initiators (identified by the SRCID)
-    // and the port index on the IOX local interconnect.
-    // External initiator have two alias SRCID (iob0 / iob1 access)
-
-    maptab_iox.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
-                         IntTab(cluster_iob0, IOX_CDMA_INI_ID));
-    maptab_iox.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
-                         IntTab(cluster_iob1, IOX_CDMA_INI_ID));
-    maptab_iox.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
-                         IntTab(cluster_iob0, IOX_BDEV_INI_ID));
-    maptab_iox.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
-                         IntTab(cluster_iob0, IOX_BDEV_INI_ID));
-
-    for (size_t x = 0; x < x_size; x++)
-    {
-        for (size_t y = 0; y < y_size ; y++)
-        {
-            size_t iob = (x < (x_size / 2)) ? IOX_IOB0_INI_ID
-                                            : IOX_IOB1_INI_ID;
-
-            for (size_t p = 0 ; p < nb_procs ; p++)
-            {
-               maptab_iox.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p),
-                                    IntTab(cluster(x,y), iob));
-            }
-            maptab_iox.srcid_map(IntTab( cluster(x,y), MDMA_LOCAL_SRCID),
-                                 IntTab( cluster(x,y), IOX_IOB0_INI_ID));
-        }
-    }
-
-    std::cout << "IOX network " << maptab_iox << std::endl;
-
-    ////////////////////
-    // Signals
-    ////////////////////
-
-    sc_clock        signal_clk("clk");
-    sc_signal<bool> signal_resetn("resetn");
-
-    sc_signal<bool> signal_irq_false;
-    sc_signal<bool> signal_irq_bdev;
-    sc_signal<bool> signal_irq_mnic_rx[1];
-    sc_signal<bool> signal_irq_mnic_tx[1];
-    sc_signal<bool> signal_irq_mtty[16];
-    sc_signal<bool> signal_irq_cdma[1*2];
-
-    // DSPIN signals for loopback in cluster_iob0 & cluster_iob1
-    DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback;
-    DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback;
-    DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback;
-    DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback;
-
-    // VCI signals for IOX network
-    VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0");
-    VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1");
-    VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev");
-    VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma");
-
-    VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0");
-    VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1");
-    VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
-    VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
-    VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
-    VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
-    VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
+   /////////////////////////////////////////////////////////////////////////
+   // RAM network mapping table
+   // - two levels address decoding for commands
+   // - two levels srcid decoding for responses
+   // - 2 local initiators (MEMC, IOBX) per cluster
+   //   (IOBX component only in cluster_iob0 and cluster_iob1)
+   // - 1 local target (XRAM) per cluster
+   ////////////////////////////////////////////////////////////////////////
+   MappingTable maptab_ram(
+         vci_address_width,
+         IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
+         IntTab(X_WIDTH + Y_WIDTH, vci_param_int::S - X_WIDTH - Y_WIDTH),
+         0x00FF000000);
+
+   for (size_t x = 0; x < x_size; x++) {
+      for (size_t y = 0; y < y_size ; y++) {
+         uint64_t offset = ((uint64_t)cluster(x,y))
+            << (vci_address_width - X_WIDTH - Y_WIDTH);
+
+         std::ostringstream sxram;
+         sxram << "ext_seg_xram_" << x << "_" << y;
+         maptab_ram.add(Segment(sxram.str(), XRAM_BASE+offset, XRAM_SIZE,
+                  IntTab(cluster(x,y), 0), false));
+      }
+   }
+
+   // This define the mapping between the initiators SRCID
+   // and the port index on the RAM local interconnect.
+   // External initiator have two alias SRCID (iob0 / iob1)
+
+   maptab_ram.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
+         IntTab(cluster_iob0, RAM_IOBX_INI_ID));
+   maptab_ram.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
+         IntTab(cluster_iob1, RAM_IOBX_INI_ID));
+   maptab_ram.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
+         IntTab(cluster_iob0, RAM_IOBX_INI_ID));
+   maptab_ram.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
+         IntTab(cluster_iob1, RAM_IOBX_INI_ID));
+   maptab_ram.srcid_map(IntTab(cluster_iob1, MEMC_LOCAL_SRCID),
+         IntTab(cluster_iob1, RAM_MEMC_INI_ID));
+
+   std::cout << "RAM network " << maptab_ram << std::endl;
+
+   ///////////////////////////////////////////////////////////////////////
+   // IOX network mapping table
+   // - two levels address decoding for commands
+   // - two levels srcid decoding for responses
+   // - 4 initiators (IOB0, IOB1, BDEV, CDMA)
+   // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC)
+   ///////////////////////////////////////////////////////////////////////
+   MappingTable maptab_iox(
+         vci_address_width,
+         IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
+         IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
+         0x00FF000000);
+
+   // compute base addresses for cluster_iob0 and cluster_iob1
+   uint64_t iob0_base = ((uint64_t)cluster_iob0)
+      << (vci_address_width - X_WIDTH - Y_WIDTH);
+   uint64_t iob1_base = ((uint64_t)cluster_iob1)
+      << (vci_address_width - X_WIDTH - Y_WIDTH);
+
+   // Each peripheral can be accessed through two segments,
+   // depending on the used IOB (IOB0 or IOB1).
+   maptab_iox.add(Segment("iox_seg_mtty_0", XTTY_BASE + iob0_base, XTTY_SIZE,
+            IntTab(cluster_iob0, IOX_MTTY_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_mtty_1", XTTY_BASE + iob1_base, XTTY_SIZE,
+            IntTab(cluster_iob1, IOX_MTTY_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE,
+            IntTab(cluster_iob0, IOX_FBUF_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE,
+            IntTab(cluster_iob1, IOX_FBUF_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE,
+            IntTab(cluster_iob0, IOX_BDEV_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE,
+            IntTab(cluster_iob1, IOX_BDEV_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE,
+            IntTab(cluster_iob0, IOX_MNIC_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE,
+            IntTab(cluster_iob1, IOX_MNIC_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE,
+            IntTab(cluster_iob0, IOX_CDMA_TGT_ID), false));
+   maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE,
+            IntTab(cluster_iob1, IOX_CDMA_TGT_ID), false));
+
+   // Each physical RAM can be accessed through IOB0, or through IOB1.
+   // if IOMMU is not activated, addresses are 40 bits (physical addresses),
+   // and the choice depends on on address bit A[39].
+   // if IOMMU is activated the addresses use only 32 bits (virtual
+   // addresses), and the choice depends on address bit A[31].
+   for (size_t x = 0; x < x_size; x++) {
+      for (size_t y = 0; y < y_size ; y++) {
+         uint64_t offset = static_cast<uint64_t>(cluster(x,y))
+            << (vci_address_width - X_WIDTH - Y_WIDTH);
+
+         // send command to XRAM through IOB0
+         if ( x < (x_size/2) ) {
+            std::ostringstream siob0;
+            siob0 << "iox_seg_xram_" << x << "_" << y;
+            maptab_iox.add(Segment(siob0.str(),
+                     XRAM_BASE + offset, XRAM_SIZE,
+                     IntTab(cluster_iob0,IOX_IOB0_TGT_ID),
+                     false));
+         }
+         // send command to XRAM through IOB1
+         else {
+            std::ostringstream siob1;
+            siob1 << "iox_seg_xram_" << x << "_" << y;
+            maptab_iox.add(Segment(siob1.str(),
+                     XRAM_BASE + offset, XRAM_SIZE,
+                     IntTab(cluster_iob1,IOX_IOB1_TGT_ID),
+                     false));
+         }
+      }
+   }
+   // useful when IOMMU activated
+   //maptab_iox.add(Segment("iox_seg_xram", 0xc0000000, 0x40000000,
+   //                       IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false));
+
+   // This define the mapping between the initiators (identified by the SRCID)
+   // and the port index on the IOX local interconnect.
+   // External initiator have two alias SRCID (iob0 / iob1 access)
+
+   maptab_iox.srcid_map(IntTab(cluster_iob0, CDMA_LOCAL_SRCID),
+         IntTab(cluster_iob0, IOX_CDMA_INI_ID));
+   maptab_iox.srcid_map(IntTab(cluster_iob1, CDMA_LOCAL_SRCID),
+         IntTab(cluster_iob1, IOX_CDMA_INI_ID));
+   maptab_iox.srcid_map(IntTab(cluster_iob0, BDEV_LOCAL_SRCID),
+         IntTab(cluster_iob0, IOX_BDEV_INI_ID));
+   maptab_iox.srcid_map(IntTab(cluster_iob1, BDEV_LOCAL_SRCID),
+         IntTab(cluster_iob0, IOX_BDEV_INI_ID));
+
+   for (size_t x = 0; x < x_size; x++) {
+      for (size_t y = 0; y < y_size ; y++) {
+         size_t iob = (x < (x_size / 2)) ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID;
+
+         for (size_t p = 0 ; p < NB_PROCS ; p++) {
+            maptab_iox.srcid_map(IntTab(cluster(x,y), PROC_LOCAL_SRCID + p),
+                  IntTab(cluster(x,y), iob));
+         }
+         maptab_iox.srcid_map(IntTab( cluster(x,y), MDMA_LOCAL_SRCID),
+               IntTab( cluster(x,y), IOX_IOB0_INI_ID));
+      }
+   }
+
+   std::cout << "IOX network " << maptab_iox << std::endl;
+
+   ////////////////////
+   // Signals
+   ////////////////////
+
+   sc_clock        signal_clk("clk");
+   sc_signal<bool> signal_resetn("resetn");
+
+   sc_signal<bool> signal_irq_false;
+   sc_signal<bool> signal_irq_bdev;
+   sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
+   sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
+   sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS];
+   sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2];
+
+   // DSPIN signals for loopback in cluster_iob0 & cluster_iob1
+   DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob0_loopback;
+   DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob0_loopback;
+   DspinSignals<dspin_ram_cmd_width> signal_dspin_cmd_iob1_loopback;
+   DspinSignals<dspin_ram_rsp_width> signal_dspin_rsp_iob1_loopback;
+
+   // VCI signals for IOX network
+   VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0");
+   VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1");
+   VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev");
+   VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma");
+
+   VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0");
+   VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1");
+   VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
+   VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
+   VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
+   VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
+   VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
 
    // Horizontal inter-clusters INT network DSPIN
@@ -919 +795 @@
    ////////////////////////////
 
-#if USE_ALMOS
-   soclib::common::Loader loader(almos_bootloader_pathname,
-                                 almos_archinfo_pathname,
-                                 almos_kernel_pathname);
-#else
    soclib::common::Loader loader(soft_name);
-#endif
 
    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
@@ -935 +805 @@
 
    std::cout << std::endl << "External Bus and Peripherals" << std::endl
-             << std::endl;
+      << std::endl;
 
    // IOX network
    VciIoxNetwork<vci_param_ext>* iox_network;
    iox_network = new VciIoxNetwork<vci_param_ext>("iox_network",
-                                                  maptab_iox,
-                                                  7,   // number of targets
-                                                  4 ); // number of initiators
+         maptab_iox,
+         7,   // number of targets
+         4 ); // number of initiators
 
    // Network Controller
    VciMultiNic<vci_param_ext>*  mnic;
    mnic = new VciMultiNic<vci_param_ext>("mnic",
-                                         IntTab(0, IOX_MNIC_TGT_ID),
-                                         maptab_iox,
-                                         nb_nic_channels,
-                                         0,           // mac_4 address
-                                         0,           // mac_2 address
-                                         nic_rx_name,
-                                         nic_tx_name);
+         IntTab(0, IOX_MNIC_TGT_ID),
+         maptab_iox,
+         NB_NIC_CHANNELS,
+         0,           // mac_4 address
+         0,           // mac_2 address
+         nic_rx_name,
+         nic_tx_name);
 
    // Frame Buffer
    VciFrameBuffer<vci_param_ext>*  fbuf;
    fbuf = new VciFrameBuffer<vci_param_ext>("fbuf",
-                                            IntTab(0, IOX_FBUF_TGT_ID),
-                                            maptab_iox,
-                                            FBUF_X_SIZE, FBUF_Y_SIZE );
+         IntTab(0, IOX_FBUF_TGT_ID),
+         maptab_iox,
+         FBUF_X_SIZE, FBUF_Y_SIZE );
 
    // Block Device
@@ -968 +838 @@
    VciBlockDeviceTsar<vci_param_ext>*  bdev;
    bdev = new VciBlockDeviceTsar<vci_param_ext>("bdev",
-                                                maptab_iox,
-                                                IntTab(0, BDEV_LOCAL_SRCID),
-                                                IntTab(0, IOX_BDEV_TGT_ID),
-                                                disk_name,
-                                                block_size,
-                                                64,  // burst size (bytes)
-                                                0 ); // disk latency
+         maptab_iox,
+         IntTab(0, BDEV_LOCAL_SRCID),
+         IntTab(0, IOX_BDEV_TGT_ID),
+         disk_name,
+         block_size,
+         64,  // burst size (bytes)
+         0 ); // disk latency
 
    // Chained Buffer DMA controller
    VciChbufDma<vci_param_ext>*  cdma;
    cdma = new VciChbufDma<vci_param_ext>("cdma",
-                                         maptab_iox,
-                                         IntTab(0, CDMA_LOCAL_SRCID),
-                                         IntTab(0, IOX_CDMA_TGT_ID),
-                                         64,  // burst size (bytes)
-                                         2 * nb_nic_channels);
+         maptab_iox,
+         IntTab(0, CDMA_LOCAL_SRCID),
+         IntTab(0, IOX_CDMA_TGT_ID),
+         64,  // burst size (bytes)
+         2 * NB_NIC_CHANNELS);
    // Multi-TTY controller
    std::vector<std::string> vect_names;
-   for( size_t tid = 0 ; tid < nb_tty_channels ; tid++ )
+   for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ )
    {
       std::ostringstream term_name;
-      term_name <<  "term" << tid;
+      term_name <<  "mtty_iox_" << tid;
       vect_names.push_back(term_name.str().c_str());
    }
    VciMultiTty<vci_param_ext>*  mtty;
    mtty = new VciMultiTty<vci_param_ext>("mtty_iox",
-                                         IntTab(0, IOX_MTTY_TGT_ID),
-                                         maptab_iox,
-                                         vect_names);
-   // Clusters
-   typedef TsarIobCluster<vci_param_int, vci_param_ext, dspin_int_cmd_width,
-           dspin_int_rsp_width, dspin_ram_cmd_width, dspin_ram_rsp_width>
-           TsarIobClusterType;
-   
+         IntTab(0, IOX_MTTY_TGT_ID),
+         maptab_iox,
+         vect_names);
+
    TsarIobClusterType* clusters[x_size][y_size];
 
 #if USE_OPENMP
 #pragma omp parallel
-    {
+   {
 #pragma omp for
 #endif
 
-        for(size_t i = 0; i  < (x_size * y_size); i++)
-        {
-            size_t x = i / y_size;
-            size_t y = i % y_size;
+      for(size_t i = 0; i  < (x_size * y_size); i++) {
+         size_t x = i / y_size;
+         size_t y = i % y_size;
 
 #if USE_OPENMP
 #pragma omp critical
-            {
+         {
 #endif
             std::cout << std::endl;
@@ -1029 +894 @@
                debug_ok && (cluster(x,y) == debug_memc_id);
             bool proc_debug = 
-               debug_ok && (cluster(x,y) == (debug_proc_id / nb_procs));
+               debug_ok && (cluster(x,y) == (debug_proc_id / NB_PROCS));
 
             TsarIobClusterType::ClusterParams params = {
                .insname           = sc.str().c_str(),
-               .nb_procs          = nb_procs,
-               .nb_dmas           = nb_dma_channels,
+
                .x_id              = x,
                .y_id              = y,
-               .x_size            = x_size,
-               .y_size            = y_size,
+
                .mt_int            = maptab_int,
                .mt_ext            = maptab_ram,
                .mt_iox            = maptab_iox,
-               .x_width           = X_WIDTH,
-               .y_width           = Y_WIDTH,
-               .l_width           = vci_srcid_width - X_WIDTH - Y_WIDTH,
-               .int_memc_tgtid    = INT_MEMC_TGT_ID,
-               .int_xicu_tgtid    = INT_XICU_TGT_ID,
-               .int_mdma_tgtid    = INT_MDMA_TGT_ID,
-               .int_iobx_tgtid    = INT_IOBX_TGT_ID,
-               .int_brom_tgtid    = INT_BROM_TGT_ID,
-               .int_proc_srcid    = INT_PROC_INI_ID,
-               .int_mdma_srcid    = INT_MDMA_INI_ID,
-               .int_iobx_srcid    = INT_IOBX_INI_ID,
-               .ext_xram_tgtid    = RAM_XRAM_TGT_ID,
-               .ext_memc_srcid    = RAM_MEMC_INI_ID,
-               .ext_iobx_srcid    = RAM_IOBX_INI_ID,
+
                .memc_ways         = MEMC_WAYS,
                .memc_sets         = MEMC_SETS,
@@ -1063 +913 @@
                .l1_d_sets         = L1_DSETS,
                .xram_latency      = XRAM_LATENCY,
+
                .loader            = loader,
+
                .frozen_cycles     = frozen_cycles,
                .debug_start_cycle = debug_from,
@@ -1074 +926 @@
 
 #if USE_OPENMP
-            } // end critical
+         } // end critical
 #endif
-        } // end for
+      } // end for
 #if USE_OPENMP
-    }
+   }
 #endif
 
-    std::cout << std::endl;
-
-    ///////////////////////////////////////////////////////////////////////////
-    //     Net-list
-    ///////////////////////////////////////////////////////////////////////////
-
-    // IOX network connexion
-    iox_network->p_clk                     (signal_clk);
-    iox_network->p_resetn                  (signal_resetn);
-    iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0);
-    iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1);
-    iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev);
-    iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma);
-    iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0);
-    iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1);
-    iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty);
-    iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf);
-    iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic);
-    iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev);
-    iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma);
-
-    // BDEV connexion
-    bdev->p_clk    (signal_clk);
-    bdev->p_resetn (signal_resetn);
-    bdev->p_irq    (signal_irq_bdev);
-
-    // For AHCI
-    // bdev->p_channel_irq[0]                             (signal_irq_bdev);
-
-    bdev->p_vci_target    (signal_vci_tgt_bdev);
-    bdev->p_vci_initiator (signal_vci_ini_bdev);
-
-    std::cout << "  - BDEV connected" << std::endl;
-
-    // FBUF connexion
-    fbuf->p_clk    (signal_clk);
-    fbuf->p_resetn (signal_resetn);
-    fbuf->p_vci    (signal_vci_tgt_fbuf);
-
-    std::cout << "  - FBUF connected" << std::endl;
-
-    // MNIC connexion
-    mnic->p_clk    (signal_clk);
-    mnic->p_resetn (signal_resetn);
-    mnic->p_vci    (signal_vci_tgt_mnic);
-    for ( size_t i=0 ; i<nb_nic_channels ; i++ )
-    {
-         mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
-         mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
-    }
-
-    std::cout << "  - MNIC connected" << std::endl;
-
-    // MTTY connexion
-    mtty->p_clk        (signal_clk);
-    mtty->p_resetn     (signal_resetn);
-    mtty->p_vci        (signal_vci_tgt_mtty);
-    for ( size_t i=0 ; i<nb_tty_channels ; i++ )
-    {
-        mtty->p_irq[i] (signal_irq_mtty[i]);
-    }
-
-    std::cout << "  - MTTY connected" << std::endl;
-
-    // CDMA connexion
-    cdma->p_clk           (signal_clk);
-    cdma->p_resetn        (signal_resetn);
-    cdma->p_vci_target    (signal_vci_tgt_cdma);
-    cdma->p_vci_initiator (signal_vci_ini_cdma);
-    for ( size_t i=0 ; i<(nb_nic_channels*2) ; i++)
-    {
-        cdma->p_irq[i]    (signal_irq_cdma[i]);
-    }
-
-    std::cout << "  - CDMA connected" << std::endl;
-
-    // IRQ connexions from external peripherals (cluster_iob0 only)
-    // IRQ_MNIC_RX  -> IRQ[08] to IRQ[09]
-    // IRQ_MNIC_TX  -> IRQ[10] to IRQ[11]
-    // IRQ_CDMA     -> IRQ[12] to IRQ[15]
-    // IRQ_MTTY     -> IRQ[16] to IRQ[30]
-    // IRQ_BDEV     -> IRQ[31]
-
-    size_t mx = 16 + nb_tty_channels;
-    for ( size_t n=0 ; n<32 ; n++ )
-    {
-        if      ( n < 8  ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
-        else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
-        else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
-        else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
-        else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]);
-        else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
-        else               (*clusters[0][0]->p_irq[n]) (signal_irq_bdev);
-    }
-
-    // IOB0 cluster connexion to IOX network
-    (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0);
-    (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0);
-
-    // IOB1 cluster connexion to IOX network
-    (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1);
-    (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1);
-
-    // All clusters Clock & RESET connexions
-    for ( size_t x = 0; x < (x_size); x++ )
-    {
-        for (size_t y = 0; y < y_size; y++)
-        {
-            clusters[x][y]->p_clk    (signal_clk);
-            clusters[x][y]->p_resetn (signal_resetn);
-        }
-    }
+   std::cout << std::endl;
+
+   ///////////////////////////////////////////////////////////////////////////
+   //     Net-list
+   ///////////////////////////////////////////////////////////////////////////
+
+   // IOX network connexion
+   iox_network->p_clk                     (signal_clk);
+   iox_network->p_resetn                  (signal_resetn);
+   iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0);
+   iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1);
+   iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev);
+   iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma);
+   iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0);
+   iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1);
+   iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty);
+   iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf);
+   iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic);
+   iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev);
+   iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma);
+
+   // BDEV connexion
+   bdev->p_clk    (signal_clk);
+   bdev->p_resetn (signal_resetn);
+   bdev->p_irq    (signal_irq_bdev);
+
+   // For AHCI
+   // bdev->p_channel_irq[0]                             (signal_irq_bdev);
+
+   bdev->p_vci_target    (signal_vci_tgt_bdev);
+   bdev->p_vci_initiator (signal_vci_ini_bdev);
+
+   std::cout << "  - BDEV connected" << std::endl;
+
+   // FBUF connexion
+   fbuf->p_clk    (signal_clk);
+   fbuf->p_resetn (signal_resetn);
+   fbuf->p_vci    (signal_vci_tgt_fbuf);
+
+   std::cout << "  - FBUF connected" << std::endl;
+
+   // MNIC connexion
+   mnic->p_clk    (signal_clk);
+   mnic->p_resetn (signal_resetn);
+   mnic->p_vci    (signal_vci_tgt_mnic);
+   for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
+   {
+      mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
+      mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
+   }
+
+   std::cout << "  - MNIC connected" << std::endl;
+
+   // MTTY connexion
+   mtty->p_clk        (signal_clk);
+   mtty->p_resetn     (signal_resetn);
+   mtty->p_vci        (signal_vci_tgt_mtty);
+   for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) {
+      mtty->p_irq[i] (signal_irq_mtty[i]);
+   }
+
+   std::cout << "  - MTTY connected" << std::endl;
+
+   // CDMA connexion
+   cdma->p_clk           (signal_clk);
+   cdma->p_resetn        (signal_resetn);
+   cdma->p_vci_target    (signal_vci_tgt_cdma);
+   cdma->p_vci_initiator (signal_vci_ini_cdma);
+   for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) {
+      cdma->p_irq[i]    (signal_irq_cdma[i]);
+   }
+
+   std::cout << "  - CDMA connected" << std::endl;
+
+   // IRQ connexions from external peripherals (cluster_iob0 only)
+   // IRQ_MNIC_RX  -> IRQ[08] to IRQ[09]
+   // IRQ_MNIC_TX  -> IRQ[10] to IRQ[11]
+   // IRQ_CDMA     -> IRQ[12] to IRQ[15]
+   // IRQ_MTTY     -> IRQ[16] to IRQ[30]
+   // IRQ_BDEV     -> IRQ[31]
+
+   size_t mx = 16 + NB_TTY_CHANNELS;
+   for ( size_t n=0 ; n<32 ; n++ ) {
+      if      ( n < 8  ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
+      else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
+      else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
+      else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
+      else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]);
+      else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false);
+      else               (*clusters[0][0]->p_irq[n]) (signal_irq_bdev);
+   }
+
+   // IOB0 cluster connexion to IOX network
+   (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0);
+   (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0);
+
+   // IOB1 cluster connexion to IOX network
+   (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1);
+   (*clusters[x_size-1][y_size-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1);
+
+   // All clusters Clock & RESET connexions
+   for ( size_t x = 0; x < (x_size); x++ ) {
+      for (size_t y = 0; y < y_size; y++) {
+         clusters[x][y]->p_clk    (signal_clk);
+         clusters[x][y]->p_resetn (signal_resetn);
+      }
+   }
 
    const int& NORTH = VirtualDspinRouter<dspin_int_cmd_width>::NORTH;
@@ -1200 +1047 @@
 
    // Inter Clusters horizontal connections
-   if (x_size > 1)
-   {
-      for (size_t x = 0; x < (x_size-1); x++)
-      {
-         for (size_t y = 0; y < y_size; y++)
-         {
-            for (size_t k = 0; k < 3; k++)
-            {
+   if (x_size > 1) {
+      for (size_t x = 0; x < (x_size-1); x++) {
+         for (size_t y = 0; y < y_size; y++) {
+            for (size_t k = 0; k < 3; k++) {
                clusters[x][y]->p_dspin_int_cmd_out[EAST][k](
                      signal_dspin_int_cmd_h_inc[x][y][k]);
@@ -1218 +1061 @@
             }
 
-            for (size_t k = 0; k < 2; k++)
-            {
+            for (size_t k = 0; k < 2; k++) {
                clusters[x][y]->p_dspin_int_rsp_out[EAST][k](
                      signal_dspin_int_rsp_h_inc[x][y][k]);
@@ -1251 +1093 @@
 
    std::cout << std::endl << "Horizontal connections established"
-             << std::endl;
+      << std::endl;
 
    // Inter Clusters vertical connections
-   if (y_size > 1)
-   {
-      for (size_t y = 0; y < (y_size-1); y++)
-      {
-         for (size_t x = 0; x < x_size; x++)
-         {
-            for (size_t k = 0; k < 3; k++)
-            {
+   if (y_size > 1) {
+      for (size_t y = 0; y < (y_size-1); y++) {
+         for (size_t x = 0; x < x_size; x++) {
+            for (size_t k = 0; k < 3; k++) {
                clusters[x][y]->p_dspin_int_cmd_out[NORTH][k](
                      signal_dspin_int_cmd_v_inc[x][y][k]);
@@ -1272 +1110 @@
             }
 
-            for (size_t k = 0; k < 2; k++)
-            {
+            for (size_t k = 0; k < 2; k++) {
                clusters[x][y]->p_dspin_int_rsp_out[NORTH][k](
                      signal_dspin_int_rsp_v_inc[x][y][k]);
@@ -1307 +1144 @@
 
    // East & West boundary cluster connections
-   for (size_t y = 0; y < y_size; y++)
-   {
-      for (size_t k = 0; k < 3; k++)
-      {
+   for (size_t y = 0; y < y_size; y++) {
+      for (size_t k = 0; k < 3; k++) {
          clusters[0][y]->p_dspin_int_cmd_in[WEST][k](
                signal_dspin_false_int_cmd_in[0][y][WEST][k]);
@@ -1321 +1156 @@
       }
 
-      for (size_t k = 0; k < 2; k++)
-      {
+      for (size_t k = 0; k < 2; k++) {
          clusters[0][y]->p_dspin_int_rsp_in[WEST][k](
                signal_dspin_false_int_rsp_in[0][y][WEST][k]);
@@ -1334 +1168 @@
 
       // handling IOB to RAM network connection in cluster_iob0
-      if( y == 0 )
-      {
+      if( y == 0 ) {
          (*clusters[0][0]->p_dspin_iob_cmd_out)(
                signal_dspin_cmd_iob0_loopback);
@@ -1349 +1182 @@
                signal_dspin_rsp_iob0_loopback);
       }
-      else
-      {
+      else {
          clusters[0][y]->p_dspin_ram_cmd_in[WEST](
                signal_dspin_false_ram_cmd_in[0][y][WEST]);
@@ -1362 +1194 @@
 
       // handling IOB to RAM network connection in cluster_iob1
-      if( y == y_size-1 )
-      {
+      if( y == y_size-1 ) {
          (*clusters[x_size-1][y_size-1]->p_dspin_iob_cmd_out)(
                signal_dspin_cmd_iob1_loopback);
@@ -1379 +1210 @@
                signal_dspin_rsp_iob1_loopback);
       }
-      else
-      {
+      else {
          clusters[x_size-1][y]->p_dspin_ram_cmd_in[EAST](
                signal_dspin_false_ram_cmd_in[x_size-1][y][EAST]);
@@ -1395 +1225 @@
 
    // North & South boundary clusters connections
-   for (size_t x = 0; x < x_size; x++)
-   {
-      for (size_t k = 0; k < 3; k++)
-      {
+   for (size_t x = 0; x < x_size; x++) {
+      for (size_t k = 0; k < 3; k++) {
          clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k](
                signal_dspin_false_int_cmd_in[x][0][SOUTH][k]);
@@ -1409 +1237 @@
       }
 
-      for (size_t k = 0; k < 2; k++)
-      {
+      for (size_t k = 0; k < 2; k++) {
          clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k](
                signal_dspin_false_int_rsp_in[x][0][SOUTH][k]);
@@ -1441 +1268 @@
 
    std::cout << "North & South boundaries established" << std::endl
-             << std::endl;
+      << std::endl;
 
    ////////////////////////////////////////////////////////
@@ -1454 +1281 @@
 
    // network boundaries signals
-   for (size_t x = 0; x < x_size ; x++)
-   {
-      for (size_t y = 0; y < y_size ; y++)
-      {
-         for (size_t a = 0; a < 4; a++)
-         {
-            for (size_t k = 0; k < 3; k++)
-            {
+   for (size_t x = 0; x < x_size ; x++) {
+      for (size_t y = 0; y < y_size ; y++) {
+         for (size_t a = 0; a < 4; a++) {
+            for (size_t k = 0; k < 3; k++) {
                signal_dspin_false_int_cmd_in[x][y][a][k].write  = false;
                signal_dspin_false_int_cmd_in[x][y][a][k].read   = true;
@@ -1468 +1291 @@
             }
 
-            for (size_t k = 0; k < 2; k++)
-            {
+            for (size_t k = 0; k < 2; k++) {
                signal_dspin_false_int_rsp_in[x][y][a][k].write  = false;
                signal_dspin_false_int_rsp_in[x][y][a][k].read   = true;
@@ -1489 +1311 @@
    }
 
-    sc_start(sc_core::sc_time(1, SC_NS));
-    signal_resetn = true;
-
-    for (size_t n = 1; n < ncycles; n++)
-    {
-        // Monitor a specific address for one L1 cache
-        // clusters[1][1]->proc[0]->cache_monitor(0x50090ULL);
-
-        // Monitor a specific address for one L2 cache
-        // clusters[0][0]->memc->cache_monitor( 0x170000ULL);
-
-        // Monitor a specific address for one XRAM
-        // if (n == 3000000)
-        //     clusters[0][0]->xram->start_monitor( 0x170000ULL , 64);
-
-        if (debug_ok and (n > debug_from) and (n % debug_period == 0))
-        {
-            std::cout << " ***********************"
-                      << " cycle " << std::dec << n
-                      << " ***********************"
-                      << std::endl;
-
-            // trace proc[debug_proc_id]
-            if ( debug_proc_id != 0xFFFFFFFF )
-            {
-                size_t l          = debug_proc_id % nb_procs ;
-                size_t cluster_xy = debug_proc_id / nb_procs ;
-                size_t x          = cluster_xy >> Y_WIDTH;
-                size_t y          = cluster_xy  & ((1 << Y_WIDTH) - 1);
-
-                clusters[x][y]->proc[l]->print_trace(1);
-
-                std::ostringstream proc_signame;
-                proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
-                clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(
-                      proc_signame.str());
-
-                clusters[x][y]->xicu->print_trace(l);
-
-                std::ostringstream xicu_signame;
-                xicu_signame << "[SIG]XICU_" << x << "_" << y;
-                clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(
-                      xicu_signame.str());
-
-                if( clusters[x][y]->signal_proc_it[l].read() )
-                    std::cout << "### IRQ_PROC_" << std::dec
-                              << x << "_" << y << "_" << l
-                              << " ACTIVE" << std::endl;
+   sc_start(sc_core::sc_time(1, SC_NS));
+   signal_resetn = true;
+
+   struct timeval t1, t2;
+   const uint64_t stats_period = 100000;
+   gettimeofday(&t1, NULL);
+   for (uint64_t n = 1; n < ncycles; n++) {
+      // stats display
+      if((n % stats_period) == 0) {
+         gettimeofday(&t2, NULL);
+
+         uint64_t ms1 = (uint64_t) t1.tv_sec  * 1000 +
+            (uint64_t) t1.tv_usec / 1000;
+         uint64_t ms2 = (uint64_t) t2.tv_sec  * 1000 +
+            (uint64_t) t2.tv_usec / 1000;
+         double freq  = (double) stats_period / (ms2 - ms1);
+
+         std::cerr << "Platform Clock Frequency: " << freq << " Khz"
+            << std::endl;
+
+         gettimeofday(&t1, NULL);
+      }
+
+      if (debug_ok and (n > debug_from) and ((n % debug_period) == 0)) {
+         std::cout << " ***********************"
+            << " cycle " << std::dec << n
+            << " ***********************"
+            << std::endl;
+
+         // trace proc[debug_proc_id]
+         if ( debug_proc_id != 0xFFFFFFFF ) {
+            size_t l          = debug_proc_id % NB_PROCS ;
+            size_t cluster_xy = debug_proc_id / NB_PROCS ;
+            size_t x          = cluster_xy >> Y_WIDTH;
+            size_t y          = cluster_xy  & ((1 << Y_WIDTH) - 1);
+
+            clusters[x][y]->proc[l]->print_trace(1);
+
+            std::ostringstream proc_signame;
+            proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
+            clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(
+                  proc_signame.str());
+
+            clusters[x][y]->xicu->print_trace(l);
+
+            std::ostringstream xicu_signame;
+            xicu_signame << "[SIG]XICU_" << x << "_" << y;
+            clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(
+                  xicu_signame.str());
+
+            if( clusters[x][y]->signal_proc_it[l].read() ) {
+               std::cout << "### IRQ_PROC_" << std::dec
+                  << x << "_" << y << "_" << l
+                  << " ACTIVE" << std::endl;
             }
-
-            // trace INT network
-//          clusters[0][0]->int_xbar_cmd_d->print_trace();
-//          clusters[0][0]->int_xbar_rsp_d->print_trace();
-
-//          clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace(
-//             "[SIG] INT_CMD_L2G_D_0_0");
-//          clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace(
-//             "[SIG] INT_RSP_G2L_D_0_0");
-
-//          clusters[0][0]->int_router_cmd->print_trace(0);
-//          clusters[0][0]->int_router_rsp->print_trace(0);
-
-            // trace INT_CMD_D xbar and router in cluster 0_1
-//          clusters[0][1]->int_router_cmd->print_trace(0);
-//          clusters[0][1]->int_router_rsp->print_trace(0);
-
-//          clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace(
-//             "[SIG] INT_CMD_G2L_D_0_0");
-//          clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace(
-//             "[SIG] INT_RSP_L2G_D_0_0");
-
-//          clusters[0][1]->int_xbar_cmd_d->print_trace();
-//          clusters[0][1]->int_xbar_rsp_d->print_trace();
-
-            // trace memc[debug_memc_id]
-            if ( debug_memc_id != 0xFFFFFFFF )
-            {
-                size_t x = debug_memc_id >> Y_WIDTH;
-                size_t y = debug_memc_id  & ((1 << Y_WIDTH) - 1);
-
-                clusters[x][y]->memc->print_trace(0);
-                std::ostringstream smemc_tgt;
-                smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y;
-                clusters[x][y]->signal_int_vci_tgt_memc.print_trace(
-                      smemc_tgt.str());
-                std::ostringstream smemc_ini;
-                smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y;
-                clusters[x][y]->signal_ram_vci_ini_memc.print_trace(
-                      smemc_ini.str());
-                clusters[x][y]->xram->print_trace();
-                std::ostringstream sxram_tgt;
-                sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y;
-                clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(
-                      sxram_tgt.str());
-            }
-
-            // trace RAM network routers
-//          for( size_t cluster = 0 ; cluster < XMAX*YMAX ; cluster++ )
-//          {
-//              size_t x = cluster / YMAX;
-//              size_t y = cluster % YMAX;
-//              clusters[x][y]->ram_router_cmd->print_trace();
-//              clusters[x][y]->ram_router_rsp->print_trace();
-//          }
-
-            // trace iob, iox and external peripherals
-            if ( debug_iob )
-            {
-                clusters[0][0]->iob->print_trace();
-                clusters[0][0]->signal_int_vci_tgt_iobx.print_trace(
-                      "[SIG]IOB0_INT_TGT");
-                clusters[0][0]->signal_int_vci_ini_iobx.print_trace(
-                      "[SIG]IOB0_INT_INI");
-                clusters[0][0]->signal_ram_vci_ini_iobx.print_trace(
-                      "[SIG]IOB0_RAM_INI");
-
-                signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
-                signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
-
-//              signal_dspin_cmd_iob0_loopback.print_trace(
-//                    "[SIG]IOB0_CMD_LOOPBACK");
-//              signal_dspin_rsp_iob0_loopback.print_trace(
-//                    "[SIG]IOB0_RSP_LOOPBACK");
-
-                cdma->print_trace();
-                signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT");
-                signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI");
-
-//              mtty->print_trace();
-//              signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT");
-
-//              bdev->print_trace();
-//              signal_vci_tgt_bdev.print_trace("[SIG]IOX_BDEV_TGT");
-//              signal_vci_ini_bdev.print_trace("[SIG]IOX_BDEV_INI");
-
-//              fbuf->print_trace();
-//              signal_vci_tgt_fbuf.print_trace("[SIG]FBUF");
-
-                iox_network->print_trace();
-
-                // interrupts
-                if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED"
-                                               << std::endl;
-            }
-        }
-
-        sc_start(sc_core::sc_time(1, SC_NS));
-    }
+         }
+
+         // trace INT network
+         //          clusters[0][0]->int_xbar_d->print_trace();
+
+         //          clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace(
+         //             "[SIG] INT_CMD_L2G_D_0_0");
+         //          clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace(
+         //             "[SIG] INT_RSP_G2L_D_0_0");
+
+         //          clusters[0][0]->int_router_cmd->print_trace(0);
+         //          clusters[0][0]->int_router_rsp->print_trace(0);
+
+         // trace INT_CMD_D xbar and router in cluster 0_1
+         //          clusters[0][1]->int_router_cmd->print_trace(0);
+         //          clusters[0][1]->int_router_rsp->print_trace(0);
+
+         //          clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace(
+         //             "[SIG] INT_CMD_G2L_D_0_0");
+         //          clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace(
+         //             "[SIG] INT_RSP_L2G_D_0_0");
+
+         //          clusters[0][1]->int_xbar_cmd_d->print_trace();
+
+         // trace memc[debug_memc_id]
+         if ( debug_memc_id != 0xFFFFFFFF ) {
+            size_t x = debug_memc_id >> Y_WIDTH;
+            size_t y = debug_memc_id  & ((1 << Y_WIDTH) - 1);
+
+            clusters[x][y]->memc->print_trace(0);
+            std::ostringstream smemc_tgt;
+            smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y;
+            clusters[x][y]->signal_int_vci_tgt_memc.print_trace(
+                  smemc_tgt.str());
+            std::ostringstream smemc_ini;
+            smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y;
+            clusters[x][y]->signal_ram_vci_ini_memc.print_trace(
+                  smemc_ini.str());
+            clusters[x][y]->xram->print_trace();
+            std::ostringstream sxram_tgt;
+            sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y;
+            clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(
+                  sxram_tgt.str());
+         }
+
+         // trace iob, iox and external peripherals
+         if ( debug_iob ) {
+            clusters[0][0]->iob->print_trace();
+            clusters[0][0]->signal_int_vci_tgt_iobx.print_trace(
+                  "[SIG]IOB0_INT_TGT");
+            clusters[0][0]->signal_int_vci_ini_iobx.print_trace(
+                  "[SIG]IOB0_INT_INI");
+            clusters[0][0]->signal_ram_vci_ini_iobx.print_trace(
+                  "[SIG]IOB0_RAM_INI");
+
+            signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI");
+            signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT");
+
+            cdma->print_trace();
+            signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT");
+            signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI");
+
+            iox_network->print_trace();
+
+            // interrupts
+            if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED"
+               << std::endl;
+         }
+      }
+      sc_start(sc_core::sc_time(1, SC_NS));
+   }
 
    delete iox_network;
@@ -1645 +1445 @@
    delete mtty;
 
-   for(size_t x = 0; x < x_size; x++)
-   {
-      for(size_t y = 0; y < y_size; y++)
-      {
+   for(size_t x = 0; x < x_size; x++) {
+      for(size_t y = 0; y < y_size; y++) {
          delete clusters[x][y];
       }
    }
-
    return EXIT_SUCCESS;
 }
 
-int sc_main (int argc, char *argv[])
-{
+int sc_main (int argc, char *argv[]) {
    try {
       return _main(argc, argv);

branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd

@@ -3 +3 @@
 
 Module('caba:tsar_iob_cluster',
-        classname = 'soclib::caba::TsarIobCluster',
+    classname = 'soclib::caba::TsarIobCluster',
 
-        tmpl_parameters = [
-                parameter.Module('vci_param_int', default = 'caba:vci_param', 
+    tmpl_parameters = [
+        parameter.Module('vci_param_int', default = 'caba:vci_param', 
                           cell_size = parameter.Reference('vci_data_width_int')),
-                parameter.Module('vci_param_ext', default = 'caba:vci_param', 
+        parameter.Module('vci_param_ext', default = 'caba:vci_param', 
                           cell_size = parameter.Reference('vci_data_width_ext')),
-                parameter.Int('dspin_int_cmd_width'),
-                parameter.Int('dspin_int_rsp_width'),
-                parameter.Int('dspin_ram_cmd_width'),
-                parameter.Int('dspin_ram_rsp_width'),
-        ],
+        parameter.Int('dspin_int_cmd_width'),
+        parameter.Int('dspin_int_rsp_width'),
+        parameter.Int('dspin_ram_cmd_width'),
+        parameter.Int('dspin_ram_rsp_width'),
+    ],
 
-        header_files = [ 
+    header_files = [ 
+        '../source/include/tsar_iob_cluster.h', 
         '../source/include/tsar_iob_cluster.h', 
     ],
 
-        implementation_files = [ 
+    implementation_files = [ 
         '../source/src/tsar_iob_cluster.cpp', 
     ],
 
-        uses = [
-                Uses('caba:base_module'),
-                Uses('common:mapping_table'),
-                Uses('common:iss2'),
-                Uses('common:elf_file_loader'),
+    uses = [
+        Uses('caba:base_module'),
+        Uses('common:mapping_table'),
+        Uses('common:iss2'),
+        Uses('common:elf_file_loader'),
 
         # internal network components
-                Uses('caba:vci_cc_vcache_wrapper', 
+        Uses('caba:vci_cc_vcache_wrapper', 
               cell_size          = parameter.Reference('vci_data_width_int'),
               dspin_in_width     = parameter.Reference('dspin_int_cmd_width'),
@@ -38 +39 @@
               gdb_iss_t          = 'common:mips32el'),
 
-                Uses('caba:vci_mem_cache',
+        Uses('caba:vci_mem_cache',
               memc_cell_size_int = parameter.Reference('vci_data_width_int'),
               memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
@@ -47 +48 @@
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-                Uses('caba:vci_simple_rom',
+        Uses('caba:vci_simple_rom',
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-                Uses('caba:vci_multi_dma',
+        Uses('caba:vci_multi_tty',
+              cell_size          = parameter.Reference('vci_data_width_int')),
+
+        Uses('caba:vci_multi_dma',
               cell_size          = parameter.Reference('vci_data_width_int')),
 
@@ -92 +96 @@
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
-                Uses('caba:vci_simple_ram',
+        Uses('caba:vci_simple_ram',
               cell_size          = parameter.Reference('vci_data_width_ext')),
 
@@ -99 +103 @@
               iob_cell_size_int  = parameter.Reference('vci_data_width_int'),
               iob_cell_size_ext  = parameter.Reference('vci_data_width_ext')),
-                ],
+        ],
 
-        ports = [
-                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
-                Port('caba:clock_in', 'p_clk', auto = 'clock'),
+    ports = [
+        Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+        Port('caba:clock_in', 'p_clk', auto = 'clock'),
 
-                Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], 
+        Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], 
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-                Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], 
+        Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], 
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-                Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], 
+        Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], 
               dspin_data_size = parameter.Reference('dspin_int_rsp_width')), 
-                Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], 
+        Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], 
               dspin_data_size = parameter.Reference('dspin_int_rsp_width')),
 
-                Port('caba:dspin_output', 'p_ram_cmd_out', [4], 
+        Port('caba:dspin_output', 'p_ram_cmd_out', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-                Port('caba:dspin_input', 'p_ram_cmd_in', [4], 
+        Port('caba:dspin_input', 'p_ram_cmd_in', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-                Port('caba:dspin_output', 'p_ram_rsp_out', [4], 
+        Port('caba:dspin_output', 'p_ram_rsp_out', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), 
-                Port('caba:dspin_input', 'p_ram_rsp_in', [4], 
+        Port('caba:dspin_input', 'p_ram_rsp_in', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_rsp_width')),
-                ],
+        ],
 )
 

branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h

@@ -32 +32 @@
 #include "vci_cc_vcache_wrapper.h"
 #include "vci_io_bridge.h"
+#include "vci_multi_tty.h"
+#include "hard_config.h"
+
+///////////////////////////////////////////////////////////////////////
+//     Number of channels for debug TTY (may be 0)
+///////////////////////////////////////////////////////////////////////
+#define NB_DEBUG_TTY_CHANNELS 1
+
+///////////////////////////////////////////////////////////////////////
+//     TGT_ID and INI_ID port indexing for INT local interconnect
+///////////////////////////////////////////////////////////////////////
+
+#define INT_MEMC_TGT_ID 0
+#define INT_XICU_TGT_ID 1
+#define INT_BROM_TGT_ID 2
+#define INT_MDMA_TGT_ID 3
+#define INT_MTTY_TGT_ID 4
+#define INT_IOBX_TGT_ID (4 + (NB_DEBUG_TTY_CHANNELS ? 1 : 0))
+
+#define INT_PROC_INI_ID 0 // from 0 to 7
+#define INT_MDMA_INI_ID NB_PROCS
+#define INT_IOBX_INI_ID (NB_PROCS + 1)
+
+///////////////////////////////////////////////////////////////////////
+//     TGT_ID and INI_ID port indexing for RAM local interconnect
+///////////////////////////////////////////////////////////////////////
+
+#define RAM_XRAM_TGT_ID 0
+
+#define RAM_MEMC_INI_ID 0
+#define RAM_IOBX_INI_ID 1
 
 namespace soclib { namespace caba {
@@ -81 +112 @@
       sc_signal<bool> signal_proc_it[8];
       sc_signal<bool> signal_irq_mdma[8];
+      sc_signal<bool> signal_irq_mtty[8];
       sc_signal<bool> signal_irq_memc;
 
@@ -104 +136 @@
       VciSignals<vci_param_int> signal_int_vci_tgt_xicu;
       VciSignals<vci_param_int> signal_int_vci_tgt_brom;
+      VciSignals<vci_param_int> signal_int_vci_tgt_mtty;
       VciSignals<vci_param_int> signal_int_vci_tgt_mdma;
       VciSignals<vci_param_int> signal_int_vci_tgt_iobx;
@@ -122 +155 @@
       DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_brom_t;
       DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_brom_t;
+      DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mtty_t;
+      DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mtty_t;
       DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t;
       DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t;
@@ -186 +221 @@
       VciIntDspinTargetWrapperType*    brom_int_wt;
 
+      VciMultiTty<vci_param_int>*      mtty;
+      VciIntDspinTargetWrapperType*    mtty_int_wt;
+
       DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d;
       DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d;
@@ -213 +251 @@
          sc_module_name insname;
 
-         size_t nb_procs;
-         size_t nb_dmas;
          size_t x_id;
          size_t y_id;
-         size_t x_size;
-         size_t y_size;
 
          const soclib::common::MappingTable &mt_int;
          const soclib::common::MappingTable &mt_ext;
          const soclib::common::MappingTable &mt_iox;
-
-         size_t x_width;
-         size_t y_width;
-         size_t l_width;
-
-         size_t int_memc_tgtid;
-         size_t int_xicu_tgtid;
-         size_t int_mdma_tgtid;
-         size_t int_iobx_tgtid;
-         size_t int_brom_tgtid;
-         size_t int_proc_srcid;
-         size_t int_mdma_srcid;
-         size_t int_iobx_srcid;
-         size_t ext_xram_tgtid;
-         size_t ext_memc_srcid;
-         size_t ext_iobx_srcid;
 
          size_t memc_ways;
@@ -257 +275 @@
       };
 
+      // utility functions
+      static uint32_t clusterId(size_t x_id, size_t y_id) {
+         return ((x_id << Y_WIDTH) | y_id); 
+      };
+
       // cluster constructor
       TsarIobCluster(struct ClusterParams& params);

branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp

@@ -33 +33 @@
 //////////////////////////////////////////////////////////////////////////
 tmpl(/**/)::TsarIobCluster(struct ClusterParams& params) :
-   soclib::caba::BaseModule(params.insname), p_clk("clk"), p_resetn("resetn")
-{
-   assert((params.x_id < params.x_size) and (params.y_id < params.y_size));
-
-   this->m_procs = params.nb_procs;
-   size_t cluster_id = (params.x_id << 4) + params.y_id;
-
-   size_t cluster_iob0 = 0;
-   size_t cluster_iob1 = ((params.x_size - 1) << 4) + params.y_size - 1;
+   soclib::caba::BaseModule(params.insname),
+   p_clk("clk"),
+   p_resetn("resetn") {
+
+   assert((params.x_id < X_MAX) && (params.y_id < Y_MAX));
+
+   size_t cid           = this->clusterId(params.x_id, params.y_id);
+   size_t cluster_iob0  = this->clusterId(0, 0);
+   size_t cluster_iob1  = this->clusterId(X_SIZE - 1, Y_SIZE - 1);
+   size_t is_iob0       = (cid == cluster_iob0);
+   size_t is_iob1       = (cid == cluster_iob1);
+   bool   is_io_cluster = is_iob0 || is_iob1;
+
+   size_t l_width = vci_param_int::S - X_WIDTH - Y_WIDTH;
 
    // Vectors of DSPIN ports for inter-cluster communications
@@ -63 +68 @@
 
    // ports in cluster_iob0 and cluster_iob1 only
-   if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
-   {
+   p_vci_iob_iox_ini   = NULL;
+   p_vci_iob_iox_tgt   = NULL;
+   p_dspin_iob_cmd_out = NULL;
+   p_dspin_iob_rsp_in  = NULL;
+   if ( is_io_cluster ) {
       // VCI ports from IOB to IOX network
       p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
@@ -70 +78 @@
 
       // DSPIN ports from IOB to RAM network
-      p_dspin_iob_cmd_out =
-         new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
-      p_dspin_iob_rsp_in  =
-         new soclib::caba::DspinInput<dspin_ram_rsp_width>;
-   }
-   else
-   {
-      p_vci_iob_iox_ini   = NULL;
-      p_vci_iob_iox_tgt   = NULL;
-      p_dspin_iob_cmd_out = NULL;
-      p_dspin_iob_rsp_in  = NULL;
+      p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
+      p_dspin_iob_rsp_in  = new soclib::caba::DspinInput<dspin_ram_rsp_width>;
    }
 
    // IRQ ports in cluster_iob0 only
-   for ( size_t n = 0 ; n < 32 ; n++ )
-   {
-      if ( cluster_id == cluster_iob0 )
-      {
-         p_irq[n] = new sc_in<bool>;
-      }
-      else
-      {
-         p_irq[n] = NULL;
-      }
+   for ( size_t n = 0 ; n < 32 ; n++ ) {
+      p_irq[n] = ( is_iob0 ) ? new sc_in<bool> : NULL;
    }
 
@@ -101 +92 @@
 
    ////////////  PROCS
-   for (size_t p = 0; p < params.nb_procs; p++)
-   { 
+   for (size_t p = 0; p < NB_PROCS; p++) { 
       std::ostringstream s_proc;
       s_proc << "proc_" << params.x_id << "_" << params.y_id << "_" << p;
       proc[p] = new VciCcVCacheWrapperType (
             s_proc.str().c_str(),
-            cluster_id * params.nb_procs + p,
+            cid * NB_PROCS + p,
             params.mt_int,
-            IntTab(cluster_id,p),
-            (cluster_id << params.l_width) + p,
+            IntTab(cid,p),
+            (cid << l_width) + p,
             8, 8,
             8, 8,
@@ -116 +106 @@
             params.l1_d_ways, params.l1_d_sets, 16,
             4, 4,
-            params.x_width, params.y_width,
+            X_WIDTH, Y_WIDTH,
             params.frozen_cycles,
             params.debug_start_cycle, params.proc_debug_ok);
 
+      proc[p]->set_dcache_paddr_ext_reset(cid);
+      proc[p]->set_icache_paddr_ext_reset(cid);
+
       std::ostringstream s_wi_proc;
-      s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_"
-         << p;
+      s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_" << p;
       proc_wi[p] = new VciIntDspinInitiatorWrapperType(
             s_wi_proc.str().c_str(),
-            params.x_width + params.y_width + params.l_width);
+            vci_param_int::S);
    }
 
@@ -135 +127 @@
          params.mt_int,
          params.mt_ext,
-         IntTab(cluster_id, params.ext_memc_srcid),
-         IntTab(cluster_id, params.int_memc_tgtid),
-         params.x_width,
-         params.y_width,
+         IntTab(cid, RAM_MEMC_INI_ID),
+         IntTab(cid, INT_MEMC_TGT_ID),
+         X_WIDTH,
+         Y_WIDTH,
          params.memc_ways, params.memc_sets, 16,
          3,
          4096,
-         8,
-         8,
-         8,
+         8, 8, 8,
          params.debug_start_cycle,
          params.memc_debug_ok);
@@ -152 +142 @@
    memc_int_wt = new VciIntDspinTargetWrapperType (
          s_wt_memc.str().c_str(),
-         params.x_width + params.y_width + params.l_width);
+         vci_param_int::S);
 
    std::ostringstream s_wi_memc;
@@ -158 +148 @@
    memc_ram_wi = new VciExtDspinInitiatorWrapperType (
          s_wi_memc.str().c_str(),
-         params.x_width + params.y_width + params.l_width);
+         vci_param_int::S);
 
    ///////////   LOCAL ROM
+   std::ostringstream s_brom;
+   s_brom << "brom_" << params.x_id << "_" << params.y_id;
    brom = new VciSimpleRom<vci_param_int>(
-         "brom",
-         IntTab(cluster_id, params.int_brom_tgtid),
+         s_brom.str().c_str(),
+         IntTab(cid, INT_BROM_TGT_ID),
          params.mt_int,
          params.loader,
-         params.x_width + params.y_width);
+         X_WIDTH + Y_WIDTH);
 
    std::ostringstream s_wt_brom;
@@ -172 +164 @@
    brom_int_wt = new VciIntDspinTargetWrapperType (
          s_wt_brom.str().c_str(),
-         params.x_width + params.y_width + params.l_width);
+         vci_param_int::S);
+
+   // Multi-TTY controller
+   mtty        = NULL;
+   mtty_int_wt = NULL;
+   if (NB_DEBUG_TTY_CHANNELS) {
+      assert(NB_DEBUG_TTY_CHANNELS < 8);
+
+      std::ostringstream s_mtty;
+      s_mtty << "mtty_" << params.x_id << "_" << params.y_id;
+      std::vector<std::string> vect_names;
+      for( size_t tid = 0 ; tid < NB_DEBUG_TTY_CHANNELS ; tid++ ) {
+         std::ostringstream term_name;
+         term_name << s_mtty.str() << "_" << tid;
+         vect_names.push_back(term_name.str().c_str());
+      }
+      mtty = new VciMultiTty<vci_param_int>(
+            s_mtty.str().c_str(),
+            IntTab(cid, INT_MTTY_TGT_ID),
+            params.mt_int,
+            vect_names);
+
+      std::ostringstream s_wt_mtty;
+      s_wt_mtty << "mtty_wt_" << params.x_id << "_" << params.y_id;
+      mtty_int_wt = new VciIntDspinTargetWrapperType (
+            s_wt_mtty.str().c_str(),
+            vci_param_int::S);
+   }
 
    ///////////   XICU
@@ -180 +199 @@
          s_xicu.str().c_str(),
          params.mt_int,
-         IntTab(cluster_id,params.int_xicu_tgtid),
+         IntTab(cid, INT_XICU_TGT_ID),
          32, 32, 32,
-         params.nb_procs);
+         NB_PROCS);
 
    std::ostringstream s_wt_xicu;
@@ -188 +207 @@
    xicu_int_wt = new VciIntDspinTargetWrapperType (
          s_wt_xicu.str().c_str(),
-         params.x_width + params.y_width + params.l_width);
+         vci_param_int::S);
 
    ////////////  MDMA
@@ -196 +215 @@
          s_mdma.str().c_str(),
          params.mt_int,
-         IntTab(cluster_id, params.nb_procs),
-         IntTab(cluster_id, params.int_mdma_tgtid),
+         IntTab(cid, NB_PROCS),
+         IntTab(cid, INT_MDMA_TGT_ID),
          64,
-         params.nb_dmas);
+         NB_DMA_CHANNELS);
 
    std::ostringstream s_wt_mdma;
@@ -205 +224 @@
    mdma_int_wt = new VciIntDspinTargetWrapperType(
          s_wt_mdma.str().c_str(),
-         params.x_width + params.y_width + params.l_width);
+         vci_param_int::S);
 
    std::ostringstream s_wi_mdma;
@@ -211 +230 @@
    mdma_int_wi = new VciIntDspinInitiatorWrapperType(
          s_wi_mdma.str().c_str(),
-         params.x_width + params.y_width + params.l_width);
+         vci_param_int::S);
 
    ///////////  Direct LOCAL_XBAR(S)
-   size_t nb_direct_initiators = params.nb_procs + 1;
+   size_t nb_direct_initiators = NB_PROCS + 1;
    size_t nb_direct_targets    = 4;
-   if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1))
-   {
-      nb_direct_initiators = params.nb_procs + 2;
-      nb_direct_targets    = 5;
+   if (NB_DEBUG_TTY_CHANNELS) {
+      nb_direct_targets++;
+   }
+   if ( is_io_cluster ) {
+      nb_direct_initiators++;
+      nb_direct_targets++;
    }
 
@@ -228 +249 @@
          params.mt_int,
          params.x_id, params.y_id,
-         params.x_width, params.y_width, params.l_width,
+         X_WIDTH, Y_WIDTH, l_width,
          nb_direct_initiators,
          nb_direct_targets,
@@ -242 +263 @@
          params.mt_int,
          params.x_id, params.y_id,
-         params.x_width, params.y_width, params.l_width,
+         X_WIDTH, Y_WIDTH, l_width,
          nb_direct_targets,
          nb_direct_initiators,
@@ -257 +278 @@
          params.mt_int,
          params.x_id, params.y_id,
-         params.x_width, params.y_width, params.l_width,
+         X_WIDTH, Y_WIDTH, l_width,
          1,
-         params.nb_procs,
+         NB_PROCS,
          2, 2,
          true,
@@ -271 +292 @@
          params.mt_int,
          params.x_id, params.y_id,
-         params.x_width, params.y_width, 0,
-         params.nb_procs,
+         X_WIDTH, Y_WIDTH, 0,
+         NB_PROCS,
          1,
          2, 2,
@@ -281 +302 @@
    std::ostringstream s_int_xbar_clack_c;
    s_int_xbar_clack_c << "int_xbar_clack_c_" << params.x_id << "_"
-      << params.y_id;
+                                             << params.y_id;
    int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
          s_int_xbar_clack_c.str().c_str(),
          params.mt_int,
          params.x_id, params.y_id,
-         params.x_width, params.y_width, params.l_width,
+         X_WIDTH, Y_WIDTH, l_width,
          1,
-         params.nb_procs,
+         NB_PROCS,
          1, 1,
          true,
@@ -299 +320 @@
    int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
          s_int_router_cmd.str().c_str(),
-         params.x_id,params.y_id,
-         params.x_width, params.y_width,
+         params.x_id, params.y_id,
+         X_WIDTH, Y_WIDTH,
          3,
          4,4);
@@ -308 +329 @@
    int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
          s_int_router_rsp.str().c_str(),
-         params.x_id,params.y_id,
-         params.x_width, params.y_width,
+         params.x_id, params.y_id,
+         X_WIDTH, Y_WIDTH,
          2,
          4,4);
@@ -318 +339 @@
    xram = new VciSimpleRam<vci_param_ext>(
          s_xram.str().c_str(),
-         IntTab(cluster_id, params.ext_xram_tgtid),
+         IntTab(cid, RAM_XRAM_TGT_ID),
          params.mt_ext,
          params.loader,
@@ -327 +348 @@
    xram_ram_wt = new VciExtDspinTargetWrapperType(
          s_wt_xram.str().c_str(),
-         params.x_width + params.y_width + params.l_width);
+         vci_param_int::S);
 
    /////////////  RAM ROUTER(S)
    std::ostringstream s_ram_router_cmd;
    s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id;
-   size_t is_iob0 = (params.x_id == 0) and (params.y_id == 0);
-   size_t is_iob1 = (params.x_id == (params.x_size-1)) and
-      (params.y_id == (params.y_size-1));
    ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>(
          s_ram_router_cmd.str().c_str(),
          params.x_id, params.y_id,
-         params.x_width,
-         params.y_width,
+         X_WIDTH, Y_WIDTH,
          4, 4,
-         is_iob0,
-         is_iob1,
+         is_iob0, is_iob1,
          false,
-         params.l_width);
+         l_width);
 
    std::ostringstream s_ram_router_rsp;
@@ -351 +367 @@
          s_ram_router_rsp.str().c_str(),
          params.x_id, params.y_id,
-         params.x_width,
-         params.y_width,
+         X_WIDTH, Y_WIDTH,
          4, 4,
-         is_iob0,
-         is_iob1,
+         is_iob0, is_iob1,
          true,
-         params.l_width);
+         l_width);
 
    ////////////////////// I/O  CLUSTER ONLY ///////////////////////
-   if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1))
-   {
+   iob        = NULL;
+   iob_int_wi = NULL;
+   iob_int_wt = NULL;
+   iob_ram_wi = NULL;
+   if ( is_io_cluster ) {
       ///////////  IO_BRIDGE
       size_t iox_local_id;
-      size_t global_id;
       bool   has_irqs;
-      if (cluster_id == cluster_iob0 ) 
-      {
+      if ( is_iob0 ) {
          iox_local_id = 0;
-         global_id    = cluster_iob0;
          has_irqs     = true;
       }
-      else
-      {
+      else {
          iox_local_id = 1;
-         global_id    = cluster_iob1;
          has_irqs     = false;
       }
@@ -386 +398 @@
             params.mt_int,
             params.mt_iox,
-            IntTab( global_id, params.int_iobx_tgtid),
-            IntTab( global_id, params.int_iobx_srcid),
-            IntTab( global_id, iox_local_id ),
+            IntTab(cid, INT_IOBX_TGT_ID),
+            IntTab(cid, INT_IOBX_INI_ID),
+            IntTab(cid, iox_local_id ),
             has_irqs,
             16,
@@ -400 +412 @@
       iob_int_wi = new VciIntDspinInitiatorWrapperType(
             s_iob_int_wi.str().c_str(),
-            params.x_width + params.y_width + params.l_width);
+            vci_param_int::S);
 
       std::ostringstream s_iob_int_wt;
@@ -406 +418 @@
       iob_int_wt = new VciIntDspinTargetWrapperType(
             s_iob_int_wt.str().c_str(),
-            params.x_width + params.y_width + params.l_width);
+            vci_param_int::S);
 
       std::ostringstream s_iob_ram_wi;
@@ -412 +424 @@
       iob_ram_wi = new VciExtDspinInitiatorWrapperType(
             s_iob_ram_wi.str().c_str(),
-            params.x_width + params.y_width + params.l_width);
-   }
-   else
-   {
-      iob        = NULL;
-      iob_int_wi = NULL;
-      iob_int_wt = NULL;
-      iob_ram_wi = NULL;
+            vci_param_int::S);
    }
 
@@ -426 +431 @@
    ////////////////////////////////////
 
-   // on coherence network : local srcid[proc] in [0...nb_procs-1]
-   //                      : local srcid[memc] = nb_procs
+   // on coherence network : local srcid[proc] in [0...NB_PROCS-1]
+   //                      : local srcid[memc] = NB_PROCS
    // In cluster_iob0, 32 HWI interrupts from external peripherals
    // are connected to the XICU ports p_hwi[0:31] 
@@ -438 +443 @@
    int_router_rsp->p_resetn (this->p_resetn);
 
-   for (int i = 0; i < 4; i++)
-   {
-      for(int k = 0; k < 3; k++)
-      {
+   for (int i = 0; i < 4; i++) {
+      for(int k = 0; k < 3; k++) {
          int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
          int_router_cmd->p_in[i][k]  (this->p_dspin_int_cmd_in[i][k]);
       }
-
-      for(int k = 0; k < 2; k++)
-      {
+      for(int k = 0; k < 2; k++) {
          int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
          int_router_rsp->p_in[i][k]  (this->p_dspin_int_rsp_in[i][k]);
@@ -472 +473 @@
    int_xbar_cmd_d->p_global_in  (signal_int_dspin_cmd_g2l_d);
 
-   int_xbar_cmd_d->p_local_out[params.int_memc_tgtid](
-         signal_int_dspin_cmd_memc_t);
-   int_xbar_cmd_d->p_local_out[params.int_xicu_tgtid](
-         signal_int_dspin_cmd_xicu_t);
-   int_xbar_cmd_d->p_local_out[params.int_brom_tgtid](
-         signal_int_dspin_cmd_brom_t);
-   int_xbar_cmd_d->p_local_out[params.int_mdma_tgtid](
-         signal_int_dspin_cmd_mdma_t);
-   int_xbar_cmd_d->p_local_in[params.int_mdma_srcid](
-         signal_int_dspin_cmd_mdma_i);
-
-   for (size_t p = 0; p < params.nb_procs; p++) {
-      int_xbar_cmd_d->p_local_in[params.int_proc_srcid + p](
+   int_xbar_cmd_d->p_local_out[INT_MEMC_TGT_ID] (signal_int_dspin_cmd_memc_t);
+   int_xbar_cmd_d->p_local_out[INT_XICU_TGT_ID] (signal_int_dspin_cmd_xicu_t);
+   int_xbar_cmd_d->p_local_out[INT_BROM_TGT_ID] (signal_int_dspin_cmd_brom_t);
+   int_xbar_cmd_d->p_local_out[INT_MDMA_TGT_ID] (signal_int_dspin_cmd_mdma_t);
+   if (NB_DEBUG_TTY_CHANNELS) {
+      int_xbar_cmd_d->p_local_out[INT_MTTY_TGT_ID] (signal_int_dspin_cmd_mtty_t);
+   }
+   int_xbar_cmd_d->p_local_in[INT_MDMA_INI_ID]  (signal_int_dspin_cmd_mdma_i);
+
+   for (size_t p = 0; p < NB_PROCS; p++) {
+      int_xbar_cmd_d->p_local_in[INT_PROC_INI_ID + p](
             signal_int_dspin_cmd_proc_i[p]);
    }
 
-   if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1))
-   {
-      int_xbar_cmd_d->p_local_out[params.int_iobx_tgtid](
+   if ( is_io_cluster ) {
+      int_xbar_cmd_d->p_local_out[INT_IOBX_TGT_ID](
             signal_int_dspin_cmd_iobx_t);
-      int_xbar_cmd_d->p_local_in[params.int_iobx_srcid](
+      int_xbar_cmd_d->p_local_in[INT_IOBX_INI_ID](
             signal_int_dspin_cmd_iobx_i);
    }
@@ -502 +500 @@
    int_xbar_rsp_d->p_global_in  (signal_int_dspin_rsp_g2l_d);
 
-   int_xbar_rsp_d->p_local_in[params.int_memc_tgtid](
-         signal_int_dspin_rsp_memc_t);
-   int_xbar_rsp_d->p_local_in[params.int_xicu_tgtid](
-         signal_int_dspin_rsp_xicu_t);
-   int_xbar_rsp_d->p_local_in[params.int_brom_tgtid](
-         signal_int_dspin_rsp_brom_t);
-   int_xbar_rsp_d->p_local_in[params.int_mdma_tgtid](
-         signal_int_dspin_rsp_mdma_t);
-
-   int_xbar_rsp_d->p_local_out[params.int_mdma_srcid](
-         signal_int_dspin_rsp_mdma_i);
-   for (size_t p = 0; p < params.nb_procs; p++)
-      int_xbar_rsp_d->p_local_out[params.int_proc_srcid + p](
+   int_xbar_rsp_d->p_local_in[INT_MEMC_TGT_ID] (signal_int_dspin_rsp_memc_t);
+   int_xbar_rsp_d->p_local_in[INT_XICU_TGT_ID] (signal_int_dspin_rsp_xicu_t);
+   int_xbar_rsp_d->p_local_in[INT_BROM_TGT_ID] (signal_int_dspin_rsp_brom_t);
+   if (NB_DEBUG_TTY_CHANNELS) {
+      int_xbar_rsp_d->p_local_in[INT_MTTY_TGT_ID] (signal_int_dspin_rsp_mtty_t);
+   }
+   int_xbar_rsp_d->p_local_in[INT_MDMA_TGT_ID] (signal_int_dspin_rsp_mdma_t);
+
+   int_xbar_rsp_d->p_local_out[INT_MDMA_INI_ID](signal_int_dspin_rsp_mdma_i);
+   for (size_t p = 0; p < NB_PROCS; p++)
+      int_xbar_rsp_d->p_local_out[INT_PROC_INI_ID + p](
             signal_int_dspin_rsp_proc_i[p]);
 
-   if ((cluster_id == cluster_iob0) or (cluster_id == cluster_iob1))
-   {
-      int_xbar_rsp_d->p_local_in[params.int_iobx_tgtid](
+   if ( is_io_cluster ) {
+      int_xbar_rsp_d->p_local_in[INT_IOBX_TGT_ID](
             signal_int_dspin_rsp_iobx_t);
-      int_xbar_rsp_d->p_local_out[params.int_iobx_srcid](
+      int_xbar_rsp_d->p_local_out[INT_IOBX_INI_ID](
             signal_int_dspin_rsp_iobx_i);
    }
@@ -531 +526 @@
    int_xbar_m2p_c->p_global_in        (signal_int_dspin_m2p_g2l_c);
    int_xbar_m2p_c->p_local_in[0]      (signal_int_dspin_m2p_memc);
-   for (size_t p = 0; p < params.nb_procs; p++)
-   {
+   for (size_t p = 0; p < NB_PROCS; p++) {
       int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
    }
@@ -542 +536 @@
    int_xbar_p2m_c->p_global_in       (signal_int_dspin_p2m_g2l_c);
    int_xbar_p2m_c->p_local_out[0]    (signal_int_dspin_p2m_memc);
-   for (size_t p = 0; p < params.nb_procs; p++)
-   {
+   for (size_t p = 0; p < NB_PROCS; p++) {
       int_xbar_p2m_c->p_local_in[p]   (signal_int_dspin_p2m_proc[p]);
    }
@@ -553 +546 @@
    int_xbar_clack_c->p_global_in       (signal_int_dspin_clack_g2l_c);
    int_xbar_clack_c->p_local_in[0]     (signal_int_dspin_clack_memc);
-   for (size_t p = 0; p < params.nb_procs; p++)
-   {
+   for (size_t p = 0; p < NB_PROCS; p++) {
       int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
    }
 
    //////////////////////////////////// Processors
-   for (size_t p = 0; p < params.nb_procs; p++)
-   {
+   for (size_t p = 0; p < NB_PROCS; p++) {
       proc[p]->p_clk          (this->p_clk);
       proc[p]->p_resetn       (this->p_resetn);
@@ -568 +559 @@
       proc[p]->p_dspin_clack  (signal_int_dspin_clack_proc[p]);
       proc[p]->p_irq[0]       (signal_proc_it[p]);
-      for ( size_t j = 1 ; j < 6 ; j++)
-      {
+      for ( size_t j = 1 ; j < 6 ; j++) {
          proc[p]->p_irq[j]    (signal_false);
       }
@@ -584 +574 @@
    xicu->p_resetn (this->p_resetn);
    xicu->p_vci    (signal_int_vci_tgt_xicu);
-   for ( size_t p = 0 ; p < params.nb_procs ; p++)
-   {
+   for ( size_t p = 0 ; p < NB_PROCS ; p++) {
       xicu->p_irq[p] (signal_proc_it[p]);
    }
-   for ( size_t i=0 ; i<32 ; i++)
-   {
-      if (cluster_id == cluster_iob0) 
+   for ( size_t i=0 ; i<32 ; i++) {
+      if ( is_iob0 ) 
          xicu->p_hwi[i] (*(this->p_irq[i]));
       else  
@@ -639 +627 @@
    brom_int_wt->p_vci       (signal_int_vci_tgt_brom);
 
+   if (NB_DEBUG_TTY_CHANNELS) {
+      //////////////////////////////////// MTTY
+      mtty->p_clk              (this->p_clk);
+      mtty->p_resetn           (this->p_resetn);
+      mtty->p_vci              (signal_int_vci_tgt_mtty);
+
+      for ( size_t i=0 ; i < NB_DEBUG_TTY_CHANNELS ; i++ ) {
+         mtty->p_irq[i] (signal_irq_mtty[i]);
+      }
+
+      //wrapper to INT network
+      mtty_int_wt->p_clk       (this->p_clk);
+      mtty_int_wt->p_resetn    (this->p_resetn);
+      mtty_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mtty_t);
+      mtty_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mtty_t);
+      mtty_int_wt->p_vci       (signal_int_vci_tgt_mtty);
+   }
+
    //////////////////////////////////// XRAM
    xram->p_clk              (this->p_clk);
@@ -656 +662 @@
    mdma->p_vci_target       (signal_int_vci_tgt_mdma);
    mdma->p_vci_initiator    (signal_int_vci_ini_mdma);
-   for (size_t i = 0 ; i < params.nb_dmas ; i++)
+   for (size_t i = 0 ; i < NB_DMA_CHANNELS ; i++)
       mdma->p_irq[i]        (signal_irq_mdma[i]);
 
@@ -678 +684 @@
    ram_router_rsp->p_clk       (this->p_clk);
    ram_router_rsp->p_resetn    (this->p_resetn);
-   for( size_t n=0 ; n<4 ; n++)
-   {
+   for( size_t n=0 ; n<4 ; n++) {
       ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
       ram_router_cmd->p_in[n]  (this->p_dspin_ram_cmd_in[n]);
@@ -691 +696 @@
 
    ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 
-   if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
-   {
+   if ( is_io_cluster ) {
       // IO bridge
       iob->p_clk         (this->p_clk);
@@ -702 +706 @@
       iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
 
-      if ( cluster_id == cluster_iob0 )
+      if ( is_iob0 )
          for ( size_t n = 0 ; n < 32 ; n++ )
             (*iob->p_irq[n]) (*(this->p_irq[n]));
@@ -729 +733 @@
 } // end constructor
 
-tmpl(/**/)::~TsarIobCluster()
-{
+tmpl(/**/)::~TsarIobCluster() {
    if (p_vci_iob_iox_ini)   delete p_vci_iob_iox_ini;
    if (p_vci_iob_iox_tgt)   delete p_vci_iob_iox_tgt;
@@ -740 +743 @@
    if (iob_ram_wi)          delete iob_ram_wi;
 
-   for (size_t n = 0 ; n < 32 ; n++)
-   {
+   for (size_t n = 0 ; n < 32 ; n++) {
       if (p_irq[n]) delete p_irq[n];
    }
 
-   for (size_t p = 0; p < m_procs; p++)
-   { 
+   for (size_t p = 0; p < NB_PROCS; p++) { 
       delete proc[p];
       delete proc_wi[p];
@@ -758 +759 @@
    delete brom;
    delete brom_int_wt;
+   delete mtty;
+   delete mtty_int_wt;
    delete mdma;
    delete mdma_int_wt;