Index: branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
===================================================================
--- branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 658)
+++ branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 695)
@@ -3,33 +3,34 @@
 
 Module('caba:tsar_iob_cluster',
-	classname = 'soclib::caba::TsarIobCluster',
+    classname = 'soclib::caba::TsarIobCluster',
 
-	tmpl_parameters = [
-		parameter.Module('vci_param_int', default = 'caba:vci_param', 
+    tmpl_parameters = [
+        parameter.Module('vci_param_int', default = 'caba:vci_param', 
                           cell_size = parameter.Reference('vci_data_width_int')),
-		parameter.Module('vci_param_ext', default = 'caba:vci_param', 
+        parameter.Module('vci_param_ext', default = 'caba:vci_param', 
                           cell_size = parameter.Reference('vci_data_width_ext')),
-		parameter.Int('dspin_int_cmd_width'),
-		parameter.Int('dspin_int_rsp_width'),
-		parameter.Int('dspin_ram_cmd_width'),
-		parameter.Int('dspin_ram_rsp_width'),
-	],
+        parameter.Int('dspin_int_cmd_width'),
+        parameter.Int('dspin_int_rsp_width'),
+        parameter.Int('dspin_ram_cmd_width'),
+        parameter.Int('dspin_ram_rsp_width'),
+    ],
 
-	header_files = [ 
+    header_files = [ 
+        '../source/include/tsar_iob_cluster.h', 
         '../source/include/tsar_iob_cluster.h', 
     ],
 
-	implementation_files = [ 
+    implementation_files = [ 
         '../source/src/tsar_iob_cluster.cpp', 
     ],
 
-	uses = [
-		Uses('caba:base_module'),
-		Uses('common:mapping_table'),
-		Uses('common:iss2'),
-		Uses('common:elf_file_loader'),
+    uses = [
+        Uses('caba:base_module'),
+        Uses('common:mapping_table'),
+        Uses('common:iss2'),
+        Uses('common:elf_file_loader'),
 
         # internal network components
-		Uses('caba:vci_cc_vcache_wrapper', 
+        Uses('caba:vci_cc_vcache_wrapper', 
               cell_size          = parameter.Reference('vci_data_width_int'),
               dspin_in_width     = parameter.Reference('dspin_int_cmd_width'),
@@ -38,5 +39,5 @@
               gdb_iss_t          = 'common:mips32el'),
 
-		Uses('caba:vci_mem_cache',
+        Uses('caba:vci_mem_cache',
               memc_cell_size_int = parameter.Reference('vci_data_width_int'),
               memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
@@ -47,8 +48,11 @@
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-		Uses('caba:vci_simple_rom',
+        Uses('caba:vci_simple_rom',
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-		Uses('caba:vci_multi_dma',
+        Uses('caba:vci_multi_tty',
+              cell_size          = parameter.Reference('vci_data_width_int')),
+
+        Uses('caba:vci_multi_dma',
               cell_size          = parameter.Reference('vci_data_width_int')),
 
@@ -92,5 +96,5 @@
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
-		Uses('caba:vci_simple_ram',
+        Uses('caba:vci_simple_ram',
               cell_size          = parameter.Reference('vci_data_width_ext')),
 
@@ -99,28 +103,28 @@
               iob_cell_size_int  = parameter.Reference('vci_data_width_int'),
               iob_cell_size_ext  = parameter.Reference('vci_data_width_ext')),
-		],
+        ],
 
-	ports = [
-		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
-		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+    ports = [
+        Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+        Port('caba:clock_in', 'p_clk', auto = 'clock'),
 
-		Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], 
+        Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], 
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-		Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], 
+        Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], 
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-		Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], 
+        Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], 
               dspin_data_size = parameter.Reference('dspin_int_rsp_width')), 
-		Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], 
+        Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], 
               dspin_data_size = parameter.Reference('dspin_int_rsp_width')),
 
-		Port('caba:dspin_output', 'p_ram_cmd_out', [4], 
+        Port('caba:dspin_output', 'p_ram_cmd_out', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-		Port('caba:dspin_input', 'p_ram_cmd_in', [4], 
+        Port('caba:dspin_input', 'p_ram_cmd_in', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-		Port('caba:dspin_output', 'p_ram_rsp_out', [4], 
+        Port('caba:dspin_output', 'p_ram_rsp_out', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), 
-		Port('caba:dspin_input', 'p_ram_rsp_in', [4], 
+        Port('caba:dspin_input', 'p_ram_rsp_in', [4], 
               dspin_data_size = parameter.Reference('dspin_ram_rsp_width')),
-		],
+        ],
 )
 
