Changeset 696
- Timestamp:
- May 18, 2014, 9:04:55 PM (11 years ago)
- Location:
- branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
r695 r696 55 55 56 56 Uses('caba:vci_multi_dma', 57 cell_size = parameter.Reference('vci_data_width_int')), 58 59 Uses('caba:vci_local_crossbar', 57 60 cell_size = parameter.Reference('vci_data_width_int')), 58 61 -
branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r695 r696 23 23 #include "vci_simple_rom.h" 24 24 #include "vci_xicu.h" 25 #include "vci_local_crossbar.h" 25 26 #include "dspin_local_crossbar.h" 26 27 #include "vci_dspin_initiator_wrapper.h" … … 119 120 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 120 121 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 122 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 123 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 121 124 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 122 125 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 123 126 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 124 127 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 125 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d;126 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d;127 128 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 128 129 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 129 130 130 // INT network VCI signals between VCI components and VCI /DSPIN wrappers131 // INT network VCI signals between VCI components and VCI local crossbar 131 132 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 132 133 VciSignals<vci_param_int> signal_int_vci_ini_mdma; … … 140 141 VciSignals<vci_param_int> signal_int_vci_tgt_iobx; 141 142 142 // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN 143 // wrappers 144 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_proc_i[8]; 145 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_proc_i[8]; 146 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_i; 147 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_i; 148 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_i; 149 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_i; 150 151 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_memc_t; 152 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_memc_t; 153 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_xicu_t; 154 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_xicu_t; 155 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_brom_t; 156 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_brom_t; 157 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mtty_t; 158 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mtty_t; 159 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_mdma_t; 160 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_mdma_t; 161 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_iobx_t; 162 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_iobx_t; 143 VciSignals<vci_param_int> signal_int_vci_l2g; 144 VciSignals<vci_param_int> signal_int_vci_g2l; 163 145 164 146 // Coherence DSPIN signals between DSPIN local crossbars and CC … … 205 187 206 188 VciCcVCacheWrapperType* proc[8]; 207 VciIntDspinInitiatorWrapperType* proc_wi[8];208 189 209 190 VciMemCacheType* memc; 210 VciIntDspinTargetWrapperType* memc_int_wt;211 191 VciExtDspinInitiatorWrapperType* memc_ram_wi; 212 192 213 193 VciXicu<vci_param_int>* xicu; 214 VciIntDspinTargetWrapperType* xicu_int_wt;215 194 216 195 VciMultiDma<vci_param_int>* mdma; 217 VciIntDspinInitiatorWrapperType* mdma_int_wi;218 VciIntDspinTargetWrapperType* mdma_int_wt;219 196 220 197 VciSimpleRom<vci_param_int>* brom; 221 VciIntDspinTargetWrapperType* brom_int_wt;222 198 223 199 VciMultiTty<vci_param_int>* mtty; 224 VciIntDspinTargetWrapperType* mtty_int_wt; 225 226 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_cmd_d; 227 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_rsp_d; 200 201 VciLocalCrossbar<vci_param_int>* int_xbar_d; 202 VciIntDspinInitiatorWrapperType* int_wi_gate_d; 203 VciIntDspinTargetWrapperType* int_wt_gate_d; 204 228 205 DspinLocalCrossbar<dspin_int_cmd_width>* int_xbar_m2p_c; 229 206 DspinLocalCrossbar<dspin_int_rsp_width>* int_xbar_p2m_c; … … 242 219 243 220 VciIoBridge<vci_param_int, vci_param_ext>* iob; 244 VciIntDspinInitiatorWrapperType* iob_int_wi;245 VciIntDspinTargetWrapperType* iob_int_wt;246 221 VciExtDspinInitiatorWrapperType* iob_ram_wi; 247 222 -
branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r695 r696 112 112 proc[p]->set_dcache_paddr_ext_reset(cid); 113 113 proc[p]->set_icache_paddr_ext_reset(cid); 114 115 std::ostringstream s_wi_proc;116 s_wi_proc << "proc_wi_" << params.x_id << "_" << params.y_id << "_" << p;117 proc_wi[p] = new VciIntDspinInitiatorWrapperType(118 s_wi_proc.str().c_str(),119 vci_param_int::S);120 114 } 121 115 … … 138 132 params.memc_debug_ok); 139 133 140 std::ostringstream s_wt_memc;141 s_wt_memc << "memc_wt_" << params.x_id << "_" << params.y_id;142 memc_int_wt = new VciIntDspinTargetWrapperType (143 s_wt_memc.str().c_str(),144 vci_param_int::S);145 146 134 std::ostringstream s_wi_memc; 147 135 s_wi_memc << "memc_wi_" << params.x_id << "_" << params.y_id; … … 160 148 X_WIDTH + Y_WIDTH); 161 149 162 std::ostringstream s_wt_brom;163 s_wt_brom << "brom_wt_" << params.x_id << "_" << params.y_id;164 brom_int_wt = new VciIntDspinTargetWrapperType (165 s_wt_brom.str().c_str(),166 vci_param_int::S);167 168 150 // Multi-TTY controller 169 151 mtty = NULL; 170 mtty_int_wt = NULL;171 152 if (NB_DEBUG_TTY_CHANNELS) { 172 153 assert(NB_DEBUG_TTY_CHANNELS < 8); … … 185 166 params.mt_int, 186 167 vect_names); 187 188 std::ostringstream s_wt_mtty;189 s_wt_mtty << "mtty_wt_" << params.x_id << "_" << params.y_id;190 mtty_int_wt = new VciIntDspinTargetWrapperType (191 s_wt_mtty.str().c_str(),192 vci_param_int::S);193 168 } 194 169 … … 203 178 NB_PROCS); 204 179 205 std::ostringstream s_wt_xicu;206 s_wt_xicu << "xicu_wt_" << params.x_id << "_" << params.y_id;207 xicu_int_wt = new VciIntDspinTargetWrapperType (208 s_wt_xicu.str().c_str(),209 vci_param_int::S);210 211 180 //////////// MDMA 212 181 std::ostringstream s_mdma; … … 220 189 NB_DMA_CHANNELS); 221 190 222 std::ostringstream s_wt_mdma;223 s_wt_mdma << "mdma_wt_" << params.x_id << "_" << params.y_id;224 mdma_int_wt = new VciIntDspinTargetWrapperType(225 s_wt_mdma.str().c_str(),226 vci_param_int::S);227 228 std::ostringstream s_wi_mdma;229 s_wi_mdma << "mdma_wi_" << params.x_id << "_" << params.y_id;230 mdma_int_wi = new VciIntDspinInitiatorWrapperType(231 s_wi_mdma.str().c_str(),232 vci_param_int::S);233 234 191 /////////// Direct LOCAL_XBAR(S) 235 192 size_t nb_direct_initiators = NB_PROCS + 1; … … 243 200 } 244 201 245 std::ostringstream s_int_xbar_cmd_d; 246 s_int_xbar_cmd_d << "int_xbar_cmd_d_" << params.x_id << "_" << params.y_id; 247 int_xbar_cmd_d = new DspinLocalCrossbar<dspin_int_cmd_width>( 248 s_int_xbar_cmd_d.str().c_str(), 249 params.mt_int, 250 params.x_id, params.y_id, 251 X_WIDTH, Y_WIDTH, l_width, 202 std::ostringstream s_int_xbar_d; 203 s_int_xbar_d << "int_xbar_cmd_d_" << params.x_id << "_" << params.y_id; 204 int_xbar_d = new VciLocalCrossbar<vci_param_int>( 205 s_int_xbar_d.str().c_str(), 206 params.mt_int, 207 cid, 252 208 nb_direct_initiators, 253 209 nb_direct_targets, 254 2, 2, 255 true, 256 true, 257 false); 258 259 std::ostringstream s_int_xbar_rsp_d; 260 s_int_xbar_rsp_d << "int_xbar_rsp_d_" << params.x_id << "_" << params.y_id; 261 int_xbar_rsp_d = new DspinLocalCrossbar<dspin_int_rsp_width>( 262 s_int_xbar_rsp_d.str().c_str(), 263 params.mt_int, 264 params.x_id, params.y_id, 265 X_WIDTH, Y_WIDTH, l_width, 266 nb_direct_targets, 267 nb_direct_initiators, 268 2, 2, 269 false, 270 false, 271 false); 210 0 ); 211 212 std::ostringstream s_int_dspin_ini_wrapper_gate_d; 213 s_int_dspin_ini_wrapper_gate_d 214 << "int_dspin_ini_wrapper_gate_d_" << params.x_id << "_" << params.y_id; 215 int_wi_gate_d = new VciIntDspinInitiatorWrapperType( 216 s_int_dspin_ini_wrapper_gate_d.str().c_str(), 217 X_WIDTH + Y_WIDTH + l_width); 218 219 std::ostringstream s_int_dspin_tgt_wrapper_gate_d; 220 s_int_dspin_tgt_wrapper_gate_d 221 << "int_dspin_tgt_wrapper_gate_d_" << params.x_id << "_" << params.y_id; 222 int_wt_gate_d = new VciIntDspinTargetWrapperType( 223 s_int_dspin_tgt_wrapper_gate_d.str().c_str(), 224 X_WIDTH + Y_WIDTH + l_width); 272 225 273 226 //////////// Coherence LOCAL_XBAR(S) … … 375 328 ////////////////////// I/O CLUSTER ONLY /////////////////////// 376 329 iob = NULL; 377 iob_int_wi = NULL;378 iob_int_wt = NULL;379 330 iob_ram_wi = NULL; 380 331 if ( is_io_cluster ) { … … 408 359 params.iob_debug_ok ); 409 360 410 std::ostringstream s_iob_int_wi;411 s_iob_int_wi << "iob_int_wi_" << params.x_id << "_" << params.y_id;412 iob_int_wi = new VciIntDspinInitiatorWrapperType(413 s_iob_int_wi.str().c_str(),414 vci_param_int::S);415 416 std::ostringstream s_iob_int_wt;417 s_iob_int_wt << "iob_int_wt_" << params.x_id << "_" << params.y_id;418 iob_int_wt = new VciIntDspinTargetWrapperType(419 s_iob_int_wt.str().c_str(),420 vci_param_int::S);421 422 361 std::ostringstream s_iob_ram_wi; 423 362 s_iob_ram_wi << "iob_ram_wi_" << params.x_id << "_" << params.y_id; … … 467 406 int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); 468 407 469 ///////////////////// CMD DSPINlocal crossbar direct470 int_xbar_ cmd_d->p_clk(this->p_clk);471 int_xbar_ cmd_d->p_resetn(this->p_resetn);472 int_xbar_ cmd_d->p_global_out (signal_int_dspin_cmd_l2g_d);473 int_xbar_ cmd_d->p_global_in (signal_int_dspin_cmd_g2l_d);474 475 int_xbar_ cmd_d->p_local_out[INT_MEMC_TGT_ID] (signal_int_dspin_cmd_memc_t);476 int_xbar_ cmd_d->p_local_out[INT_XICU_TGT_ID] (signal_int_dspin_cmd_xicu_t);477 int_xbar_ cmd_d->p_local_out[INT_BROM_TGT_ID] (signal_int_dspin_cmd_brom_t);478 int_xbar_ cmd_d->p_local_out[INT_MDMA_TGT_ID] (signal_int_dspin_cmd_mdma_t);408 ///////////////////// CMD & RSP VCI local crossbar direct 409 int_xbar_d->p_clk (this->p_clk); 410 int_xbar_d->p_resetn (this->p_resetn); 411 int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); 412 int_xbar_d->p_target_to_up (signal_int_vci_g2l); 413 414 int_xbar_d->p_to_target[INT_MEMC_TGT_ID] (signal_int_vci_tgt_memc); 415 int_xbar_d->p_to_target[INT_XICU_TGT_ID] (signal_int_vci_tgt_xicu); 416 int_xbar_d->p_to_target[INT_BROM_TGT_ID] (signal_int_vci_tgt_brom); 417 int_xbar_d->p_to_target[INT_MDMA_TGT_ID] (signal_int_vci_tgt_mdma); 479 418 if (NB_DEBUG_TTY_CHANNELS) { 480 int_xbar_cmd_d->p_local_out[INT_MTTY_TGT_ID] (signal_int_dspin_cmd_mtty_t); 481 } 482 int_xbar_cmd_d->p_local_in[INT_MDMA_INI_ID] (signal_int_dspin_cmd_mdma_i); 483 419 int_xbar_d->p_to_target[INT_MTTY_TGT_ID] (signal_int_vci_tgt_mtty); 420 } 421 int_xbar_d->p_to_initiator[INT_MDMA_INI_ID] (signal_int_vci_ini_mdma); 484 422 for (size_t p = 0; p < NB_PROCS; p++) { 485 int_xbar_ cmd_d->p_local_in[INT_PROC_INI_ID + p](486 signal_int_ dspin_cmd_proc_i[p]);423 int_xbar_d->p_to_initiator[INT_PROC_INI_ID + p]( 424 signal_int_vci_ini_proc[p]); 487 425 } 488 426 489 427 if ( is_io_cluster ) { 490 int_xbar_cmd_d->p_local_out[INT_IOBX_TGT_ID]( 491 signal_int_dspin_cmd_iobx_t); 492 int_xbar_cmd_d->p_local_in[INT_IOBX_INI_ID]( 493 signal_int_dspin_cmd_iobx_i); 494 } 495 496 //////////////////////// RSP DSPIN local crossbar direct 497 int_xbar_rsp_d->p_clk (this->p_clk); 498 int_xbar_rsp_d->p_resetn (this->p_resetn); 499 int_xbar_rsp_d->p_global_out (signal_int_dspin_rsp_l2g_d); 500 int_xbar_rsp_d->p_global_in (signal_int_dspin_rsp_g2l_d); 501 502 int_xbar_rsp_d->p_local_in[INT_MEMC_TGT_ID] (signal_int_dspin_rsp_memc_t); 503 int_xbar_rsp_d->p_local_in[INT_XICU_TGT_ID] (signal_int_dspin_rsp_xicu_t); 504 int_xbar_rsp_d->p_local_in[INT_BROM_TGT_ID] (signal_int_dspin_rsp_brom_t); 505 if (NB_DEBUG_TTY_CHANNELS) { 506 int_xbar_rsp_d->p_local_in[INT_MTTY_TGT_ID] (signal_int_dspin_rsp_mtty_t); 507 } 508 int_xbar_rsp_d->p_local_in[INT_MDMA_TGT_ID] (signal_int_dspin_rsp_mdma_t); 509 510 int_xbar_rsp_d->p_local_out[INT_MDMA_INI_ID](signal_int_dspin_rsp_mdma_i); 511 for (size_t p = 0; p < NB_PROCS; p++) 512 int_xbar_rsp_d->p_local_out[INT_PROC_INI_ID + p]( 513 signal_int_dspin_rsp_proc_i[p]); 514 515 if ( is_io_cluster ) { 516 int_xbar_rsp_d->p_local_in[INT_IOBX_TGT_ID]( 517 signal_int_dspin_rsp_iobx_t); 518 int_xbar_rsp_d->p_local_out[INT_IOBX_INI_ID]( 519 signal_int_dspin_rsp_iobx_i); 520 } 521 428 int_xbar_d->p_to_target[INT_IOBX_TGT_ID] (signal_int_vci_tgt_iobx); 429 int_xbar_d->p_to_initiator[INT_IOBX_INI_ID] (signal_int_vci_ini_iobx); 430 } 431 432 int_wi_gate_d->p_clk (this->p_clk); 433 int_wi_gate_d->p_resetn (this->p_resetn); 434 int_wi_gate_d->p_vci (signal_int_vci_l2g); 435 int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); 436 int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); 437 438 int_wt_gate_d->p_clk (this->p_clk); 439 int_wt_gate_d->p_resetn (this->p_resetn); 440 int_wt_gate_d->p_vci (signal_int_vci_g2l); 441 int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); 442 int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); 443 522 444 ////////////////////// M2P DSPIN local crossbar coherence 523 445 int_xbar_m2p_c->p_clk (this->p_clk); … … 562 484 proc[p]->p_irq[j] (signal_false); 563 485 } 564 565 proc_wi[p]->p_clk (this->p_clk);566 proc_wi[p]->p_resetn (this->p_resetn);567 proc_wi[p]->p_dspin_cmd (signal_int_dspin_cmd_proc_i[p]);568 proc_wi[p]->p_dspin_rsp (signal_int_dspin_rsp_proc_i[p]);569 proc_wi[p]->p_vci (signal_int_vci_ini_proc[p]);570 486 } 571 487 … … 583 499 xicu->p_hwi[i] (signal_false); 584 500 } 585 586 // wrapper XICU587 xicu_int_wt->p_clk (this->p_clk);588 xicu_int_wt->p_resetn (this->p_resetn);589 xicu_int_wt->p_dspin_cmd (signal_int_dspin_cmd_xicu_t);590 xicu_int_wt->p_dspin_rsp (signal_int_dspin_rsp_xicu_t);591 xicu_int_wt->p_vci (signal_int_vci_tgt_xicu);592 501 593 502 ///////////////////////////////////// MEMC … … 601 510 memc->p_irq (signal_irq_memc); 602 511 603 // wrapper to INT network604 memc_int_wt->p_clk (this->p_clk);605 memc_int_wt->p_resetn (this->p_resetn);606 memc_int_wt->p_dspin_cmd (signal_int_dspin_cmd_memc_t);607 memc_int_wt->p_dspin_rsp (signal_int_dspin_rsp_memc_t);608 memc_int_wt->p_vci (signal_int_vci_tgt_memc);609 610 512 // wrapper to RAM network 611 513 memc_ram_wi->p_clk (this->p_clk); … … 620 522 brom->p_vci (signal_int_vci_tgt_brom); 621 523 622 //wrapper to INT network623 brom_int_wt->p_clk (this->p_clk);624 brom_int_wt->p_resetn (this->p_resetn);625 brom_int_wt->p_dspin_cmd (signal_int_dspin_cmd_brom_t);626 brom_int_wt->p_dspin_rsp (signal_int_dspin_rsp_brom_t);627 brom_int_wt->p_vci (signal_int_vci_tgt_brom);628 629 524 if (NB_DEBUG_TTY_CHANNELS) { 630 525 //////////////////////////////////// MTTY … … 636 531 mtty->p_irq[i] (signal_irq_mtty[i]); 637 532 } 638 639 //wrapper to INT network640 mtty_int_wt->p_clk (this->p_clk);641 mtty_int_wt->p_resetn (this->p_resetn);642 mtty_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mtty_t);643 mtty_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mtty_t);644 mtty_int_wt->p_vci (signal_int_vci_tgt_mtty);645 533 } 646 534 … … 664 552 for (size_t i = 0 ; i < NB_DMA_CHANNELS ; i++) 665 553 mdma->p_irq[i] (signal_irq_mdma[i]); 666 667 // target wrapper668 mdma_int_wt->p_clk (this->p_clk);669 mdma_int_wt->p_resetn (this->p_resetn);670 mdma_int_wt->p_dspin_cmd (signal_int_dspin_cmd_mdma_t);671 mdma_int_wt->p_dspin_rsp (signal_int_dspin_rsp_mdma_t);672 mdma_int_wt->p_vci (signal_int_vci_tgt_mdma);673 674 // initiator wrapper675 mdma_int_wi->p_clk (this->p_clk);676 mdma_int_wi->p_resetn (this->p_resetn);677 mdma_int_wi->p_dspin_cmd (signal_int_dspin_cmd_mdma_i);678 mdma_int_wi->p_dspin_rsp (signal_int_dspin_rsp_mdma_i);679 mdma_int_wi->p_vci (signal_int_vci_ini_mdma);680 554 681 555 //////////////////////////// RAM network CMD & RSP routers … … 706 580 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); 707 581 708 if ( is_iob0 ) 709 for ( size_t n = 0 ; n < 32 ; n++ ) 582 if ( is_iob0 ) { 583 for ( size_t n = 0 ; n < 32 ; n++ ) { 710 584 (*iob->p_irq[n]) (*(this->p_irq[n])); 585 } 586 } 711 587 712 588 // initiator wrapper to RAM network … … 716 592 iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); 717 593 iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); 718 719 // initiator wrapper to INT network720 iob_int_wi->p_clk (this->p_clk);721 iob_int_wi->p_resetn (this->p_resetn);722 iob_int_wi->p_dspin_cmd (signal_int_dspin_cmd_iobx_i);723 iob_int_wi->p_dspin_rsp (signal_int_dspin_rsp_iobx_i);724 iob_int_wi->p_vci (signal_int_vci_ini_iobx);725 726 // target wrapper to INT network727 iob_int_wt->p_clk (this->p_clk);728 iob_int_wt->p_resetn (this->p_resetn);729 iob_int_wt->p_dspin_cmd (signal_int_dspin_cmd_iobx_t);730 iob_int_wt->p_dspin_rsp (signal_int_dspin_rsp_iobx_t);731 iob_int_wt->p_vci (signal_int_vci_tgt_iobx);732 594 } 733 595 } // end constructor … … 739 601 if (p_dspin_iob_rsp_in) delete p_dspin_iob_rsp_in; 740 602 if (iob) delete iob; 741 if (iob_int_wi) delete iob_int_wi;742 if (iob_int_wt) delete iob_int_wt;743 603 if (iob_ram_wi) delete iob_ram_wi; 744 604 … … 749 609 for (size_t p = 0; p < NB_PROCS; p++) { 750 610 delete proc[p]; 751 delete proc_wi[p];752 611 } 753 612 754 613 delete memc; 755 delete memc_int_wt;756 614 delete memc_ram_wi; 757 615 delete xicu; 758 delete xicu_int_wt;759 616 delete brom; 760 delete brom_int_wt;761 617 delete mtty; 762 delete mtty_int_wt;763 618 delete mdma; 764 delete mdma_int_wt; 765 delete mdma_int_wi; 766 delete int_xbar_cmd_d; 767 delete int_xbar_rsp_d; 619 delete int_xbar_d; 768 620 delete int_xbar_m2p_c; 769 621 delete int_xbar_p2m_c;
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