Changeset 700 for branches/MESI/modules/vci_mem_cache
- Timestamp:
- May 20, 2014, 2:43:42 PM (11 years ago)
- Location:
- branches/MESI/modules/vci_mem_cache/caba/source
- Files:
-
- 2 edited
-
include/vci_mem_cache.h (modified) (12 diffs)
-
src/vci_mem_cache.cpp (modified) (76 diffs)
Legend:
- Unmodified
- Added
- Removed
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branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r686 r700 290 290 CAS_DIR_HIT_COMPARE, 291 291 CAS_DIR_HIT_WRITE, 292 CAS_ MULTI_INVAL_IVT_LOCK,292 CAS_INVAL_IVT_LOCK, 293 293 CAS_WAIT, 294 294 CAS_MULTI_INVAL_HEAP_LOCK, … … 296 296 CAS_HEAP_NEXT, 297 297 CAS_HEAP_LAST, 298 CAS_BC_TRT_LOCK,299 CAS_BC_IVT_LOCK,300 CAS_BC_DIR_INVAL,301 CAS_BC_CC_SEND,302 CAS_BC_XRAM_REQ,303 298 CAS_RSP_FAIL, 304 299 CAS_RSP_SUCCESS, … … 361 356 }; 362 357 363 // /* States of the ALLOC_UPT fsm */364 // enum alloc_upt_fsm_state_e365 // {366 // ALLOC_UPT_WRITE,367 // ALLOC_UPT_CAS,368 // ALLOC_UPT_MULTI_ACK369 // };370 //371 358 /* States of the ALLOC_IVT fsm */ 372 359 enum alloc_ivt_fsm_state_e … … 435 422 // Counters accessible in software (not yet but eventually) 436 423 uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset 437 uint32_t m_cpt_read_local; // Number of local READ transactions 438 uint32_t m_cpt_read_remote; // number of remote READ transactions 439 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs 424 uint32_t m_cpt_read_miss_local; // Number of local READ transactions 425 uint32_t m_cpt_read_miss_remote; // number of remote READ transactions 426 uint32_t m_cpt_read_miss_cost; // Number of (flits * distance) for READs 427 428 uint32_t m_cpt_getm_miss_local; // Number of local getm miss transactions 429 uint32_t m_cpt_getm_miss_remote; // number of remote getm miss transactions 430 431 uint32_t m_cpt_getm_hit_local; // Number of local getm hit transactions 432 uint32_t m_cpt_getm_hit_remote; // number of remote getm hit transactions 433 uint32_t m_cpt_getm_cost; // Number of (flits * distance) for getm 440 434 441 435 uint32_t m_cpt_write_local; // Number of local WRITE transactions … … 471 465 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions 472 466 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions 467 uint32_t m_cpt_cleanup_with_data; 473 468 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs 474 469 470 uint32_t m_cpt_multi_ack_miss; // Number of local CLEANUP transactions 471 uint32_t m_cpt_multi_ack_hit; // Number of local CLEANUP transactions 472 uint32_t m_cpt_multi_ack_hit_with_data; // Number of remote CLEANUP transactions 473 475 474 // Counters not accessible by software 476 475 uint32_t m_cpt_read_miss; // Number of MISS READ 477 uint32_t m_cpt_write_miss; // Number of MISS WRITE 478 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 476 uint32_t m_cpt_getm_miss; // Number of getm miss 477 uint32_t m_cpt_getm_broadcast; // Number of BROADCAST INVAL because getm 478 uint32_t m_cpt_getm_minval; // Number of MULTI INVAL because getm 479 uint32_t m_cpt_write_miss; // Number of MISS WRITE 480 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 479 481 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write 482 uint32_t m_cpt_write_minval; // Number of MULTI INVAL because write 483 uint32_t m_cpt_cas_broadcast; // Number of BROADCAST INVAL because cas 484 uint32_t m_cpt_cas_minval; // Number of MULTI INVAL because cas 485 uint32_t m_cpt_cas_miss; 486 487 uint32_t m_cpt_read_locked_rb; // Read blocked by a locked ligne 488 uint32_t m_cpt_cas_locked_rb; // cas blocked by a locked ligne 489 uint32_t m_cpt_write_locked_rb; // wt blocked by a locked ligne 480 490 481 491 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt … … 492 502 uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK 493 503 uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK 494 504 uint32_t m_cpt_multi_ack_fsm_dir_lock; // wait DIR LOCK 505 uint32_t m_cpt_multi_ack_fsm_n_dir_lock; // NB DIR LOCK 506 495 507 uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused 496 508 uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used … … 499 511 uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used 500 512 uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used 513 uint32_t m_cpt_multi_ack_fsm_dir_used; // NB cycles DIR LOCK used 501 514 502 515 uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK … … 510 523 uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK 511 524 uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK 512 uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK 525 uint32_t m_cpt_ixr_cmd_fsm_n_trt_lock; // NB TRT LOCK 526 uint32_t m_cpt_ixr_rsp_fsm_n_trt_lock; // NB TRT LOCK 513 527 514 528 uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used … … 516 530 uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used 517 531 uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used 518 uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used 532 uint32_t m_cpt_ixr_cmd_fsm_trt_used; // NB cycles TRT LOCK used 533 uint32_t m_cpt_ixr_rsp_fsm_trt_used; // NB cycles TRT LOCK used 534 uint32_t m_cpt_cleanup_fsm_trt_used; // NB cycles TRT LOCK used 519 535 520 536 uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused 521 537 522 uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK 523 uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK 524 uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK 525 uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait UPT LOCK 526 uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK 538 uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait ivt LOCK 539 uint32_t m_cpt_cleanup_fsm_n_ivt_lock; // NB cycles UPT LOCK used 527 540 528 uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK 529 uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK 530 uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK 531 uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK 532 uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK 533 534 uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used 535 uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used 536 uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used 537 uint32_t m_cpt_cleanup_fsm_ivt_used; // NB cycles UPT LOCK used 538 uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used 539 541 uint32_t m_cpt_multi_ack_fsm_ivt_lock; // wait ivt LOCK 542 uint32_t m_cpt_multi_ack_fsm_n_ivt_lock; // NB cycles UPT LOCK used 543 540 544 uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused 541 uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused542 545 543 546 uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK … … 546 549 uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK 547 550 uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK 551 uint32_t m_cpt_multi_ack_fsm_heap_lock; // wait HEAP LOCK 548 552 549 553 uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK … … 552 556 uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK 553 557 uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK 558 uint32_t m_cpt_multi_ack_fsm_n_heap_lock; // NB HEAP LOCK 554 559 555 560 uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used … … 558 563 uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used 559 564 uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used 565 uint32_t m_cpt_multi_ack_fsm_heap_used; // NB cycles HEAP LOCK used 560 566 561 567 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 562 563 //RWT 564 uint32_t m_cpt_cleanup_data; 565 uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ 566 uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE 567 uint32_t m_cpt_ncc_to_cc; // NB change from NCC to CC 568 569 uint32_t m_cpt_read_data_unc; 570 uint32_t m_cpt_read_data_miss_CC; 571 uint32_t m_cpt_read_ins_unc; 572 uint32_t m_cpt_read_ins_miss; 573 uint32_t m_cpt_read_ll_CC; 574 uint32_t m_cpt_read_data_miss_NCC; 575 uint32_t m_cpt_read_ll_NCC; 576 uint32_t m_cpt_read_WTF; 577 578 uint32_t m_cpt_update_flits; // Number of flits for UPDATEs 579 uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs 580 581 uint32_t m_cpt_get; 582 uint32_t m_cpt_put; 583 584 size_t m_prev_count; 568 uint32_t m_cpt_slot_inval; 585 569 586 570 protected: -
branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r686 r700 250 250 "CAS_DIR_HIT_COMPARE", 251 251 "CAS_DIR_HIT_WRITE", 252 "CAS_ MULTI_INVAL_IVT_LOCK",252 "CAS_INVAL_IVT_LOCK", 253 253 "CAS_WAIT", 254 254 "CAS_MULTI_INVAL_HEAP_LOCK", … … 256 256 "CAS_HEAP_NEXT", 257 257 "CAS_HEAP_LAST", 258 "CAS_BC_TRT_LOCK",259 "CAS_BC_IVT_LOCK",260 "CAS_BC_DIR_INVAL",261 "CAS_BC_CC_SEND",262 "CAS_BC_XRAM_REQ",263 258 "CAS_RSP_FAIL", 264 259 "CAS_RSP_SUCCESS", … … 314 309 "ALLOC_TRT_CONFIG" 315 310 }; 316 // const char *alloc_upt_fsm_str[] = 317 // { 318 // "ALLOC_UPT_WRITE", 319 // "ALLOC_UPT_CAS", 320 // "ALLOC_UPT_MULTI_ACK" 321 // }; 311 322 312 const char *alloc_ivt_fsm_str[] = 323 313 { … … 716 706 // LOCAL 717 707 718 case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_ local; break;708 case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_miss_local ; break; 719 709 case MEMC_LOCAL_WRITE_LO : rdata = m_cpt_write_flits_local ; break; 720 710 case MEMC_LOCAL_LL_LO : rdata = m_cpt_ll_local ; break; … … 729 719 // REMOTE 730 720 731 case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_ remote; break;721 case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_miss_remote ; break; 732 722 case MEMC_REMOTE_WRITE_LO : rdata = m_cpt_write_flits_remote ; break; 733 723 case MEMC_REMOTE_LL_LO : rdata = m_cpt_ll_remote ; break; … … 742 732 // COST 743 733 744 case MEMC_COST_READ_LO : rdata = m_cpt_read_ cost ; break;734 case MEMC_COST_READ_LO : rdata = m_cpt_read_miss_cost ; break; 745 735 case MEMC_COST_WRITE_LO : rdata = m_cpt_write_cost; break; 746 736 case MEMC_COST_LL_LO : rdata = m_cpt_ll_cost ; break; … … 838 828 { 839 829 m_cpt_reset_count = m_cpt_cycles; 840 m_cpt_read_local = 0; 841 m_cpt_read_remote = 0; 842 m_cpt_read_cost = 0; 843 m_cpt_write_local = 0; 844 m_cpt_write_remote = 0; 845 m_cpt_write_flits_local = 0; 846 m_cpt_write_flits_remote = 0; 847 m_cpt_write_cost = 0; 848 m_cpt_ll_local = 0; 849 m_cpt_ll_remote = 0; 850 m_cpt_ll_cost = 0; 851 m_cpt_sc_local = 0; 852 m_cpt_sc_remote = 0; 853 m_cpt_sc_cost = 0; 854 m_cpt_cas_local = 0; 855 m_cpt_cas_remote = 0; 856 m_cpt_cas_cost = 0; 857 m_cpt_update = 0; 858 m_cpt_update_local = 0; 859 m_cpt_update_remote = 0; 860 m_cpt_update_cost = 0; 861 m_cpt_minval = 0; 862 m_cpt_minval_local = 0; 863 m_cpt_minval_remote = 0; 864 m_cpt_minval_cost = 0; 865 m_cpt_binval = 0; 866 m_cpt_cleanup_local = 0; 867 m_cpt_cleanup_remote = 0; 868 m_cpt_cleanup_cost = 0; 869 m_cpt_read_miss = 0; 870 m_cpt_write_miss = 0; 871 m_cpt_write_dirty = 0; 872 m_cpt_trt_rb = 0; 873 m_cpt_trt_full = 0; 874 m_cpt_get = 0; 875 m_cpt_put = 0; 876 m_cpt_ncc_to_cc_read = 0; 877 m_cpt_ncc_to_cc_write = 0; 878 m_cpt_ncc_to_cc = 0; 830 831 m_cpt_read_miss_local = 0 ; 832 m_cpt_read_miss_remote = 0 ; 833 m_cpt_read_miss_cost = 0 ; 834 835 m_cpt_getm_miss_local = 0 ; 836 m_cpt_getm_miss_remote = 0 ; 837 838 m_cpt_getm_hit_local = 0 ; 839 m_cpt_getm_hit_remote = 0 ; 840 m_cpt_getm_cost = 0 ; 841 842 m_cpt_write_local = 0 ; 843 m_cpt_write_remote = 0 ; 844 m_cpt_write_flits_local = 0 ; 845 m_cpt_write_flits_remote = 0 ; 846 m_cpt_write_cost = 0 ; 847 848 m_cpt_ll_local = 0 ; 849 m_cpt_ll_remote = 0 ; 850 m_cpt_ll_cost = 0 ; 851 852 m_cpt_sc_local = 0 ; 853 m_cpt_sc_remote = 0 ; 854 m_cpt_sc_cost = 0 ; 855 856 m_cpt_cas_local = 0 ; 857 m_cpt_cas_remote = 0 ; 858 m_cpt_cas_cost = 0 ; 859 860 m_cpt_update = 0 ; 861 m_cpt_update_local = 0 ; 862 m_cpt_update_remote = 0 ; 863 m_cpt_update_cost = 0 ; 864 865 m_cpt_minval = 0 ; 866 m_cpt_minval_local = 0 ; 867 m_cpt_minval_remote = 0 ; 868 m_cpt_minval_cost = 0 ; 869 870 m_cpt_binval = 0 ; 871 872 m_cpt_cleanup_local = 0 ; 873 m_cpt_cleanup_remote = 0 ; 874 m_cpt_cleanup_with_data = 0 ; 875 m_cpt_cleanup_cost = 0 ; 876 877 m_cpt_multi_ack_miss = 0 ; 878 m_cpt_multi_ack_hit = 0 ; 879 m_cpt_multi_ack_hit_with_data = 0 ; 880 881 882 m_cpt_read_miss = 0 ; 883 m_cpt_getm_miss = 0 ; 884 m_cpt_getm_broadcast = 0 ; 885 m_cpt_getm_minval = 0 ; 886 m_cpt_write_miss = 0 ; 887 m_cpt_write_dirty = 0 ; 888 m_cpt_write_broadcast = 0 ; 889 m_cpt_write_minval = 0 ; 890 m_cpt_cas_broadcast = 0 ; 891 m_cpt_cas_minval = 0 ; 892 m_cpt_cas_miss = 0 ; 893 894 m_cpt_read_locked_rb = 0 ; 895 m_cpt_cas_locked_rb = 0 ; 896 m_cpt_write_locked_rb = 0 ; 897 898 m_cpt_trt_rb = 0 ; 899 m_cpt_trt_full = 0 ; 900 901 m_cpt_read_fsm_dir_lock = 0 ; 902 m_cpt_read_fsm_n_dir_lock = 0 ; 903 m_cpt_write_fsm_dir_lock = 0 ; 904 m_cpt_write_fsm_n_dir_lock = 0 ; 905 m_cpt_xram_rsp_fsm_dir_lock = 0 ; 906 m_cpt_xram_rsp_fsm_n_dir_lock = 0 ; 907 m_cpt_cas_fsm_dir_lock = 0 ; 908 m_cpt_cas_fsm_n_dir_lock = 0 ; 909 m_cpt_cleanup_fsm_dir_lock = 0 ; 910 m_cpt_cleanup_fsm_n_dir_lock = 0 ; 911 m_cpt_multi_ack_fsm_dir_lock = 0 ; 912 m_cpt_multi_ack_fsm_n_dir_lock = 0 ; 913 914 m_cpt_dir_unused = 0 ; 915 m_cpt_read_fsm_dir_used = 0 ; 916 m_cpt_write_fsm_dir_used = 0 ; 917 m_cpt_cas_fsm_dir_used = 0 ; 918 m_cpt_xram_rsp_fsm_dir_used = 0 ; 919 m_cpt_cleanup_fsm_dir_used = 0 ; 920 m_cpt_multi_ack_fsm_dir_used = 0 ; 921 922 m_cpt_read_fsm_trt_lock = 0 ; 923 m_cpt_write_fsm_trt_lock = 0 ; 924 m_cpt_cas_fsm_trt_lock = 0 ; 925 m_cpt_xram_rsp_fsm_trt_lock = 0 ; 926 m_cpt_ixr_fsm_trt_lock = 0 ; 927 928 m_cpt_read_fsm_n_trt_lock = 0 ; 929 m_cpt_write_fsm_n_trt_lock = 0 ; 930 m_cpt_cas_fsm_n_trt_lock = 0 ; 931 m_cpt_xram_rsp_fsm_n_trt_lock = 0 ; 932 m_cpt_ixr_cmd_fsm_n_trt_lock = 0 ; 933 m_cpt_ixr_rsp_fsm_n_trt_lock = 0 ; 934 935 m_cpt_read_fsm_trt_used = 0 ; 936 m_cpt_write_fsm_trt_used = 0 ; 937 m_cpt_cas_fsm_trt_used = 0 ; 938 m_cpt_xram_rsp_fsm_trt_used = 0 ; 939 m_cpt_ixr_cmd_fsm_trt_used = 0 ; 940 m_cpt_ixr_rsp_fsm_trt_used = 0 ; 941 m_cpt_cleanup_fsm_trt_used = 0 ; 942 943 m_cpt_trt_unused = 0 ; 944 945 m_cpt_cleanup_fsm_ivt_lock = 0 ; 946 m_cpt_cleanup_fsm_n_ivt_lock = 0 ; 947 948 m_cpt_multi_ack_fsm_ivt_lock = 0 ; 949 m_cpt_multi_ack_fsm_n_ivt_lock = 0 ; 950 951 m_cpt_ivt_unused = 0 ; 952 953 m_cpt_read_fsm_heap_lock = 0 ; 954 m_cpt_write_fsm_heap_lock = 0 ; 955 m_cpt_cas_fsm_heap_lock = 0 ; 956 m_cpt_cleanup_fsm_heap_lock = 0 ; 957 m_cpt_xram_rsp_fsm_heap_lock = 0 ; 958 m_cpt_multi_ack_fsm_heap_lock = 0 ; 959 960 m_cpt_read_fsm_n_heap_lock = 0 ; 961 m_cpt_write_fsm_n_heap_lock = 0 ; 962 m_cpt_cas_fsm_n_heap_lock = 0 ; 963 m_cpt_cleanup_fsm_n_heap_lock = 0 ; 964 m_cpt_xram_rsp_fsm_n_heap_lock = 0 ; 965 m_cpt_multi_ack_fsm_n_heap_lock = 0 ; 966 967 m_cpt_read_fsm_heap_used = 0 ; 968 m_cpt_write_fsm_heap_used = 0 ; 969 m_cpt_cas_fsm_heap_used = 0 ; 970 m_cpt_cleanup_fsm_heap_used = 0 ; 971 m_cpt_xram_rsp_fsm_heap_used = 0 ; 972 m_cpt_multi_ack_fsm_heap_used = 0 ; 973 974 m_cpt_heap_unused = 0 ; 975 m_cpt_slot_inval = 0 ; 976 879 977 } 880 978 … … 894 992 << "[001] NUMBER OF CYCLES = " << m_cpt_cycles << std::endl 895 993 << std::endl 896 << "[002] LOCAL READ = " << m_cpt_read_ local << std::endl897 << "[003] REMOTE READ = " << m_cpt_read_ remote << std::endl898 << "[004] READ COST (FLITS * DIST) = " << m_cpt_read_ cost << std::endl994 << "[002] LOCAL READ = " << m_cpt_read_miss_local << std::endl 995 << "[003] REMOTE READ = " << m_cpt_read_miss_remote << std::endl 996 << "[004] READ COST (FLITS * DIST) = " << m_cpt_read_miss_cost << std::endl 899 997 << std::endl 900 << "[005] LOCAL WRITE = " << m_cpt_write_local << std::endl901 << "[006] REMOTE WRITE = " << m_cpt_write_remote << std::endl902 << "[007] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl903 << "[008] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl904 << "[009] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl998 << "[005] LOCAL GETM MISS = " << m_cpt_getm_miss_local << std::endl 999 << "[006] REMOTE GETM MISS = " << m_cpt_getm_miss_remote << std::endl 1000 << "[007] LOCAL GETM HIT = " << m_cpt_getm_hit_local << std::endl 1001 << "[008] REMOTE GETM HIT = " << m_cpt_getm_hit_remote << std::endl 1002 << "[009] GETM COST (FLITS * DIST) = " << m_cpt_getm_cost << std::endl 905 1003 << std::endl 906 << "[010] LOCAL LL = " << m_cpt_ll_local << std::endl 907 << "[011] REMOTE LL = " << m_cpt_ll_remote << std::endl 908 << "[012] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl 1004 << "[010] LOCAL WRITE = " << m_cpt_write_local << std::endl 1005 << "[011] REMOTE WRITE = " << m_cpt_write_remote << std::endl 1006 << "[012] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl 1007 << "[013] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl 1008 << "[014] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl 909 1009 << std::endl 910 << "[01 3] LOCAL SC = " << m_cpt_sc_local << std::endl911 << "[01 4] REMOTE SC = " << m_cpt_sc_remote << std::endl912 << "[01 5] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl1010 << "[015] LOCAL LL = " << m_cpt_ll_local << std::endl 1011 << "[016] REMOTE LL = " << m_cpt_ll_remote << std::endl 1012 << "[017] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl 913 1013 << std::endl 914 << "[01 6] LOCAL CAS = " << m_cpt_cas_local << std::endl915 << "[01 7] REMOTE CAS = " << m_cpt_cas_remote << std::endl916 << "[0 18] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl1014 << "[018] LOCAL SC = " << m_cpt_sc_local << std::endl 1015 << "[019] REMOTE SC = " << m_cpt_sc_remote << std::endl 1016 << "[020] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl 917 1017 << std::endl 918 << "[019] REQUESTS TRIG. UPDATE = " << m_cpt_update << std::endl 919 << "[020] LOCAL UPDATE = " << m_cpt_update_local << std::endl 920 << "[021] REMOTE UPDATE = " << m_cpt_update_remote << std::endl 921 << "[022] UPDT COST (FLITS * DIST) = " << m_cpt_update_cost << std::endl 1018 << "[021] LOCAL CAS = " << m_cpt_cas_local << std::endl 1019 << "[022] REMOTE CAS = " << m_cpt_cas_remote << std::endl 1020 << "[023] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl 922 1021 << std::endl 923 << "[02 3] REQUESTS TRIG. M_INV = " << m_cpt_minval<< std::endl924 << "[02 4] LOCAL M_INV = " << m_cpt_minval_local << std::endl925 << "[02 5] REMOTE M_INV = " << m_cpt_minval_remote << std::endl926 << "[02 6] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl1022 << "[024] REQUESTS TRIG. UPDATE = " << m_cpt_update << std::endl 1023 << "[025] LOCAL UPDATE = " << m_cpt_update_local << std::endl 1024 << "[026] REMOTE UPDATE = " << m_cpt_update_remote << std::endl 1025 << "[027] UPDT COST (FLITS * DIST) = " << m_cpt_update_cost << std::endl 927 1026 << std::endl 928 << "[027] BROADCAT INVAL = " << m_cpt_binval << std::endl 1027 << "[028] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl 1028 << "[029] LOCAL M_INV = " << m_cpt_minval_local << std::endl 1029 << "[030] REMOTE M_INV = " << m_cpt_minval_remote << std::endl 1030 << "[031] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl 929 1031 << std::endl 930 << "[028] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl 931 << "[029] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl 932 << "[030] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl 1032 << "[032] BROADCAT INVAL = " << m_cpt_binval << std::endl 933 1033 << std::endl 1034 << "[033] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl 1035 << "[034] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl 1036 << "[035] CLEANUP DATA = " << m_cpt_cleanup_with_data << std::endl 1037 << "[036] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl 934 1038 << std::endl 935 << "[031] READ MISS = " << m_cpt_read_miss << std::endl 936 << "[032] WRITE MISS = " << m_cpt_write_miss << std::endl 937 << "[033] WRITE DIRTY = " << m_cpt_write_dirty << std::endl 938 << "[034] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl 939 << "[035] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl 940 << "[036] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl 941 << "[037] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl 942 << "[038] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl 1039 << "[037] MULTI_ACK_MISS = " << m_cpt_multi_ack_miss << std::endl 1040 << "[038] MULTI_ACK_HIT = " << m_cpt_multi_ack_hit << std::endl 1041 << "[039] MULTI_ACK_DATA = " << m_cpt_multi_ack_hit_with_data << std::endl 943 1042 << std::endl 944 << "[039] CLEANUP DATA (FLITS) = " << m_cpt_cleanup_data * 16 << std::endl 945 << "[040] NCC TO CC (READ) = " << m_cpt_ncc_to_cc_read << std::endl 946 << "[041] NCC TO CC (WRITE) = " << m_cpt_ncc_to_cc_write << std::endl 947 << "[042] NCC TO CC (TOTAL) = " << m_cpt_ncc_to_cc << std::endl 1043 << "[040] READ MISS = " << m_cpt_read_miss << std::endl 1044 << "[041] GETM MISS = " << m_cpt_getm_miss << std::endl 1045 << "[042] WRITE MISS = " << m_cpt_write_miss << std::endl 1046 << "[043] CAS MISS = " << m_cpt_cas_miss << std::endl 1047 << "[044] WRITE DIRTY = " << m_cpt_write_dirty << std::endl 1048 << "[045] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl 1049 << "[046] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl 1050 << "[047] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl 1051 << "[048] WRITE MINVAL = " << m_cpt_write_minval << std::endl 1052 << "[049] CAS BROADCAST = " << m_cpt_cas_broadcast << std::endl 1053 << "[050] CAS MINVAL = " << m_cpt_cas_minval << std::endl 1054 << "[051] GETM BROADCAST = " << m_cpt_getm_broadcast << std::endl 1055 << "[052] GETM MINVAL = " << m_cpt_getm_minval << std::endl 1056 << std::endl 1057 << "[053] READ LOCKED WAIT = " << m_cpt_read_locked_rb << std::endl 1058 << "[054] CAS LOCKED WAIT = " << m_cpt_cas_locked_rb << std::endl 1059 << "[055] WRITE LOCKED WAIT = " << m_cpt_write_locked_rb << std::endl 1060 << "[056] EVICTED SLOT = " << m_cpt_slot_inval << std::endl 1061 948 1062 << std::endl; 949 1063 } … … 954 1068 std::cout << "----------------------------------" << std::dec << std::endl; 955 1069 std::cout 956 << "[100] READ TOTAL = " << m_cpt_read_local + m_cpt_read_remote << std::endl 957 << "[101] READ RATE = " << (double) (m_cpt_read_local + m_cpt_read_remote) / m_cpt_cycles << std::endl 958 << "[102] LOCAL READ RATE = " << (double) m_cpt_read_local / m_cpt_cycles << std::endl 959 << "[103] REMOTE READ RATE = " << (double) m_cpt_read_remote / m_cpt_cycles << std::endl 960 << "[104] READ MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_read_local + m_cpt_read_remote) << std::endl 1070 << "[100] READ TOTAL = " << m_cpt_read_miss_local + m_cpt_read_miss_remote << std::endl 1071 << "[101] READ RATE = " << (double) (m_cpt_read_miss_local + m_cpt_read_miss_remote) / m_cpt_cycles << std::endl 1072 << "[102] LOCAL READ RATE = " << (double) m_cpt_read_miss_local / m_cpt_cycles << std::endl 1073 << "[103] REMOTE READ RATE = " << (double) m_cpt_read_miss_remote / m_cpt_cycles << std::endl 1074 << "[104] READ MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_read_miss_local + m_cpt_read_miss_remote) << std::endl 1075 << "[100] GETM MISS TOTAL = " << m_cpt_getm_miss_local + m_cpt_getm_miss_remote << std::endl 1076 << "[101] GETM MISS RATE = " << (double) (m_cpt_getm_miss_local + m_cpt_getm_miss_remote) / m_cpt_cycles << std::endl 1077 << "[102] LOCAL GETM MISS RATE = " << (double) m_cpt_getm_miss_local / m_cpt_cycles << std::endl 1078 << "[103] REMOTE GETM MISS RATE = " << (double) m_cpt_getm_miss_remote / m_cpt_cycles << std::endl 1079 << "[100] GETM HIT TOTAL = " << m_cpt_getm_hit_local + m_cpt_getm_hit_remote << std::endl 1080 << "[101] GETM HIT RATE = " << (double) (m_cpt_getm_hit_local + m_cpt_getm_hit_remote) / m_cpt_cycles << std::endl 1081 << "[102] LOCAL GETM HIT RATE = " << (double) m_cpt_getm_hit_local / m_cpt_cycles << std::endl 1082 << "[103] REMOTE GETM HIT RATE = " << (double) m_cpt_getm_hit_remote / m_cpt_cycles << std::endl 1083 1084 << "[100] GETM TOTAL = " << m_cpt_getm_hit_local + m_cpt_getm_hit_remote + m_cpt_getm_miss_remote + m_cpt_getm_miss_local << std::endl 1085 1086 << "[104] GETM MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_getm_hit_local + m_cpt_getm_hit_remote + m_cpt_getm_miss_remote + m_cpt_getm_miss_local) << std::endl 1087 961 1088 << std::endl 962 1089 << "[105] WRITE TOTAL = " << m_cpt_write_local + m_cpt_write_remote << std::endl … … 995 1122 << "[134] LOCAL CAS RATE = " << (double) m_cpt_cas_local / m_cpt_cycles << std::endl 996 1123 << "[135] REMOTE CAS RATE = " << (double) m_cpt_cas_remote / m_cpt_cycles << std::endl 1124 << "[124] MULTI ACK RATE = " << (double) (m_cpt_multi_ack_hit + m_cpt_multi_ack_miss) / m_cpt_cycles << std::endl 997 1125 << std::endl 998 1126 << std::endl; … … 1187 1315 1188 1316 // Activity counters 1189 m_cpt_reset_count = 0; 1190 m_cpt_cycles = 0; 1191 m_cpt_read_local = 0; 1192 m_cpt_read_remote = 0; 1193 m_cpt_read_cost = 0; 1194 m_cpt_write_local = 0; 1195 m_cpt_write_remote = 0; 1196 m_cpt_write_flits_local = 0; 1197 m_cpt_write_flits_remote = 0; 1198 m_cpt_write_cost = 0; 1199 m_cpt_ll_local = 0; 1200 m_cpt_ll_remote = 0; 1201 m_cpt_ll_cost = 0; 1202 m_cpt_sc_local = 0; 1203 m_cpt_sc_remote = 0; 1204 m_cpt_sc_cost = 0; 1205 m_cpt_cas_local = 0; 1206 m_cpt_cas_remote = 0; 1207 m_cpt_cas_cost = 0; 1208 m_cpt_update = 0; 1209 m_cpt_update_local = 0; 1210 m_cpt_update_remote = 0; 1211 m_cpt_update_cost = 0; 1212 m_cpt_minval = 0; 1213 m_cpt_minval_local = 0; 1214 m_cpt_minval_remote = 0; 1215 m_cpt_minval_cost = 0; 1216 m_cpt_binval = 0; 1217 m_cpt_cleanup_local = 0; 1218 m_cpt_cleanup_remote = 0; 1219 m_cpt_cleanup_cost = 0; 1220 1221 m_cpt_read_miss = 0; 1222 m_cpt_write_miss = 0; 1223 m_cpt_write_dirty = 0; 1224 m_cpt_write_broadcast = 0; 1225 m_cpt_trt_rb = 0; 1226 m_cpt_trt_full = 0; 1227 m_cpt_get = 0; 1228 m_cpt_put = 0; 1229 m_cpt_dir_unused = 0; 1230 m_cpt_upt_unused = 0; 1231 m_cpt_ivt_unused = 0; 1232 m_cpt_heap_unused = 0; 1233 m_cpt_trt_unused = 0; 1234 m_cpt_read_fsm_n_dir_lock = 0; 1235 m_cpt_read_fsm_dir_lock = 0; 1236 m_cpt_read_fsm_dir_used = 0; 1237 m_cpt_read_fsm_trt_lock = 0; 1238 m_cpt_read_fsm_heap_lock = 0; 1239 m_cpt_write_fsm_dir_lock = 0; 1240 m_cpt_write_fsm_n_dir_lock = 0; 1241 m_cpt_write_fsm_upt_lock = 0; 1242 m_cpt_write_fsm_heap_lock = 0; 1243 m_cpt_write_fsm_dir_used = 0; 1244 m_cpt_write_fsm_trt_lock = 0; 1245 m_cpt_cas_fsm_n_dir_lock = 0; 1246 m_cpt_cas_fsm_dir_lock = 0; 1247 m_cpt_cas_fsm_upt_lock = 0; 1248 m_cpt_cas_fsm_heap_lock = 0; 1249 m_cpt_cas_fsm_trt_lock = 0; 1250 m_cpt_cas_fsm_dir_used = 0; 1251 m_cpt_xram_rsp_fsm_n_dir_lock = 0; 1252 m_cpt_xram_rsp_fsm_dir_lock = 0; 1253 m_cpt_xram_rsp_fsm_trt_lock = 0; 1254 m_cpt_xram_rsp_fsm_upt_lock = 0; 1255 m_cpt_xram_rsp_fsm_heap_lock = 0; 1256 m_cpt_xram_rsp_fsm_dir_used = 0; 1257 m_cpt_cleanup_fsm_dir_lock = 0; 1258 m_cpt_cleanup_fsm_n_dir_lock = 0; 1259 m_cpt_cleanup_fsm_heap_lock = 0; 1260 m_cpt_cleanup_fsm_ivt_lock = 0; 1261 m_cpt_cleanup_fsm_dir_used = 0; 1262 m_cpt_ixr_fsm_trt_lock = 0; 1263 m_cpt_multi_ack_fsm_upt_lock = 0; 1264 m_cpt_read_data_unc = 0; 1265 m_cpt_read_data_miss_CC = 0; 1266 m_cpt_read_ins_unc = 0; 1267 m_cpt_read_ins_miss = 0; 1268 m_cpt_read_ll_CC = 0; 1269 m_cpt_read_data_miss_NCC = 0; 1270 m_cpt_read_ll_NCC = 0; 1271 m_cpt_read_WTF = 0; 1272 m_cpt_cleanup_data = 0; 1273 m_cpt_ncc_to_cc_read = 0; 1274 m_cpt_ncc_to_cc_write = 0; 1275 m_cpt_ncc_to_cc = 0; 1317 m_cpt_reset_count = 0 ; 1318 m_cpt_read_miss_local = 0 ; 1319 m_cpt_read_miss_remote = 0 ; 1320 m_cpt_read_miss_cost = 0 ; 1321 1322 m_cpt_getm_miss_local = 0 ; 1323 m_cpt_getm_miss_remote = 0 ; 1324 1325 m_cpt_getm_hit_local = 0 ; 1326 m_cpt_getm_hit_remote = 0 ; 1327 m_cpt_getm_cost = 0 ; 1328 1329 m_cpt_write_local = 0 ; 1330 m_cpt_write_remote = 0 ; 1331 m_cpt_write_flits_local = 0 ; 1332 m_cpt_write_flits_remote = 0 ; 1333 m_cpt_write_cost = 0 ; 1334 1335 m_cpt_ll_local = 0 ; 1336 m_cpt_ll_remote = 0 ; 1337 m_cpt_ll_cost = 0 ; 1338 1339 m_cpt_sc_local = 0 ; 1340 m_cpt_sc_remote = 0 ; 1341 m_cpt_sc_cost = 0 ; 1342 1343 m_cpt_cas_local = 0 ; 1344 m_cpt_cas_remote = 0 ; 1345 m_cpt_cas_cost = 0 ; 1346 1347 m_cpt_update = 0 ; 1348 m_cpt_update_local = 0 ; 1349 m_cpt_update_remote = 0 ; 1350 m_cpt_update_cost = 0 ; 1351 1352 m_cpt_minval = 0 ; 1353 m_cpt_minval_local = 0 ; 1354 m_cpt_minval_remote = 0 ; 1355 m_cpt_minval_cost = 0 ; 1356 1357 m_cpt_binval = 0 ; 1358 1359 m_cpt_cleanup_local = 0 ; 1360 m_cpt_cleanup_remote = 0 ; 1361 m_cpt_cleanup_with_data = 0 ; 1362 m_cpt_cleanup_cost = 0 ; 1363 1364 m_cpt_multi_ack_miss = 0 ; 1365 m_cpt_multi_ack_hit = 0 ; 1366 m_cpt_multi_ack_hit_with_data = 0 ; 1367 1368 1369 m_cpt_read_miss = 0 ; 1370 m_cpt_getm_miss = 0 ; 1371 m_cpt_getm_broadcast = 0 ; 1372 m_cpt_getm_minval = 0 ; 1373 m_cpt_write_miss = 0 ; 1374 m_cpt_write_dirty = 0 ; 1375 m_cpt_write_broadcast = 0 ; 1376 m_cpt_write_minval = 0 ; 1377 m_cpt_cas_broadcast = 0 ; 1378 m_cpt_cas_minval = 0 ; 1379 m_cpt_cas_miss = 0 ; 1380 1381 m_cpt_read_locked_rb = 0 ; 1382 m_cpt_cas_locked_rb = 0 ; 1383 m_cpt_write_locked_rb = 0 ; 1384 1385 m_cpt_trt_rb = 0 ; 1386 m_cpt_trt_full = 0 ; 1387 1388 m_cpt_read_fsm_dir_lock = 0 ; 1389 m_cpt_read_fsm_n_dir_lock = 0 ; 1390 m_cpt_write_fsm_dir_lock = 0 ; 1391 m_cpt_write_fsm_n_dir_lock = 0 ; 1392 m_cpt_xram_rsp_fsm_dir_lock = 0 ; 1393 m_cpt_xram_rsp_fsm_n_dir_lock = 0 ; 1394 m_cpt_cas_fsm_dir_lock = 0 ; 1395 m_cpt_cas_fsm_n_dir_lock = 0 ; 1396 m_cpt_cleanup_fsm_dir_lock = 0 ; 1397 m_cpt_cleanup_fsm_n_dir_lock = 0 ; 1398 m_cpt_multi_ack_fsm_dir_lock = 0 ; 1399 m_cpt_multi_ack_fsm_n_dir_lock = 0 ; 1400 1401 m_cpt_dir_unused = 0 ; 1402 m_cpt_read_fsm_dir_used = 0 ; 1403 m_cpt_write_fsm_dir_used = 0 ; 1404 m_cpt_cas_fsm_dir_used = 0 ; 1405 m_cpt_xram_rsp_fsm_dir_used = 0 ; 1406 m_cpt_cleanup_fsm_dir_used = 0 ; 1407 m_cpt_multi_ack_fsm_dir_used = 0 ; 1408 1409 m_cpt_read_fsm_trt_lock = 0 ; 1410 m_cpt_write_fsm_trt_lock = 0 ; 1411 m_cpt_cas_fsm_trt_lock = 0 ; 1412 m_cpt_xram_rsp_fsm_trt_lock = 0 ; 1413 m_cpt_ixr_fsm_trt_lock = 0 ; 1414 1415 m_cpt_read_fsm_n_trt_lock = 0 ; 1416 m_cpt_write_fsm_n_trt_lock = 0 ; 1417 m_cpt_cas_fsm_n_trt_lock = 0 ; 1418 m_cpt_xram_rsp_fsm_n_trt_lock = 0 ; 1419 m_cpt_ixr_cmd_fsm_n_trt_lock = 0 ; 1420 m_cpt_ixr_rsp_fsm_n_trt_lock = 0 ; 1421 1422 m_cpt_read_fsm_trt_used = 0 ; 1423 m_cpt_write_fsm_trt_used = 0 ; 1424 m_cpt_cas_fsm_trt_used = 0 ; 1425 m_cpt_xram_rsp_fsm_trt_used = 0 ; 1426 m_cpt_ixr_cmd_fsm_trt_used = 0 ; 1427 m_cpt_ixr_rsp_fsm_trt_used = 0 ; 1428 m_cpt_cleanup_fsm_trt_used = 0 ; 1429 1430 m_cpt_trt_unused = 0 ; 1431 1432 m_cpt_cleanup_fsm_ivt_lock = 0 ; 1433 m_cpt_cleanup_fsm_n_ivt_lock = 0 ; 1434 1435 m_cpt_multi_ack_fsm_ivt_lock = 0 ; 1436 m_cpt_multi_ack_fsm_n_ivt_lock = 0 ; 1437 1438 m_cpt_ivt_unused = 0 ; 1439 1440 m_cpt_read_fsm_heap_lock = 0 ; 1441 m_cpt_write_fsm_heap_lock = 0 ; 1442 m_cpt_cas_fsm_heap_lock = 0 ; 1443 m_cpt_cleanup_fsm_heap_lock = 0 ; 1444 m_cpt_xram_rsp_fsm_heap_lock = 0 ; 1445 m_cpt_multi_ack_fsm_heap_lock = 0 ; 1446 1447 m_cpt_read_fsm_n_heap_lock = 0 ; 1448 m_cpt_write_fsm_n_heap_lock = 0 ; 1449 m_cpt_cas_fsm_n_heap_lock = 0 ; 1450 m_cpt_cleanup_fsm_n_heap_lock = 0 ; 1451 m_cpt_xram_rsp_fsm_n_heap_lock = 0 ; 1452 m_cpt_multi_ack_fsm_n_heap_lock = 0 ; 1453 1454 m_cpt_read_fsm_heap_used = 0 ; 1455 m_cpt_write_fsm_heap_used = 0 ; 1456 m_cpt_cas_fsm_heap_used = 0 ; 1457 m_cpt_cleanup_fsm_heap_used = 0 ; 1458 m_cpt_xram_rsp_fsm_heap_used = 0 ; 1459 m_cpt_multi_ack_fsm_heap_used = 0 ; 1460 1461 m_cpt_heap_unused = 0 ; 1462 m_cpt_slot_inval = 0 ; 1276 1463 return; 1277 1464 } … … 1830 2017 } 1831 2018 else { 1832 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_local++; 1833 else m_cpt_read_remote++; 1834 m_cpt_read_cost += m_words * req_distance(p_vci_tgt.srcid.read()); 2019 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_WRITE) 2020 { 2021 if ((p_vci_tgt.pktid.read() & 0x8) == 0x8) 2022 { 2023 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_getm_hit_local++; 2024 else m_cpt_getm_hit_remote++; 2025 } 2026 else 2027 { 2028 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_getm_miss_local++; 2029 else m_cpt_getm_miss_remote++; 2030 } 2031 m_cpt_getm_cost += req_distance(p_vci_tgt.srcid.read()); 2032 } 2033 else 2034 { 2035 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_miss_local++; 2036 else m_cpt_read_miss_remote++; 2037 m_cpt_read_miss_cost += req_distance(p_vci_tgt.srcid.read()); 2038 } 1835 2039 } 1836 2040 // </Activity counters> … … 1963 2167 r_multi_ack_miss_updt = miss_updt; 1964 2168 2169 if(miss_updt) 2170 m_cpt_multi_ack_miss ++; 2171 else 2172 m_cpt_multi_ack_hit ++; 2173 1965 2174 if( not eop) 1966 2175 { … … 1968 2177 r_multi_ack_need_data = true; 1969 2178 r_multi_ack_data_index = 0; 2179 m_cpt_multi_ack_hit_with_data ++; 1970 2180 } 1971 2181 else … … 2028 2238 case MULTI_ACK_IVT_LOCK: 2029 2239 { 2240 m_cpt_multi_ack_fsm_ivt_lock ++; 2030 2241 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break; 2242 2243 m_cpt_multi_ack_fsm_n_ivt_lock ++; 2244 2031 2245 assert( r_alloc_dir_fsm.read() == ALLOC_DIR_MULTI_ACK && " BAD ALLOC_DIR_MULTI_ACK IN MULTI_ACK_IVT_LOCK STATE"); 2032 2246 size_t index = r_multi_ack_ivt_index.read(); … … 2090 2304 case MULTI_ACK_DIR_REQ: // Get the lock to the directory 2091 2305 { 2306 m_cpt_multi_ack_fsm_dir_lock ++; 2092 2307 if(r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) break; 2093 2308 2094 2309 r_multi_ack_fsm = MULTI_ACK_IVT_LOCK; 2095 2310 //std::cout << " MEM_CACHE : CLEANUP_DIR_REQ" << std::endl; 2311 m_cpt_multi_ack_fsm_n_dir_lock ++; 2096 2312 2097 2313 #if DEBUG_MEMC_CLEANUP … … 2333 2549 case MULTI_ACK_HEAP_REQ: // Get the lock to the HEAP directory 2334 2550 { 2551 m_cpt_multi_ack_fsm_n_heap_lock ++; 2335 2552 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK) 2336 2553 { 2337 2554 r_multi_ack_fsm = MULTI_ACK_HEAP_LOCK; 2338 2555 } 2556 2557 m_cpt_multi_ack_fsm_heap_lock ++; 2339 2558 #if DEBUG_MEMC_MULTI_ACK 2340 2559 if(m_debug) … … 3173 3392 else if(entry.state == ENTRY_LOCKED) // the line is locked, can't use it at this time 3174 3393 { 3394 m_cpt_read_locked_rb ++; 3175 3395 r_read_fsm = READ_WAIT; 3176 3396 } … … 3287 3507 cmd_read_fifo_get = true; 3288 3508 } 3509 3510 if(multi_req) 3511 m_cpt_getm_minval ++; 3512 else 3513 m_cpt_getm_broadcast ++; 3289 3514 #if DEBUG_MEMC_READ 3290 3515 if(m_debug) … … 3850 4075 else // missing line is requested to the XRAM 3851 4076 { 3852 m_cpt_read_miss++; 4077 4078 if ( (m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_WRITE ) 4079 m_cpt_getm_miss ++; 4080 else 4081 m_cpt_read_miss++; 4082 3853 4083 r_read_trt_index = index; 3854 4084 r_read_fsm = READ_TRT_SET; … … 4059 4289 // Get the lock to the directory 4060 4290 // and access the llsc_global_table 4061 if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) break; 4291 if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) 4292 { 4293 m_cpt_write_fsm_n_dir_lock ++; 4294 break; 4295 } 4062 4296 4063 4297 if ((r_write_pktid.read() & 0x7) == TYPE_SC) … … 4087 4321 r_write_fsm = WRITE_DIR_LOCK; 4088 4322 } 4323 4324 m_cpt_write_fsm_dir_lock ++; 4089 4325 4090 4326 #if DEBUG_MEMC_WRITE … … 4129 4365 else if (entry.state == ENTRY_LOCKED)//the line is locked 4130 4366 { 4367 m_cpt_write_locked_rb ++; 4131 4368 r_write_fsm = WRITE_WAIT; 4132 4369 } … … 4439 4676 } 4440 4677 4678 m_cpt_write_fsm_n_trt_lock ++; 4441 4679 assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); 4442 4680 } … … 4582 4820 false, // is a command write 4583 4821 index); 4584 /*// std::cout << " trt wait nline =" << std::hex << nline 4585 << " write data " << std::hex << std::endl;*/ 4822 4823 if(is_brdcast) 4824 m_cpt_write_broadcast ++; 4825 else 4826 m_cpt_write_minval ++; 4586 4827 #if DEBUG_MEMC_WRITE 4587 4828 if( m_debug and wok ) … … 4627 4868 } 4628 4869 4629 m_cpt_write_fsm_upt_lock++;4630 4870 4631 4871 break; … … 4844 5084 for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i]; 4845 5085 5086 m_cpt_ixr_cmd_fsm_n_trt_lock ++; 4846 5087 #if DEBUG_MEMC_IXR_CMD 4847 5088 if(m_debug) … … 5142 5383 } 5143 5384 5385 m_cpt_ixr_rsp_fsm_n_trt_lock ++; 5144 5386 #if DEBUG_MEMC_IXR_RSP 5145 5387 if(m_debug) … … 5183 5425 << " / data = " << std::hex << data << std::endl; 5184 5426 #endif 5185 m_cpt_ixr_ fsm_n_trt_lock++;5427 m_cpt_ixr_rsp_fsm_n_trt_lock ++; 5186 5428 } 5187 5429 m_cpt_ixr_fsm_trt_lock++; … … 5481 5723 5482 5724 r_xram_rsp_ivt_index = index; 5725 5726 m_cpt_slot_inval ++; 5727 5483 5728 assert( wok and 5484 5729 "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); … … 5915 6160 r_cleanup_data_index = 0; 5916 6161 r_cleanup_contains_data = true; 6162 m_cpt_cleanup_with_data ++; 5917 6163 } 5918 6164 else … … 5976 6222 if (r_cleanup_data_index.read() == m_words - 1) 5977 6223 { 5978 m_cpt_cleanup_data ++;5979 6224 r_cleanup_fsm = CLEANUP_DIR_REQ; 5980 6225 } … … 6187 6432 { 6188 6433 //Search for a matching inval in the ivt (there must be one) and check if there is a pending read or cas. 6434 6435 m_cpt_cleanup_fsm_ivt_lock++; 6189 6436 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) 6190 6437 { … … 6454 6701 { 6455 6702 // get the lock to the HEAP directory 6703 m_cpt_cleanup_fsm_heap_lock ++; 6456 6704 if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; 6457 6705 … … 6711 6959 bool match_inval; 6712 6960 6961 m_cpt_cleanup_fsm_n_ivt_lock++; 6962 6713 6963 match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); 6714 6964 if ( not match_inval ) // no pending inval … … 6725 6975 << std::endl; 6726 6976 #endif 6727 m_cpt_cleanup_fsm_n_ upt_lock++;6977 m_cpt_cleanup_fsm_n_ivt_lock++; 6728 6978 } 6729 6979 else … … 7058 7308 r_cas_count = entry.count; 7059 7309 7060 if(entry.state == ENTRY_LOCKED) r_cas_fsm = CAS_WAIT; 7061 else if(entry.state == ENTRY_INVALID) r_cas_fsm = CAS_MISS_TRT_LOCK; 7062 else r_cas_fsm = CAS_DIR_HIT_READ; 7063 7310 if(entry.state == ENTRY_LOCKED) 7311 { 7312 r_cas_fsm = CAS_WAIT; 7313 m_cpt_cas_locked_rb ++; 7314 } 7315 else if(entry.state == ENTRY_INVALID) 7316 { 7317 r_cas_fsm = CAS_MISS_TRT_LOCK; 7318 } 7319 else 7320 { 7321 r_cas_fsm = CAS_DIR_HIT_READ; 7322 } 7064 7323 #if DEBUG_MEMC_CAS 7065 7324 if(m_debug) … … 7184 7443 else 7185 7444 { 7186 r_cas_fsm = CAS_ MULTI_INVAL_IVT_LOCK; // multi invalidate required7445 r_cas_fsm = CAS_INVAL_IVT_LOCK; // multi invalidate required 7187 7446 #if DEBUG_MEMC_CAS 7188 7447 if(m_debug) … … 7220 7479 } 7221 7480 ///////////////// 7222 case CAS_ MULTI_INVAL_IVT_LOCK: // try to register the transaction in ivt7481 case CAS_INVAL_IVT_LOCK: // try to register the transaction in ivt 7223 7482 // and write data in cache if successful registration 7224 7483 // releases locks to retry later if ivt full … … 7236 7495 addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 7237 7496 7238 wok = m_ivt.set(false, // it's an invalid transaction7239 false, // it's not a broadcast7240 true, // response required7241 false, // no acknowledge required7497 wok = m_ivt.set(false, // it's an invalid transaction 7498 r_cas_is_cnt.read(), 7499 true, // response required 7500 false, // no acknowledge required 7242 7501 srcid, 7243 7502 trdid, … … 7274 7533 m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); 7275 7534 7535 if(r_cas_is_cnt.read()) 7536 m_cpt_cas_broadcast ++; 7537 else 7538 m_cpt_cas_minval ++; 7539 7276 7540 //r_cas_ivt_index = index; 7277 7541 if((r_cas_count.read() != 1) and not r_cas_is_cnt.read()) … … 7296 7560 7297 7561 r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; 7298 //r_cas_to_cleanup_req = true;7299 //r_cas_to_cleanup_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];7300 7562 r_cas_fsm = CAS_IDLE; 7301 7563 cmd_cas_fifo_get = true; … … 7306 7568 if(m_debug) 7307 7569 std::cout << " <MEMC " << name() 7308 << " CAS_ MULTI_INVAL_IVT_LOCK> Line is locked"7570 << " CAS_INVAL_IVT_LOCK> Line is locked" 7309 7571 << " / wok = " << wok 7310 7572 << " / set = " << set … … 7472 7734 break; 7473 7735 } 7474 7475 7476 7736 ///////////////////// 7477 case CAS_BC_TRT_LOCK: // check the TRT to register a PUT transaction7478 {7479 assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and7480 "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation");7481 7482 if(r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)7483 {7484 size_t wok_index = 0;7485 bool wok = !m_trt.full(wok_index);7486 if( wok )7487 {7488 r_cas_trt_index = wok_index;7489 r_cas_fsm = CAS_BC_IVT_LOCK;7490 }7491 else7492 {7493 r_cas_fsm = CAS_WAIT;7494 m_cpt_cas_fsm_n_trt_lock++;7495 }7496 7497 #if DEBUG_MEMC_CAS7498 if(m_debug)7499 std::cout << " <MEMC " << name() << " CAS_BC_TRT_LOCK> Check TRT"7500 << " : wok = " << wok << " / index = " << wok_index << std::endl;7501 #endif7502 }7503 m_cpt_cas_fsm_trt_lock++;7504 7505 break;7506 }7507 /////////////////////7508 case CAS_BC_IVT_LOCK: // register a broadcast inval transaction in IVT7509 // write data in cache in case of successful registration7510 {7511 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS)7512 {7513 bool wok = false;7514 size_t index = 0;7515 size_t srcid = m_cmd_cas_srcid_fifo.read();7516 size_t trdid = m_cmd_cas_trdid_fifo.read();7517 size_t pktid = m_cmd_cas_pktid_fifo.read();7518 addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];7519 size_t nb_copies = r_cas_count.read();7520 7521 // register a broadcast inval transaction in IVT7522 wok = m_ivt.set(false, // it's an inval transaction7523 true, // it's a broadcast7524 true, // response required7525 false, // no acknowledge required7526 srcid,7527 trdid,7528 pktid,7529 nline,7530 nb_copies,7531 false, // is a command write7532 index);7533 7534 if(wok) // IVT not full7535 {7536 // cache update7537 size_t way = r_cas_way.read();7538 size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];7539 size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];7540 7541 m_cache_data.write(way, set, word, r_cas_wdata.read());7542 if(r_cas_cpt.read() ==4)7543 m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());7544 7545 r_cas_ivt_index = index;7546 r_cas_fsm = CAS_BC_DIR_INVAL;7547 7548 #if DEBUG_MEMC_CAS7549 if(m_debug)7550 std::cout << " <MEMC " << name()7551 << " CAS_BC_IVT_LOCK> Register a broadcast inval transaction in IVT"7552 << " / nline = " << std::hex << nline7553 << " / count = " << std::dec << nb_copies7554 << " / ivt_index = " << index << std::endl;7555 #endif7556 }7557 else // releases the lock protecting IVT7558 {7559 r_cas_fsm = CAS_WAIT;7560 }7561 m_cpt_cas_fsm_n_upt_lock++;7562 }7563 7564 m_cpt_cas_fsm_upt_lock++;7565 7566 break;7567 }7568 //////////////////////7569 case CAS_BC_DIR_INVAL: // Register the PUT transaction in TRT, and inval the DIR entry7570 {7571 assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and7572 "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation");7573 7574 assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and7575 "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation");7576 7577 assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and7578 "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation");7579 7580 std::vector<data_t> data_vector;7581 data_vector.clear();7582 size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())];7583 7584 for(size_t i=0; i<m_words; i++)7585 {7586 if(i == word) // first modified word7587 data_vector.push_back( r_cas_wdata.read() );7588 else if((i == word+1) and (r_cas_cpt.read() == 4)) // second modified word7589 data_vector.push_back( m_cmd_cas_wdata_fifo.read() );7590 else // unmodified words7591 data_vector.push_back( r_cas_data[i].read() );7592 }7593 m_trt.set( r_cas_trt_index.read(),7594 false, // PUT request7595 m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],7596 0,7597 0,7598 0,7599 false, // not a processor read7600 0,7601 0,7602 std::vector<be_t> (m_words,0),7603 data_vector );7604 7605 // invalidate directory entry7606 DirectoryEntry entry;7607 entry.state = ENTRY_INVALID;7608 entry.dirty = false;7609 entry.tag = 0;7610 entry.is_cnt = false;7611 entry.lock = false;7612 entry.count = 0;7613 entry.owner.srcid = 0;7614 entry.owner.inst = false;7615 entry.ptr = 0;7616 size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())];7617 size_t way = r_cas_way.read();7618 m_cache_directory.write(set, way, entry);7619 7620 r_cas_fsm = CAS_BC_CC_SEND;7621 7622 #if DEBUG_MEMC_CAS7623 if(m_debug)7624 std::cout << " <MEMC " << name() << " CAS_BC_DIR_INVAL> Inval DIR & register in TRT:"7625 << " address = " << m_cmd_cas_addr_fifo.read() << std::endl;7626 #endif7627 break;7628 }7629 ///////////////////7630 case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM7631 {7632 if( not r_cas_to_cc_send_multi_req.read() and7633 not r_cas_to_cc_send_brdcast_req.read())7634 {7635 r_cas_to_cc_send_multi_req = false;7636 r_cas_to_cc_send_brdcast_req = true;7637 r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())];7638 7639 r_cas_fsm = CAS_BC_XRAM_REQ;7640 }7641 break;7642 }7643 ////////////////////7644 case CAS_BC_XRAM_REQ: // request the IXR FSM to start a put transaction7645 {7646 if( not r_cas_to_ixr_cmd_req.read() )7647 {7648 r_cas_to_ixr_cmd_req = true;7649 r_cas_to_ixr_cmd_index = r_cas_trt_index.read();7650 r_cas_fsm = CAS_IDLE;7651 cmd_cas_fifo_get = true;7652 r_cas_cpt = 0;7653 7654 #if DEBUG_MEMC_CAS7655 if(m_debug)7656 std::cout << " <MEMC " << name()7657 << " CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex7658 << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read()7659 << " / trt_index = " << r_cas_trt_index.read() << std::endl;7660 #endif7661 }7662 7663 break;7664 }7665 /////////////////7666 7737 case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response 7667 7738 { … … 7738 7809 r_cas_trt_index = index; 7739 7810 r_cas_fsm = CAS_MISS_TRT_SET; 7811 m_cpt_cas_miss ++; 7740 7812 } 7741 7813 m_cpt_cas_fsm_n_trt_lock++; … … 8312 8384 { 8313 8385 if(not p_dspin_m2p.read) break; 8386 // <Activity Counters> 8387 m_cpt_binval++; 8388 // </Activity Counters> 8314 8389 r_cc_send_fsm = CC_SEND_READ_BRDCAST_NLINE; 8315 8390 break; … … 8327 8402 { 8328 8403 if(not p_dspin_m2p.read) break; 8404 // <Activity Counters> 8405 if (is_local_req(m_read_to_cc_send_srcid_fifo.read())) 8406 { 8407 if(r_read_to_cc_send_type.read()) 8408 m_cpt_minval_local ++; 8409 else 8410 m_cpt_update_local ++; 8411 } 8412 else 8413 { 8414 if(r_read_to_cc_send_type.read()) 8415 { 8416 m_cpt_minval_remote++; 8417 m_cpt_minval_cost += req_distance(m_read_to_cc_send_srcid_fifo.read()); 8418 } 8419 else 8420 { 8421 m_cpt_update_remote++; 8422 m_cpt_update_cost += req_distance(m_read_to_cc_send_srcid_fifo.read()); 8423 } 8424 } 8425 // </Activity Counters> 8329 8426 r_cc_send_fsm = CC_SEND_READ_MULTI_NLINE; 8330 8427 break; … … 8335 8432 r_read_to_cc_send_multi_req = false; 8336 8433 } 8337 8434 // <Activity Counters> 8435 if(r_read_to_cc_send_type.read()) 8436 m_cpt_minval++; 8437 // </Activity Counters> 8338 8438 r_cc_send_fsm = CC_SEND_READ_IDLE; 8339 8439 break; … … 8392 8492 { 8393 8493 if(not p_dspin_m2p.read) break; 8494 // <Activity Counters> 8495 if (is_local_req(m_write_to_cc_send_srcid_fifo.read())) 8496 { 8497 m_cpt_minval_local++; 8498 } 8499 else 8500 { 8501 m_cpt_minval_remote++; 8502 m_cpt_minval_cost += req_distance(m_write_to_cc_send_srcid_fifo.read()); 8503 } 8504 // </Activity Counters> 8394 8505 r_cc_send_fsm = CC_SEND_WRITE_INVAL_NLINE; 8395 8506 break; … … 8400 8511 r_write_to_cc_send_multi_req = false; 8401 8512 } 8402 8403 8513 // <Activity Counters> 8404 m_cpt_ update++;8514 m_cpt_minval++; 8405 8515 // </Activity Counters> 8406 8516 r_cc_send_fsm = CC_SEND_WRITE_IDLE; … … 8437 8547 // </Activity Counters> 8438 8548 8439 r_cas_to_cc_send_brdcast_req = false; 8549 // <Activity Counters> 8550 m_cpt_minval++; 8551 // </Activity Counters> r_cas_to_cc_send_brdcast_req = false; 8440 8552 r_cc_send_fsm = CC_SEND_CAS_IDLE; 8441 8553 … … 8454 8566 { 8455 8567 if(not p_dspin_m2p.read) break; 8568 // <Activity Counters> 8569 if (is_local_req(m_cas_to_cc_send_srcid_fifo.read())) 8570 { 8571 m_cpt_minval_local++; 8572 } 8573 else 8574 { 8575 m_cpt_minval_remote++; 8576 m_cpt_minval_cost += req_distance(m_cas_to_cc_send_srcid_fifo.read()); 8577 } 8578 // </Activity Counters> 8456 8579 r_cc_send_fsm = CC_SEND_CAS_INVAL_NLINE; 8457 8580 break; … … 8463 8586 r_cas_to_cc_send_multi_req = false; 8464 8587 } 8465 8588 // <Activity Counters> 8589 m_cpt_minval++; 8590 // </Activity Counters> 8466 8591 r_cc_send_fsm = CC_SEND_CAS_IDLE; 8467 8592 break; … … 8902 9027 r_read_to_tgt_rsp_req = false; 8903 9028 r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; 8904 if (r_read_to_tgt_rsp_pktid.read() == 0x0)8905 {8906 m_cpt_read_data_unc ++;8907 }8908 else if (r_read_to_tgt_rsp_pktid.read() == 0x1)8909 {8910 m_cpt_read_data_miss_CC ++;8911 }8912 else if (r_read_to_tgt_rsp_pktid.read() == 0x2)8913 {8914 m_cpt_read_ins_unc ++;8915 }8916 else if (r_read_to_tgt_rsp_pktid.read() == 0x3)8917 {8918 m_cpt_read_ins_miss ++;8919 }8920 else if (r_read_to_tgt_rsp_pktid.read() == 0x6)8921 {8922 m_cpt_read_ll_CC ++;8923 }8924 else if (r_read_to_tgt_rsp_pktid.read() == 0x9)8925 {8926 m_cpt_read_data_miss_NCC ++;8927 }8928 else if (r_read_to_tgt_rsp_pktid.read() == 0x14)8929 {8930 m_cpt_read_ll_NCC ++;8931 }8932 else8933 {8934 m_cpt_read_WTF ++;8935 }8936 9029 } 8937 9030 else … … 8994 9087 r_cleanup_to_tgt_rsp_req = false; 8995 9088 r_tgt_rsp_key_sent = false; 8996 8997 if (r_cleanup_to_tgt_rsp_pktid.read() == 0x0)8998 {8999 m_cpt_read_data_unc ++;9000 }9001 else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x1)9002 {9003 m_cpt_read_data_miss_CC ++;9004 }9005 else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x2)9006 {9007 m_cpt_read_ins_unc ++;9008 }9009 else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x3)9010 {9011 m_cpt_read_ins_miss ++;9012 }9013 else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x6)9014 {9015 m_cpt_read_ll_CC ++;9016 }9017 else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x9)9018 {9019 m_cpt_read_data_miss_NCC ++;9020 }9021 else if (r_cleanup_to_tgt_rsp_pktid.read() == 0x14)9022 {9023 m_cpt_read_ll_NCC ++;9024 }9025 else if (!r_cleanup_to_tgt_rsp_type.read())9026 {9027 m_cpt_read_WTF ++;9028 }9029 9030 9089 } 9031 9090 else … … 9090 9149 r_xram_rsp_to_tgt_rsp_req = false; 9091 9150 r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; 9092 9093 9094 if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x0)9095 {9096 m_cpt_read_data_unc ++;9097 }9098 else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x1)9099 {9100 m_cpt_read_data_miss_CC ++;9101 }9102 else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x2)9103 {9104 m_cpt_read_ins_unc ++;9105 }9106 else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x3)9107 {9108 m_cpt_read_ins_miss ++;9109 }9110 else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x6)9111 {9112 m_cpt_read_ll_CC ++;9113 }9114 else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x9)9115 {9116 m_cpt_read_data_miss_NCC ++;9117 }9118 else if (r_xram_rsp_to_tgt_rsp_pktid.read() == 0x14)9119 {9120 m_cpt_read_ll_NCC ++;9121 }9122 else9123 {9124 m_cpt_read_WTF ++;9125 }9126 9127 9151 } 9128 9152 else … … 9217 9241 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 9218 9242 9219 else if ((r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) or 9220 (r_cas_fsm.read() == CAS_BC_IVT_LOCK)) 9243 else if (r_cas_fsm.read() == CAS_INVAL_IVT_LOCK) 9221 9244 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 9222 9245 … … 9244 9267 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 9245 9268 9246 else if ((r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) or 9247 (r_cas_fsm.read() == CAS_BC_IVT_LOCK)) 9269 else if (r_cas_fsm.read() == CAS_INVAL_IVT_LOCK) 9248 9270 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 9249 9271 … … 9270 9292 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 9271 9293 9272 else if ((r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) or 9273 (r_cas_fsm.read() == CAS_BC_IVT_LOCK)) 9294 else if (r_cas_fsm.read() == CAS_INVAL_IVT_LOCK) 9274 9295 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 9275 9296 … … 9299 9320 (r_cleanup_fsm.read() != CLEANUP_LOCKED_IVT_DECREMENT)) 9300 9321 { 9301 if ((r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) or 9302 (r_cas_fsm.read() == CAS_BC_IVT_LOCK)) 9322 if (r_cas_fsm.read() == CAS_INVAL_IVT_LOCK) 9303 9323 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 9304 9324 … … 9326 9346 ////////////////////////// 9327 9347 case ALLOC_IVT_CAS: // allocated to CAS FSM 9328 if ((r_cas_fsm.read() != CAS_MULTI_INVAL_IVT_LOCK) and 9329 (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) 9348 if (r_cas_fsm.read() != CAS_INVAL_IVT_LOCK) 9330 9349 { 9331 9350 if (r_config_fsm.read() == CONFIG_IVT_LOCK) … … 9375 9394 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 9376 9395 9377 else if ((r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) or 9378 (r_cas_fsm.read() == CAS_BC_IVT_LOCK)) 9396 else if (r_cas_fsm.read() == CAS_INVAL_IVT_LOCK) 9379 9397 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 9380 9398 … … 9405 9423 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 9406 9424 9407 else if ((r_cas_fsm.read() == CAS_MULTI_INVAL_IVT_LOCK) or 9408 (r_cas_fsm.read() == CAS_BC_IVT_LOCK)) 9425 else if (r_cas_fsm.read() == CAS_INVAL_IVT_LOCK) 9409 9426 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 9410 9427 … … 9562 9579 (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and 9563 9580 (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and 9564 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and9565 (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and9566 9581 (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 9567 (r_cas_fsm.read() != CAS_ MULTI_INVAL_IVT_LOCK) and9582 (r_cas_fsm.read() != CAS_INVAL_IVT_LOCK) and 9568 9583 (r_cas_fsm.read() != CAS_MULTI_INVAL_HEAP_LOCK)) 9569 9584 or … … 9633 9648 } 9634 9649 else 9635 m_cpt_ xram_rsp_fsm_dir_used++;9650 m_cpt_multi_ack_fsm_dir_used++; 9636 9651 break; 9637 9652 /////////////////////// … … 9720 9735 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9721 9736 9722 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 9723 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 9737 else if(r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9724 9738 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9725 9739 … … 9758 9772 (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) 9759 9773 { 9760 if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 9761 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 9774 if(r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9762 9775 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9763 9776 … … 9796 9809 //////////////////// 9797 9810 case ALLOC_TRT_CAS: 9798 if((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and 9799 (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and 9800 (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) 9811 if(r_cas_fsm.read() != CAS_MISS_TRT_LOCK) 9801 9812 { 9802 9813 if((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or … … 9863 9874 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9864 9875 9865 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 9866 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 9876 else if(r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9867 9877 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9868 } 9878 9879 else 9880 m_cpt_trt_unused++; 9881 9882 } 9883 else 9884 m_cpt_ixr_cmd_fsm_trt_used++; 9885 9869 9886 break; 9870 9887 … … 9893 9910 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9894 9911 9895 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 9896 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 9912 else if(r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9897 9913 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9898 9914 … … 9929 9945 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9930 9946 9931 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) || 9932 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 9947 else if(r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9933 9948 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9934 9949 … … 9949 9964 } 9950 9965 else 9951 m_cpt_ixr_ fsm_trt_used++;9966 m_cpt_ixr_rsp_fsm_trt_used++; 9952 9967 break; 9953 9968 … … 9966 9981 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9967 9982 9968 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 9969 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 9983 else if(r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9970 9984 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9971 9985 … … 9998 10012 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9999 10013 10000 else if((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or 10001 (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) 10014 else if(r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 10002 10015 r_alloc_trt_fsm = ALLOC_TRT_CAS; 10003 10016 … … 10020 10033 else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 10021 10034 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 10022 } 10035 10036 else 10037 m_cpt_trt_unused ++; 10038 } 10039 else 10040 m_cpt_cleanup_fsm_trt_used++; 10023 10041 break; 10024 10042 … … 10208 10226 } 10209 10227 else 10210 m_cpt_ cleanup_fsm_heap_used++;10228 m_cpt_multi_ack_fsm_heap_used++; 10211 10229 break; 10212 10230
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