Changeset 707
- Timestamp:
- Jun 5, 2014, 11:27:33 AM (11 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 1 added
- 4 edited
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genmap.py (added)
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top.cpp (modified) (39 diffs)
-
top.desc (modified) (1 diff)
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tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (1 diff)
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tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (modified) (12 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/top.cpp
r693 r707 1 1 /////////////////////////////////////////////////////////////////////////////// 2 // File: top.cpp 2 // File: top.cpp (for tsar_generic_iob platform) 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 … … 7 7 /////////////////////////////////////////////////////////////////////////////// 8 8 // This file define a generic TSAR architecture with an IO network emulating 9 // an external bus (i.e. Hypertransport) to access external peripherals:9 // an external bus (i.e. Hypertransport) to access 7 external peripherals: 10 10 // 11 11 // - BROM : boot ROM … … 15 15 // - CDMA : Chained Buffer DMA controller (up to 4 channels) 16 16 // - BDEV : Dlock Device controler (1 channel) 17 // 18 // The internal physical address space is 40 bits. 17 // - IOPI : HWI to SWI translator. 19 18 // 20 // It contains a 2D mesh of XMAX*YMAX clusters, and the cluster index 21 // is encoded on 8 bits (X_WIDTH = 4 / Y_WIDTH = 4) whatever the mesh size. 19 // The internal physical address space is 40 bits, and the cluster index 20 // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, 21 // Y is encodes on 4 bits, whatever the actual mesh size. 22 // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. 22 23 // 23 24 // It contains 3 networks: 24 25 // 25 // 1) the INTnetwork supports Read/Write transactions26 // 1) the "INT" network supports Read/Write transactions 26 27 // between processors and L2 caches or peripherals. 27 28 // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) 28 29 // It supports also coherence transactions between L1 & L2 caches. 29 // 3) the RAMnetwork is emulating the 3D network between L2 caches30 // 3) the "RAM" network is emulating the 3D network between L2 caches 30 31 // and L3 caches, and is implemented as a 2D mesh between the L2 caches, 31 32 // the two IO bridges and the physical RAMs disributed in all clusters. 32 33 // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) 33 34 // 4) the IOX network connects the two IO bridge components to the 34 // 6external peripheral controllers.35 // 7 external peripheral controllers. 35 36 // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) 36 37 // 37 // The external peripherals IRQs are connected to the XICU component 38 // in cluster(0,0): therefore, the number of channels for the external 39 // peripherals (MTTY, MNIC, CDMA) is limited by the number of IRQ ports... 38 // The external peripherals HWI IRQs are translated to WTI IRQs by the 39 // external IOPIC component, that must be configured by the OS to route 40 // these WTI ITQS to one or several internal XICU components. 41 // The total number of channels for the external peripherals (MTTY, MNIC, CDMA 42 // IOC or HBA) is limited by the IOPIC 32 HWI inputs:.. 43 // - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] 44 // - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] 45 // - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] 46 // - IOPIC HWI[8] connected to IRQ_BDEV 47 // - IOPIC HWI[15:9] unused (grounded) 48 // - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]] 49 // - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]] TBD 40 50 // 41 // In cluster(0,0), the XICU HWI input ports are connected as follow: 42 // - IRQ_IN[0] to IRQ_IN[7] grounded (reserved for PTI or SWI) 43 // - IRQ_IN[8] to IRQ_IN[9] are connected to 2 NIC_RX channels. 44 // - IRQ_IN[10] to IRQ_IN[11] are connected to 2 NIC_TX channels. 45 // - IRQ_IN[12] to IRQ_IN[15] are connected to 4 CDMA channels 46 // - IRQ_IN[16] to IRQ_IN[30] are connected to 15 TTY channels 47 // - IRQ_IN[31] is connected to BDEV 48 // In other clusters, the XICU HWI input ports are grounded. 51 // Besides the external peripherals, each cluster contains on XICU component, 52 // and one multi channels DMA component. 53 // The XICU component is mainly used to handle WTI IRQs, as only 2 HWI IRQs 54 // are connected to XICU in each cluster: 55 // - IRQ_IN[0] : MMC 56 // - IRQ_IN[1] : DMA channel 0 57 // - IRQ_IN[2] : DMA channel 1 58 // - IRQ_IN[3] : DMA channel 2 59 // - IRQ_IN[4] : DMA channel 3 49 60 // 50 61 // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) 51 62 // contain an extra IO bridge component. These IOB0 & IOB1 components are 52 63 // connected to the three networks (INT, RAM, IOX). 53 // The number of clusters cannot be larger than 256.54 // The number of processors per cluster cannot be larger than 4.55 64 // 56 65 // - It uses two dspin_local_crossbar per cluster to implement the … … 70 79 // 71 80 // The main hardware parameters must be defined in the hard_config.h file : 72 // - XMAX : number of clusters in a row (power of 2) 73 // - YMAX : number of clusters in a column (power of 2) 74 // - CLUSTER_SIZE : size of the segment allocated to a cluster 81 // - X_SIZE : number of clusters in a row 82 // - Y_SIZE : number of clusters in a column 75 83 // - NB_PROCS_MAX : number of processors per cluster (power of 2) 76 // - NB_ DMA_CHANNELS : number of DMA channels per cluster (< 9)77 // - NB_ TTY_CHANNELS : number of TTY channels in I/O network (< 16)78 // - NB_ NIC_CHANNELS : number of NIC channels in I/O network (< 9)84 // - NB_TTY_CHANNELS : number of TTY channels in I/O network (up to 16) 85 // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) 86 // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) 79 87 // 80 88 // Some secondary hardware parameters must be defined in this top.cpp file: … … 99 107 // The (x_width + y_width) MSB bits (left aligned) define 100 108 // the cluster index, and the LADR bits define the local index: 101 // | X_ID | Y_ID |---| LADR| OFFSET |102 // | x_width|y_width|---| 8| 24 |109 // |X_ID|Y_ID| LADR | OFFSET | 110 // | 4 | 4 | 8 | 24 | 103 111 // 104 112 // General policy for 14 bits SRCID decoding: 105 113 // Each component is identified by (x_id, y_id, l_id) tuple. 106 // | X_ID | Y_ID |---| L_ID |107 // | x_width|y_width|---| 6 |114 // |X_ID|Y_ID| L_ID | 115 // | 4 | 4 | 6 | 108 116 ///////////////////////////////////////////////////////////////////////// 109 117 … … 127 135 #include "vci_framebuffer.h" 128 136 #include "vci_iox_network.h" 137 #include "vci_iox_network.h" 138 #include "vci_iopic.h" 129 139 130 140 #include "alloc_elems.h" … … 179 189 //////////////////////i///////////////////////////////////// 180 190 181 #include " giet_vm/hard_config.h"191 #include "hard_config.h" 182 192 183 193 //////////////////////////////////////////////////////////// … … 238 248 239 249 #define IOBX_BASE 0x00BE000000 240 #define IOBX_SIZE 0x0000001000 // 4 K Kbytes250 #define IOBX_SIZE 0x0000001000 // 4 Kbytes 241 251 242 252 #define BDEV_BASE 0x00B3000000 243 #define BDEV_SIZE 0x000000 8000 // 4 Kbytes253 #define BDEV_SIZE 0x0000001000 // 4 Kbytes 244 254 245 255 #define MTTY_BASE 0x00B4000000 246 #define MTTY_SIZE 0x0000001000 * NB_TTY_CHANNELS// 4 Kbytes256 #define MTTY_SIZE 0x0000001000 // 4 Kbytes 247 257 248 258 #define MNIC_BASE 0x00B5000000 … … 250 260 251 261 #define CDMA_BASE 0x00B6000000 252 #define CDMA_SIZE 0x0000001000 * (NB_ NIC_CHANNELS * 2) // 4 Kbytes per channel262 #define CDMA_SIZE 0x0000001000 * (NB_CMA_CHANNELS) // 4 Kbytes per channel 253 263 254 264 #define FBUF_BASE 0x00B7000000 255 265 #define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE 256 266 267 #define IOPI_BASE 0x00B8000000 268 #define IOPI_SIZE 0x0000001000 // 4 Kbytes 269 257 270 // Replicated peripherals : address is incremented by a cluster offset 258 271 // offset = cluster(x,y) << (address_width-x_width-y_width); 259 272 260 273 #define XRAM_BASE 0x0000000000 261 #define XRAM_SIZE 0x00 10000000 // 256Mbytes274 #define XRAM_SIZE 0x0004000000 // 64 Mbytes 262 275 263 276 #define XICU_BASE 0x00B0000000 … … 287 300 // accessed in 2 clusters : cluster_iob0 and cluster_iob1. 288 301 // They have the same local index, but two different cluster indexes. 302 // 289 303 // As cluster_iob0 and cluster_iob1 contain both internal initiators 290 304 // and external initiators, they must have different local indexes. 291 305 // Consequence: For a local interconnect, the INI_ID port index 292 306 // is NOT equal to the SRCID local index, and the local interconnect 293 // must make a translation: SRCID => INI_ID (port index)307 // must make a translation: SRCID => INI_ID 294 308 //////////////////////////////////////////////////////////////////////// 295 309 … … 298 312 #define IOBX_LOCAL_SRCID 0x9 299 313 #define MEMC_LOCAL_SRCID 0xA 314 #define IOPI_LOCAL_SRCID 0xD 300 315 #define CDMA_LOCAL_SRCID 0xE // hard-coded in dspin_tsar 301 316 #define BDEV_LOCAL_SRCID 0xF // hard-coded in dspin_tsar … … 311 326 312 327 #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) 313 #define INT_MDMA_INI_ID NB_PROCS_MAX328 #define INT_MDMA_INI_ID (NB_PROCS_MAX) 314 329 #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) 315 330 … … 335 350 #define IOX_BROM_TGT_ID 6 336 351 #define IOX_MTTY_TGT_ID 7 352 #define IOX_IOPI_TGT_ID 8 337 353 338 354 #define IOX_IOB0_INI_ID 0 // Don't change this value … … 340 356 #define IOX_BDEV_INI_ID 2 341 357 #define IOX_CDMA_INI_ID 3 358 #define IOX_IOPI_INI_ID 4 342 359 343 360 //////////////////////////////////////////////////////////////////////// … … 360 377 size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc 361 378 size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc 379 size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram 362 380 bool debug_iob = false; // trace iob0 & iob1 when true 363 381 uint32_t debug_from = 0; // trace start cycle … … 401 419 if( (x>=XMAX) || (y>=YMAX) ) 402 420 { 403 std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; 421 std::cout << "MEMCID parameter does'nt fit XMAX/YMAX" << std::endl; 422 exit(0); 423 } 424 } 425 else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1<argc) ) 426 { 427 debug_xram_id = atoi(argv[n+1]); 428 size_t x = debug_xram_id >> 4; 429 size_t y = debug_xram_id & 0xF; 430 if( (x>=XMAX) || (y>=YMAX) ) 431 { 432 std::cout << "XRAMID parameter does'nt fit XMAX/YMAX" << std::endl; 404 433 exit(0); 405 434 } … … 447 476 std::cout << " -PERIOD number_of_cycles between trace" << std::endl; 448 477 std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; 478 std::cout << " -XRAMID index_xram_to_be_traced" << std::endl; 449 479 std::cout << " -PROCID index_proc_to_be_traced" << std::endl; 450 480 std::cout << " -IOB non_zero_value" << std::endl; … … 473 503 "The NB_NIC_CHANNELS parameter must be 2" ); 474 504 475 std::cout << std::endl; 476 std::cout << " - XMAX = " << XMAX << std::endl; 477 std::cout << " - YMAX = " << YMAX << std::endl; 478 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 479 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; 480 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; 481 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; 482 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 483 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 484 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 485 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 505 std::cout << std::endl << std::dec 506 << " - XMAX = " << XMAX << std::endl 507 << " - YMAX = " << YMAX << std::endl 508 << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl 509 << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl 510 << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl 511 << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl 512 << " - MEMC_WAYS = " << MEMC_WAYS << std::endl 513 << " - MEMC_SETS = " << MEMC_SETS << std::endl 514 << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl 515 << " - MAX_FROZEN = " << frozen_cycles << std::endl 516 << " - DEBUG_PROCID = " << debug_proc_id << std::endl 517 << " - DEBUG_MEMCID = " << debug_memc_id << std::endl 518 << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; 486 519 487 520 std::cout << std::endl; … … 597 630 maptab_int.add(Segment(sdma.str(), CDMA_BASE+offset, CDMA_SIZE, 598 631 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 632 633 std::ostringstream spic; 634 spic << "int_seg_iopi_" << x << "_" << y; 635 maptab_int.add(Segment(spic.str(), IOPI_BASE+offset, IOPI_SIZE, 636 IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); 599 637 } 600 638 … … 606 644 607 645 maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), 646 IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); 647 648 maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), 608 649 IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); 609 650 … … 667 708 // - two levels address decoding for commands 668 709 // - two levels srcid decoding for responses 669 // - 4 initiators (IOB0, IOB1, BDEV, CDMA)670 // - 8 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC)710 // - 5 initiators (IOB0, IOB1, BDEV, CDMA, IOPI) 711 // - 9 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) 671 712 /////////////////////////////////////////////////////////////////////// 672 713 MappingTable maptab_iox( vci_address_width, … … 679 720 uint64_t iob1_base = ((uint64_t)cluster_iob1) << (vci_address_width - x_width - y_width); 680 721 681 // Each peripheral can be accessed through two segments, 682 // depending on the used IOB (IOB0 or IOB1). 722 // External peripherals segments 723 // WHen there is more than one cluster, external peripherals can be accessed 724 // through two segments, depending on the used IOB (IOB0 or IOB1). 683 725 maptab_iox.add(Segment("iox_seg_mtty_0", MTTY_BASE + iob0_base, MTTY_SIZE, 684 726 IntTab(cluster_iob0,IOX_MTTY_TGT_ID), false)); 685 maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE,686 IntTab(cluster_iob1,IOX_MTTY_TGT_ID), false));687 688 727 maptab_iox.add(Segment("iox_seg_fbuf_0", FBUF_BASE + iob0_base, FBUF_SIZE, 689 728 IntTab(cluster_iob0,IOX_FBUF_TGT_ID), false)); 690 maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE,691 IntTab(cluster_iob1,IOX_FBUF_TGT_ID), false));692 693 729 maptab_iox.add(Segment("iox_seg_bdev_0", BDEV_BASE + iob0_base, BDEV_SIZE, 694 730 IntTab(cluster_iob0,IOX_BDEV_TGT_ID), false)); 695 maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE,696 IntTab(cluster_iob1,IOX_BDEV_TGT_ID), false));697 698 731 maptab_iox.add(Segment("iox_seg_mnic_0", MNIC_BASE + iob0_base, MNIC_SIZE, 699 732 IntTab(cluster_iob0,IOX_MNIC_TGT_ID), false)); 700 maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE,701 IntTab(cluster_iob1,IOX_MNIC_TGT_ID), false));702 703 733 maptab_iox.add(Segment("iox_seg_cdma_0", CDMA_BASE + iob0_base, CDMA_SIZE, 704 734 IntTab(cluster_iob0,IOX_CDMA_TGT_ID), false)); 705 maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE,706 IntTab(cluster_iob1,IOX_CDMA_TGT_ID), false));707 708 735 maptab_iox.add(Segment("iox_seg_brom_0", BROM_BASE + iob0_base, BROM_SIZE, 709 736 IntTab(cluster_iob0,IOX_BROM_TGT_ID), false)); 710 maptab_iox.add(Segment("iox_seg_brom_1", BROM_BASE + iob1_base, BROM_SIZE, 737 maptab_iox.add(Segment("iox_seg_iopi_0", IOPI_BASE + iob0_base, IOPI_SIZE, 738 IntTab(cluster_iob0,IOX_IOPI_TGT_ID), false)); 739 740 if ( cluster_iob0 != cluster_iob1 ) 741 { 742 maptab_iox.add(Segment("iox_seg_mtty_1", MTTY_BASE + iob1_base, MTTY_SIZE, 743 IntTab(cluster_iob1,IOX_MTTY_TGT_ID), false)); 744 maptab_iox.add(Segment("iox_seg_fbuf_1", FBUF_BASE + iob1_base, FBUF_SIZE, 745 IntTab(cluster_iob1,IOX_FBUF_TGT_ID), false)); 746 maptab_iox.add(Segment("iox_seg_bdev_1", BDEV_BASE + iob1_base, BDEV_SIZE, 747 IntTab(cluster_iob1,IOX_BDEV_TGT_ID), false)); 748 maptab_iox.add(Segment("iox_seg_mnic_1", MNIC_BASE + iob1_base, MNIC_SIZE, 749 IntTab(cluster_iob1,IOX_MNIC_TGT_ID), false)); 750 maptab_iox.add(Segment("iox_seg_cdma_1", CDMA_BASE + iob1_base, CDMA_SIZE, 751 IntTab(cluster_iob1,IOX_CDMA_TGT_ID), false)); 752 maptab_iox.add(Segment("iox_seg_brom_1", BROM_BASE + iob1_base, BROM_SIZE, 711 753 IntTab(cluster_iob1,IOX_BROM_TGT_ID), false)); 712 713 // Each physical RAM can be accessed through IOB0, or through IOB1. 714 // if IOMMU is not activated, addresses are 40 bits (physical addresses), 715 // and the choice depends on on address bit A[39]. 716 // if IOMMU is activated the addresses use only 32 bits (virtual addresses), 717 // and the choice depends on address bit A[31]. 754 maptab_iox.add(Segment("iox_seg_iopi_1", IOPI_BASE + iob1_base, IOPI_SIZE, 755 IntTab(cluster_iob1,IOX_IOPI_TGT_ID), false)); 756 } 757 758 // If there is more than one cluster, external peripherals 759 // can access RAM through two segments (IOB0 / IOB1). 760 // As IOMMU is not activated, addresses are 40 bits (physical addresses), 761 // and the choice depends on address bit A[39]. 718 762 for (size_t x = 0; x < XMAX; x++) 719 763 { … … 723 767 << (vci_address_width-x_width-y_width); 724 768 725 if ( x < (XMAX/2) ) // send command to XRAM through IOB0 769 if ( (cluster_iob0 != cluster_iob1) and (x >= (XMAX/2)) ) // use IOB1 770 { 771 std::ostringstream siob1; 772 siob1 << "iox_seg_xram_" << x << "_" << y; 773 maptab_iox.add(Segment(siob1.str(), offset, XRAM_SIZE, 774 IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); 775 } 776 else // USE IOB0 726 777 { 727 778 std::ostringstream siob0; 728 779 siob0 << "iox_seg_xram_" << x << "_" << y; 729 maptab_iox.add(Segment(siob0.str(), offset, 0x80000000,780 maptab_iox.add(Segment(siob0.str(), offset, XRAM_SIZE, 730 781 IntTab(cluster_iob0,IOX_IOB0_TGT_ID), false)); 731 }732 else // send command to XRAM through IOB1733 {734 std::ostringstream siob1;735 siob1 << "iox_seg_xram_" << x << "_" << y;736 maptab_iox.add(Segment(siob1.str(), offset, 0x80000000,737 IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false));738 782 } 739 783 } 740 784 } 741 // useful when IOMMU activated 742 maptab_iox.add(Segment("iox_seg_xram ", 0xc0000000, 0x40000000, 743 IntTab(cluster_iob1,IOX_IOB1_TGT_ID), false)); 744 745 // This define the mapping between the initiators (identified by the SRCID) 785 786 // This define the mapping between the external initiators (SRCID) 746 787 // and the port index on the IOX local interconnect. 747 // External initiator have two alias SRCID (iob0 / iob1 access)748 788 // If there is more than one cluster, external initiators 789 // have two alias SRCID (iob0 / iob1 access) 749 790 maptab_iox.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), 750 791 IntTab( cluster_iob0, IOX_CDMA_INI_ID ) ); 751 752 maptab_iox.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ),753 IntTab( cluster_iob1, IOX_CDMA_INI_ID ) );754 755 792 maptab_iox.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), 756 793 IntTab( cluster_iob0, IOX_BDEV_INI_ID ) ); 757 758 maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), 759 IntTab( cluster_iob0, IOX_BDEV_INI_ID ) ); 794 maptab_iox.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), 795 IntTab( cluster_iob0, IOX_IOPI_INI_ID ) ); 796 797 if ( cluster_iob0 != cluster_iob1 ) 798 { 799 maptab_iox.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), 800 IntTab( cluster_iob1, IOX_CDMA_INI_ID ) ); 801 maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), 802 IntTab( cluster_iob1, IOX_BDEV_INI_ID ) ); 803 maptab_iox.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), 804 IntTab( cluster_iob1, IOX_IOPI_INI_ID ) ); 805 } 806 807 // This define the mapping between the internal initiators (SRCID) 808 // and the port index on the IOX local interconnect. 809 // If there is more than one cluster, external initiators 760 810 761 811 for (size_t x = 0; x < XMAX; x++) … … 763 813 for (size_t y = 0; y < YMAX ; y++) 764 814 { 765 size_t iob = ( x < (XMAX/2) ) ? IOX_IOB0_INI_ID : IOX_IOB1_INI_ID; 766 767 for (size_t p = 0 ; p < NB_PROCS_MAX ; p++) 768 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID + p ), 769 IntTab( cluster(x,y), iob ) ); 770 771 maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 772 IntTab( cluster(x,y), IOX_IOB0_INI_ID ) ); 815 if ( (cluster_iob0 != cluster_iob1) and (x >= (XMAX/2)) ) // use IOB1 816 { 817 for (size_t p = 0 ; p < NB_PROCS_MAX ; p++) 818 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID + p ), 819 IntTab( cluster_iob1, IOX_IOB1_INI_ID ) ); 820 821 maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 822 IntTab( cluster_iob1, IOX_IOB1_INI_ID ) ); 823 } 824 else // USE IOB0 825 { 826 for (size_t p = 0 ; p < NB_PROCS_MAX ; p++) 827 maptab_iox.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID + p ), 828 IntTab( cluster_iob0, IOX_IOB0_INI_ID ) ); 829 830 maptab_iox.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), 831 IntTab( cluster_iob0, IOX_IOB0_INI_ID ) ); 832 } 773 833 } 774 834 } … … 787 847 sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; 788 848 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; 789 sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; 790 sc_signal<bool> signal_irq_cdma[NB_NIC_CHANNELS*2]; 849 sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS]; 850 // sc_signal<bool> signal_irq_mtty_tx[NB_TTY_CHANNELS]; 851 sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; 791 852 792 853 // DSPIN signals for loopback in cluster_iob0 & cluster_iob1 … … 801 862 VciSignals<vci_param_ext> signal_vci_ini_bdev("signal_vci_ini_bdev"); 802 863 VciSignals<vci_param_ext> signal_vci_ini_cdma("signal_vci_ini_cdma"); 864 VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); 803 865 804 866 VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); … … 810 872 VciSignals<vci_param_ext> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); 811 873 VciSignals<vci_param_ext> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); 874 VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_ini_iopi"); 812 875 813 876 // Horizontal inter-clusters INT network DSPIN … … 897 960 iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", 898 961 maptab_iox, 899 8, // number of targets900 4); // number of initiators962 9, // number of targets 963 5 ); // number of initiators 901 964 // boot ROM 902 965 VciSimpleRom<vci_param_ext>* brom; … … 950 1013 { 951 1014 std::ostringstream term_name; 952 term_name << "term" << tid; 953 vect_names.push_back(term_name.str().c_str()); 954 } 955 VciMultiTty<vci_param_ext>* mtty; 956 mtty = new VciMultiTty<vci_param_ext>( "mtty", 957 IntTab(0, IOX_MTTY_TGT_ID), 958 maptab_iox, 959 vect_names); 1015 term_name << "term" << tid; 1016 vect_names.push_back(term_name.str().c_str()); 1017 } 1018 VciMultiTty<vci_param_ext>* mtty; 1019 mtty = new VciMultiTty<vci_param_ext>( "mtty", 1020 IntTab(0, IOX_MTTY_TGT_ID), 1021 maptab_iox, 1022 vect_names); 1023 1024 // IOPIC 1025 VciIopic<vci_param_ext>* iopi; 1026 iopi = new VciIopic<vci_param_ext>( "iopi", 1027 maptab_iox, 1028 IntTab(0, IOPI_LOCAL_SRCID), 1029 IntTab(0, IOX_IOPI_TGT_ID), 1030 32, // number of input HWI 1031 5000 ); // period between WTI 960 1032 // Clusters 961 1033 TsarIobCluster<vci_param_int, … … 1061 1133 iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); 1062 1134 iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); 1135 iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); 1136 1063 1137 iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); 1064 1138 iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); … … 1069 1143 iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); 1070 1144 iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); 1145 iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); 1071 1146 1072 1147 // BDEV connexion … … 1115 1190 for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) 1116 1191 { 1117 mtty->p_irq[i] (signal_irq_mtty [i]);1192 mtty->p_irq[i] (signal_irq_mtty_rx[i]); 1118 1193 } 1119 1194 … … 1127 1202 for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) 1128 1203 { 1129 cdma->p_irq[i] 1204 cdma->p_irq[i] (signal_irq_cdma[i]); 1130 1205 } 1131 1206 1132 1207 std::cout << " - CDMA connected" << std::endl; 1133 1208 1134 // IRQ connexions from external peripherals (cluster_iob0 only) 1135 // IRQ_MNIC_RX -> IRQ[08] to IRQ[09] 1136 // IRQ_MNIC_TX -> IRQ[10] to IRQ[11] 1137 // IRQ_CDMA -> IRQ[12] to IRQ[15] 1138 // IRQ_MTTY -> IRQ[16] to IRQ[30] 1139 // IRQ_BDEV -> IRQ[31] 1140 1141 size_t mx = 16 + NB_TTY_CHANNELS; 1142 for ( size_t n=0 ; n<32 ; n++ ) 1209 // IOPI connexion 1210 iopi->p_clk (signal_clk); 1211 iopi->p_resetn (signal_resetn); 1212 iopi->p_vci_target (signal_vci_tgt_iopi); 1213 iopi->p_vci_initiator (signal_vci_ini_iopi); 1214 for ( size_t i=0 ; i<32 ; i++) 1143 1215 { 1144 if ( n < 8 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1145 1146 else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1147 // else if ( n < 10 ) (*clusters[0][0]->p_irq[n]) (signal_irq_mnic_rx[n-8]); 1148 1149 else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1150 // else if ( n < 12 ) (*clusters[0][0]->p_irq[n]) (signal_irq_mnic_tx[n-10]); 1151 1152 else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1153 // else if ( n < 16 ) (*clusters[0][0]->p_irq[n]) (signal_irq_cdma[n-12]); 1154 1155 else if ( n < mx ) (*clusters[0][0]->p_irq[n]) (signal_irq_mtty[n-16]); 1156 else if ( n < 31 ) (*clusters[0][0]->p_irq[n]) (signal_irq_false); 1157 1158 else (*clusters[0][0]->p_irq[n]) (signal_irq_bdev); 1216 if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); 1217 else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); 1218 else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); 1219 else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); 1220 else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); 1221 else if(i < 8) iopi->p_hwi[i] (signal_irq_false); 1222 else if(i == 8) iopi->p_hwi[i] (signal_irq_bdev); 1223 else if(i < 16) iopi->p_hwi[i] (signal_irq_false); 1224 else if(i < 16+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); 1225 else if(i < 24) iopi->p_hwi[i] (signal_irq_false); 1226 else if(i < 24+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_false); 1227 // else if(i < 24+NB_TTY_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_tx[i-24]); 1228 else iopi->p_hwi[i] (signal_irq_false); 1159 1229 } 1160 1230 1231 std::cout << " - IOPIC connected" << std::endl; 1232 1233 1161 1234 // IOB0 cluster connexion to IOX network 1162 (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); 1163 (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); 1164 1165 // IOB1 cluster connexion to IOX network 1166 (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); 1167 (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); 1235 (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); 1236 (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); 1237 1238 // IOB1 cluster connexion to IOX network 1239 // (only when there is more than 1 cluster) 1240 if ( cluster_iob0 != cluster_iob1 ) 1241 { 1242 (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); 1243 (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); 1244 } 1168 1245 1169 1246 // All clusters Clock & RESET connexions … … 1290 1367 } 1291 1368 1292 if( y == YMAX-1 )// handling IOB to RAM network connection in cluster_iob11369 if( (y == YMAX-1) and (cluster_iob0 != cluster_iob1) ) // handling IOB to RAM network connection in cluster_iob1 1293 1370 { 1294 1371 (*clusters[XMAX-1][YMAX-1]->p_dspin_iob_cmd_out) (signal_dspin_cmd_iob1_loopback); … … 1354 1431 signal_irq_false = false; 1355 1432 1433 // only one cluster case: 1434 if ( cluster_iob0 == cluster_iob1 ) 1435 { 1436 signal_vci_ini_iob1.cmdval = false; 1437 signal_vci_ini_iob1.rspack = true; 1438 signal_vci_tgt_iob1.cmdack = true; 1439 signal_vci_tgt_iob1.rspval = false; 1440 } 1441 1356 1442 // network boundaries signals 1357 1443 for (size_t x = 0; x < XMAX ; x++) … … 1393 1479 signal_resetn = true; 1394 1480 1481 1482 // simulation loop 1395 1483 struct timeval t1,t2; 1396 1484 gettimeofday(&t1, NULL); 1485 1397 1486 for (size_t n = 1; n < ncycles; n++) 1398 1487 { … … 1485 1574 smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; 1486 1575 clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); 1576 1487 1577 clusters[x][y]->xram->print_trace(); 1488 1578 std::ostringstream sxram_tgt; … … 1491 1581 } 1492 1582 1493 // trace RAM network routers 1494 // for( size_t cluster = 0 ; cluster < XMAX*YMAX ; cluster++ ) 1495 // { 1496 // size_t x = cluster / YMAX; 1497 // size_t y = cluster % YMAX; 1498 // clusters[x][y]->ram_router_cmd->print_trace(); 1499 // clusters[x][y]->ram_router_rsp->print_trace(); 1500 // } 1583 1584 // trace XRAM and XRAM network routers in cluster[debug_xram_id] 1585 if ( debug_xram_id != 0xFFFFFFFF ) 1586 { 1587 size_t x = debug_xram_id >> 4; 1588 size_t y = debug_xram_id & 0xF; 1589 1590 clusters[x][y]->xram->print_trace(); 1591 std::ostringstream sxram_tgt; 1592 sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; 1593 clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); 1594 1595 clusters[x][y]->ram_router_cmd->print_trace(); 1596 clusters[x][y]->ram_router_rsp->print_trace(); 1597 } 1501 1598 1502 1599 // trace iob, iox and external peripherals … … 1514 1611 // signal_dspin_rsp_iob0_loopback.print_trace("[SIG]IOB0_RSP_LOOPBACK"); 1515 1612 1516 1517 1518 1519 1520 //brom->print_trace();1521 //signal_vci_tgt_brom.print_trace("[SIG]IOX_BROM_TGT");1613 // cdma->print_trace(); 1614 // signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); 1615 // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); 1616 1617 brom->print_trace(); 1618 signal_vci_tgt_brom.print_trace("[SIG]IOX_BROM_TGT"); 1522 1619 1523 1620 // mtty->print_trace(); 1524 1621 // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); 1525 1622 1526 //bdev->print_trace();1527 // signal_vci_tgt_bdev.print_trace("[SIG]IOX_BDEV_TGT");1528 // signal_vci_ini_bdev.print_trace("[SIG]IOX_BDEV_INI");1623 bdev->print_trace(); 1624 signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 1625 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1529 1626 1530 1627 // fbuf->print_trace(); 1531 1628 // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); 1532 1629 1630 iopi->print_trace(); 1631 signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); 1632 signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); 1533 1633 iox_network->print_trace(); 1534 1634 1535 1635 // interrupts 1536 if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVATED" << std::endl; 1636 if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; 1637 if (signal_irq_mtty_rx[0]) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; 1537 1638 } 1538 1639 } -
trunk/platforms/tsar_generic_iob/top.desc
r450 r707 64 64 cell_size = vci_cell_size_ext), 65 65 66 # IOPIC 67 Uses('caba:vci_iopic', 68 cell_size = vci_cell_size_ext), 69 66 70 Uses('common:elf_file_loader'), 67 71 Uses('common:plain_file_loader'), -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r693 r707 61 61 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in; 62 62 63 // These ports are used to connect hard IRQ from external peripherals to IOB064 sc_in<bool>* p_irq[32];65 66 63 // These arrays of ports are used to connect the INT & RAM networks in top cell 67 64 soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r693 r707 110 110 p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>; 111 111 p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>; 112 }113 114 // IRQ ports in cluster_iob0 only115 if ( cluster_id == cluster_iob0 )116 {117 for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_in<bool>;118 112 } 119 113 … … 192 186 32, // number of hard IRQs 193 187 32, // number of soft IRQs 194 nb_procs);// number of output IRQs188 32); // number of output IRQs 195 189 196 190 //////////// MDMA … … 241 235 s_int_dspin_tgt_wrapper_gate_d.str().c_str(), 242 236 x_width + y_width + l_width); 243 244 237 245 238 //////////// Coherence LOCAL_XBAR(S) … … 283 276 1, 1, // fifo depths 284 277 true, // CMD 285 false, // don't use localrouting table278 false, // no routing table 286 279 false); // broadcast 287 280 … … 359 352 size_t iox_local_id; 360 353 size_t global_id; 361 bool has_irqs;362 354 if ( cluster_id == cluster_iob0 ) 363 355 { 364 356 iox_local_id = 0; 365 357 global_id = cluster_iob0; 366 has_irqs = true;367 358 } 368 359 else … … 370 361 iox_local_id = 1; 371 362 global_id = cluster_iob1; 372 has_irqs = false;373 363 } 374 364 … … 384 374 IntTab( global_id, iobx_int_srcid ), // INT SRCID 385 375 IntTab( global_id, iox_local_id ), // IOX TGTID 386 has_irqs,387 376 16, // cache line words 388 377 8, // IOTLB ways … … 511 500 proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); 512 501 proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); 513 proc[p]->p_irq[0] (signal_proc_it[p]); 514 for ( size_t j = 1; j < 6 ; j++)502 503 for ( size_t j = 0 ; j < 6 ; j++) 515 504 { 516 proc[p]->p_irq[j] (signal_false); 505 if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); 506 else proc[p]->p_irq[j] (signal_false); 517 507 } 518 508 } … … 522 512 xicu->p_resetn (this->p_resetn); 523 513 xicu->p_vci (signal_int_vci_tgt_xicu); 524 for ( size_t p=0 ; p <nb_procs; p++)514 for ( size_t p=0 ; p < 32 ; p++) 525 515 { 526 516 xicu->p_irq[p] (signal_proc_it[p]); … … 528 518 for ( size_t i=0 ; i<32 ; i++) 529 519 { 530 if (cluster_id == cluster_iob0) 531 xicu->p_hwi[i] (*(this->p_irq[i])); 532 else 533 xicu->p_hwi[i] (signal_false); 520 if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); 521 else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); 522 else xicu->p_hwi[i] (signal_false); 534 523 } 535 524 … … 572 561 573 562 //////////////////////////// RAM network CMD & RSP routers 574 ram_router_cmd->p_clk (this->p_clk);575 ram_router_cmd->p_resetn (this->p_resetn);576 ram_router_rsp->p_clk (this->p_clk);577 ram_router_rsp->p_resetn (this->p_resetn);563 ram_router_cmd->p_clk (this->p_clk); 564 ram_router_cmd->p_resetn (this->p_resetn); 565 ram_router_rsp->p_clk (this->p_clk); 566 ram_router_rsp->p_resetn (this->p_resetn); 578 567 for( size_t n=0 ; n<4 ; n++) 579 568 { 580 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);581 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);582 ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);583 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);584 } 585 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);586 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);587 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);588 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);569 ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); 570 ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); 571 ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); 572 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); 573 } 574 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); 575 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); 576 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 577 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); 589 578 590 579 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. … … 600 589 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); 601 590 602 if ( cluster_id == cluster_iob0 )603 for ( size_t n=0 ; n<32 ; n++ )604 (*iob->p_irq[n]) (*(this->p_irq[n]));605 606 591 // initiator wrapper to RAM network 607 592 iob_ram_wi->p_clk (this->p_clk);
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