Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 70)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 71)
@@ -2269,6 +2269,4 @@
     	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
     	{
-            bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update);
-            assert(write_hit && "Write on miss ignores data");
             r_dcache_itlb_ll_acc_req = true;
 	    r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    	
@@ -3153,7 +3151,4 @@
                 {
                     r_dcache_tlb_ptba_read = false;
-                    write_hit = r_dcache.write(((paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
-                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)), r_dcache_pte_update);
-                    //assert(write_hit && "Write on miss ignores data");
                     r_dcache_tlb_ll_dirty_req = true;
                     r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
@@ -3181,6 +3176,4 @@
                         r_dcache_pte_update = tlb_data | PTE_L_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
 			m_cpt_dcache_data_write++; 
@@ -3200,6 +3193,4 @@
                         r_dcache_pte_update = tlb_data | PTE_R_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
 			m_cpt_dcache_data_write++; 
@@ -3495,7 +3486,4 @@
                 {
                     r_dcache_tlb_ptba_read = false;
-                    write_hit = r_dcache.write(((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
-                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)),r_dcache_pte_update);
-                    //assert(write_hit && "Write on miss ignores data");
                     r_dcache_tlb_ll_dirty_req = true;
                     r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
@@ -3523,6 +3511,4 @@
                         r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
 			m_cpt_dcache_data_write++; 
@@ -3542,6 +3528,4 @@
                         r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
 			m_cpt_dcache_data_write++; 
@@ -3655,6 +3639,4 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
 			m_cpt_dcache_data_write++; 
@@ -3676,6 +3658,4 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
 			m_cpt_dcache_data_write++; 
@@ -3986,6 +3966,4 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
 			m_cpt_dcache_data_write++; 
@@ -4007,6 +3985,4 @@
 	        	r_dcache_ppn_update = tlb_data_ppn;
                         r_dcache_tlb_ll_acc_req = true;
-                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
-                	assert(write_hit && "Write on miss ignores data");  
                         r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
 			m_cpt_dcache_data_write++;