Changeset 711
- Timestamp:
- Jun 10, 2014, 11:29:40 AM (11 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r668 r711 473 473 { 474 474 // b0 : write buffer trace 475 // b1 : write buffer verbose476 475 // b2 : dcache trace 477 476 // b3 : icache trace … … 493 492 << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] 494 493 << " | MMU = " << r_mmu_mode.read(); 494 495 495 if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; 496 496 if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; … … 499 499 if(mode & 0x01) 500 500 { 501 if ( r_icache_miss_req.read() ) std::cout << " IMISS_REQ" << std::endl; 502 if ( r_icache_unc_req.read() ) std::cout << " IUNC_REQ" << std::endl; 503 if ( r_dcache_vci_miss_req.read() ) std::cout << " DMISS_REQ" << std::endl; 504 if ( r_dcache_vci_unc_req.read() ) std::cout << " DUNC_REQ" << std::endl; 505 501 506 r_wbuf.printTrace((mode>>1)&1); 502 507 } … … 1240 1245 if ( m_debug_icache_fsm ) 1241 1246 std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 1242 << " : PADDR = " << std::hex << paddr << std::endl; 1247 << " : PADDR = " << std::hex << paddr 1248 << " / INST = " << cache_inst << std::endl; 1243 1249 #endif 1244 1250 } … … 1700 1706 std::cout << " <PROC " << name() 1701 1707 << " ICACHE_MISS_DATA_UPDT> Write one word:" 1702 << " WDATA = " << r_vci_rsp_fifo_icache.read()1708 << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() 1703 1709 << " WAY = " << r_icache_miss_way.read() 1704 1710 << " SET = " << r_icache_miss_set.read() … … 2760 2766 std::cout << " <PROC " << name() << " DCACHE_IDLE>" 2761 2767 << " READ HIT in dcache" 2762 << " / PADDR = " << std::hex << paddr << std::endl; 2768 << " : PADDR = " << std::hex << paddr 2769 << " / DATA = " << std::hex << cache_rdata << std::endl; 2763 2770 #endif 2764 2771 } … … 4200 4207 4201 4208 // coherence request (from CC_RECEIVE FSM) 4202 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read()) 4209 if ( r_cc_receive_dcache_req.read() and 4210 not r_dcache_cc_send_req.read() and 4211 not r_dcache_cleanup_victim_req.read()) 4203 4212 { 4204 4213 r_dcache_fsm = DCACHE_CC_CHECK; … … 4333 4342 4334 4343 // coherence request (from CC_RECEIVE FSM) 4335 if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) 4344 if ( r_cc_receive_dcache_req.read() and 4345 not r_dcache_cc_send_req.read() and 4346 not r_dcache_cleanup_victim_req.read() ) 4336 4347 { 4337 4348 r_dcache_fsm = DCACHE_CC_CHECK;
Note: See TracChangeset
for help on using the changeset viewer.