Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 709)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 711)
@@ -473,5 +473,4 @@
 {
     // b0 : write buffer trace
-    // b1 : write buffer verbose
     // b2 : dcache trace
     // b3 : icache trace
@@ -493,4 +492,5 @@
               << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
               << " | MMU = " << r_mmu_mode.read();
+
     if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT";
     if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF";
@@ -499,4 +499,9 @@
     if(mode & 0x01)
     {
+        if ( r_icache_miss_req.read()     ) std::cout << "  IMISS_REQ" << std::endl;
+        if ( r_icache_unc_req.read()      ) std::cout << "  IUNC_REQ" << std::endl;
+        if ( r_dcache_vci_miss_req.read() ) std::cout << "  DMISS_REQ" << std::endl;
+        if ( r_dcache_vci_unc_req.read()  ) std::cout << "  DUNC_REQ" << std::endl;
+
         r_wbuf.printTrace((mode>>1)&1);
     }
@@ -1240,5 +1245,6 @@
 if ( m_debug_icache_fsm )
 std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 
-          << " : PADDR = " << std::hex << paddr << std::endl;
+          << " : PADDR = " << std::hex << paddr
+          << " / INST  = " << cache_inst << std::endl;
 #endif
                 }
@@ -1700,5 +1706,5 @@
     std::cout << "  <PROC " << name()
               << " ICACHE_MISS_DATA_UPDT> Write one word:"
-              << " WDATA = " << r_vci_rsp_fifo_icache.read()
+              << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
               << " WAY = " << r_icache_miss_way.read()
               << " SET = " << r_icache_miss_set.read()
@@ -2760,5 +2766,6 @@
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
           << " READ HIT in dcache" 
-          << " / PADDR = " << std::hex << paddr << std::endl;
+          << " : PADDR = " << std::hex << paddr 
+          << " / DATA  = " << std::hex << cache_rdata << std::endl;
 #endif
                             }
@@ -4200,5 +4207,7 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read())
+        if ( r_cc_receive_dcache_req.read() and 
+             not r_dcache_cc_send_req.read() and 
+             not r_dcache_cleanup_victim_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4333,5 +4342,7 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() )
+        if ( r_cc_receive_dcache_req.read() and 
+             not r_dcache_cc_send_req.read() and 
+             not r_dcache_cleanup_victim_req.read() )
         {
             r_dcache_fsm = DCACHE_CC_CHECK;