Changeset 712 for trunk/modules/vci_io_bridge/include

Timestamp:

Jun 10, 2014, 11:32:32 AM (11 years ago)

Author:

alain

Message:

Introducing support for read and write WTI transactions.
The WTI read transaction is used for IRQ reset.

File:

• trunk/modules/vci_io_bridge/include/soclib/io_bridge.h (modified) (3 diffs)

trunk/modules/vci_io_bridge/include/soclib/io_bridge.h

@@ -29 +29 @@
 
 // IOB Configuration registers
-// Minimal required segment size = 512 bytes (128 words)
+// Minimal required segment size = 64 bytes (16 words)
 enum 
 {
@@ -39 +39 @@
     IOB_INVAL_PTE        = 5,     // W    : Invalidate PTE (using virtual address)
     IOB_WTI_ENABLE       = 6,     // R/W  : Enable WTI (both IOB and external IRQs)
-    IOB_WTI_ADDR_LO      = 7,     // R/W  : WTI for IOB itself (32 LSB address bits)
-    IOB_WTI_ADDR_HI      = 8,     // R/W  : WTI for IOB itself (32 MSB address bits)
-    IOB_PERI_WTI_BEGIN   = 64,    // R/W  : two 32 bits words per IRQ
+    IOB_WTI_ADDR_LO      = 7,     // R/W  : IOB WTI address (32 LSB bits)
+    IOB_WTI_ADDR_HI      = 8,     // R/W  : IOB WTI address (32 MSB bits)
+    IOB_XICU_BASE        = 9,     // R/W  : XICU pbase address in cluster 0
+    IOB_XICU_SIZE        = 10,    // R/W  : XICU segment size 
     /**/
-    IOB_SPAN             = 128,                                
+    IOB_SPAN             = 16,                                
 };
 
@@ -51 +52 @@
 {
     MMU_NONE                      = 0x0000, // None
-    MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write access to a non writable page 
-    MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write Bus Error accessing Table 1       
-    MMU_READ_PT1_UNMAPPED             = 0x1001, // Read  Page fault on Page Table 1     
-    MMU_READ_PT2_UNMAPPED             = 0x1002, // Read  Page fault on Page Table 2  
-    MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read  Bus Error in Table1 access      
-    MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read  Bus Error in Table2 access         
+    MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write access to non writable page 
+    MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write Bus Error accessing Table 1
+    MMU_READ_PT1_UNMAPPED             = 0x1001, // Read  Page fault on Page Table 1 
+    MMU_READ_PT2_UNMAPPED             = 0x1002, // Read  Page fault on Page Table 2 
+    MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read  Bus Error in Table1 access 
+    MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read  Bus Error in Table2 access
     MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read  Bus Error in cache access 
 };