Changeset 712 for trunk/modules/vci_io_bridge/include/soclib
- Timestamp:
- Jun 10, 2014, 11:32:32 AM (10 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_io_bridge/include/soclib/io_bridge.h
r434 r712 29 29 30 30 // IOB Configuration registers 31 // Minimal required segment size = 512 bytes (128words)31 // Minimal required segment size = 64 bytes (16 words) 32 32 enum 33 33 { … … 39 39 IOB_INVAL_PTE = 5, // W : Invalidate PTE (using virtual address) 40 40 IOB_WTI_ENABLE = 6, // R/W : Enable WTI (both IOB and external IRQs) 41 IOB_WTI_ADDR_LO = 7, // R/W : WTI for IOB itself (32 LSB address bits) 42 IOB_WTI_ADDR_HI = 8, // R/W : WTI for IOB itself (32 MSB address bits) 43 IOB_PERI_WTI_BEGIN = 64, // R/W : two 32 bits words per IRQ 41 IOB_WTI_ADDR_LO = 7, // R/W : IOB WTI address (32 LSB bits) 42 IOB_WTI_ADDR_HI = 8, // R/W : IOB WTI address (32 MSB bits) 43 IOB_XICU_BASE = 9, // R/W : XICU pbase address in cluster 0 44 IOB_XICU_SIZE = 10, // R/W : XICU segment size 44 45 /**/ 45 IOB_SPAN = 1 28,46 IOB_SPAN = 16, 46 47 }; 47 48 … … 51 52 { 52 53 MMU_NONE = 0x0000, // None 53 MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access to anon writable page54 MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write Bus Error accessing Table 1 55 MMU_READ_PT1_UNMAPPED = 0x1001, // Read Page fault on Page Table 1 56 MMU_READ_PT2_UNMAPPED = 0x1002, // Read Page fault on Page Table 2 57 MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read Bus Error in Table1 access 58 MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read Bus Error in Table2 access 54 MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access to non writable page 55 MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write Bus Error accessing Table 1 56 MMU_READ_PT1_UNMAPPED = 0x1001, // Read Page fault on Page Table 1 57 MMU_READ_PT2_UNMAPPED = 0x1002, // Read Page fault on Page Table 2 58 MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read Bus Error in Table1 access 59 MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read Bus Error in Table2 access 59 60 MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read Bus Error in cache access 60 61 };
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