Index: /trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h =================================================================== --- /trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h (revision 711) +++ /trunk/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h (revision 712) @@ -37,10 +37,13 @@ // configuration or data transactions to peripherals. // -// Regarding DMA transactions initiated by external peripherals, it provides +// It supports two types of transactions from peripherals: +// - DMA transactions to the RAM network, +// - WTI transactions to the INT network. +// Regarding transactions initiated by external peripherals, it provides // an - optional - IOMMU service : the 32 bits virtual address is translated // to a (up to) 40 bits physical address by a standard SoCLib generic TLB. // In case of TLB MISS, the DMA transaction is stalled until the TLB is updated. -// In case of page fault (illegal access), a VCI error is returned to the -// faulty peripheral. +// In case of page fault or read_only violation (illegal access), a VCI error +// is returned to the faulty peripheral, and a IOMMU WTI is sent. ///////////////////////////////////////////////////////////////////////////////// // General Constraints: @@ -63,6 +66,4 @@ // - Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit // (seulement 'data' et 'be') -// - Traiter complêtement les codes d'erreur en réponse à une transaction -// WTI write /////////////////////////////////////////////////////////////////////////////// @@ -94,9 +95,9 @@ : public soclib::caba::BaseModule { - // Data and be fields have different widths on INT and EXT networks + // Data and be fields have different widths on INT and EXT/IOC networks typedef typename vci_param_ext::data_t ext_data_t; typedef typename vci_param_int::data_t int_data_t; typedef typename vci_param_ext::be_t ext_be_t; - typedef typename vci_param_int::be_t ext_in_t; + typedef typename vci_param_int::be_t int_be_t; // Other fields must be equal @@ -130,15 +131,21 @@ { DMA_CMD_IDLE, - DMA_CMD_FIFO_PUT_CMD, - DMA_CMD_FIFO_PUT_RSP, - DMA_CMD_MISS_WAIT, - DMA_CMD_WAIT_EOP, + DMA_CMD_DMA_REQ, + DMA_CMD_WTI_IOX_REQ, + DMA_CMD_ERR_WAIT_EOP, + DMA_CMD_ERR_WTI_REQ, + DMA_CMD_ERR_RSP_REQ, + DMA_CMD_TLB_MISS_WAIT, }; - // States for DMA_RSP FSM (from RAM to IOX) + // States for DMA_RSP FSM enum dma_rsp_fsm_state { - DMA_RSP_IDLE, - DMA_RSP_FIFO_PUT, + DMA_RSP_IDLE_DMA, + DMA_RSP_IDLE_WTI, + DMA_RSP_IDLE_ERR, + DMA_RSP_PUT_DMA, + DMA_RSP_PUT_WTI, + DMA_RSP_PUT_ERR, }; @@ -159,5 +166,5 @@ }; - // States for CONFIG_CMD FSM (from INT to IOX) + // States for CONFIG_CMD FSM enum config_cmd_fsm_state { @@ -168,26 +175,22 @@ }; - // states for CONFIG_RSP FSM (from IOX to INT) + // states for CONFIG_RSP FSM enum config_rsp_fsm_state { - CONFIG_RSP_IDLE, - CONFIG_RSP_PUT_LO, + CONFIG_RSP_IDLE_IOX, + CONFIG_RSP_IDLE_LOC, + CONFIG_RSP_PUT_LOW, CONFIG_RSP_PUT_HI, CONFIG_RSP_PUT_UNC, + CONFIG_RSP_PUT_LOC, + }; - // States for MISS_WTI_CMD FSM (to INT network) - enum miss_wti_cmd_state - { - MISS_WTI_CMD_IDLE, - MISS_WTI_CMD_WTI, - MISS_WTI_CMD_MISS, - }; - - // States for MISS_WTI_RSP FSM (from INT network) + // States for MISS_WTI_RSP FSM enum miss_wti_rsp_state { MISS_WTI_RSP_IDLE, - MISS_WTI_RSP_WTI, + MISS_WTI_RSP_WTI_IOX, + MISS_WTI_RSP_WTI_MMU, MISS_WTI_RSP_MISS, }; @@ -196,6 +199,7 @@ enum pktid_values_e { - PKTID_READ = 0x0, // TSAR code for read data uncached - PKTID_WRITE = 0x4, // TSAR code for write + PKTID_MISS = 0x0, // TSAR code for read data uncached + PKTID_WTI_IOX = 0x4, // TSAR code for write + PKTID_WTI_MMU = 0xC, // TSAR code for write }; @@ -210,5 +214,4 @@ sc_in p_clk; sc_in p_resetn; - sc_in* p_irq[32]; // not always constructed soclib::caba::VciInitiator p_vci_ini_ram; @@ -222,9 +225,8 @@ private: const size_t m_words; - const bool m_has_irqs; // INT & IOX Networks std::list m_int_seglist; - const vci_srcid_t m_int_srcid; // local SRCID on INT network + const vci_srcid_t m_int_srcid; // SRCID on INT network std::list m_iox_seglist; @@ -241,12 +243,15 @@ // MEMORY MAPPED REGISTERS /////////////////////////////// - sc_signal r_iommu_ptpr; // page table pointer register + sc_signal r_iommu_ptpr; // page table pointer sc_signal r_iommu_active; // iotlb mode - sc_signal r_iommu_bvar; // iommu bad virtual address - sc_signal r_iommu_etr; // iommu error type - sc_signal r_iommu_bad_id; // SRCID of faulty peripheral - sc_signal r_iommu_wti_enable; // enable WTI transactions - sc_signal r_iommu_wti_paddr; // address of IOMMU WTI - sc_signal* r_iommu_peri_wti; // array[32] WTI for peripherals + sc_signal r_iommu_bvar; // bad vaddr + sc_signal r_iommu_etr; // error type + sc_signal r_iommu_bad_id; // faulty srcid + sc_signal r_iommu_wti_enable; // enable IOB WTI + sc_signal r_iommu_wti_addr_lo; // IOMMU WTI paddr (32 lsb) + sc_signal r_iommu_wti_addr_hi; // IOMMU WTI paddr (32 msb) + + sc_signal r_xicu_base; // XICU paddr base (cluster 0) + sc_signal r_xicu_size; // XIXU paddr size (cluster 0) /////////////////////////////////// @@ -254,6 +259,23 @@ /////////////////////////////////// sc_signal r_dma_cmd_fsm; - sc_signal r_dma_cmd_vaddr; // input virtual address - sc_signal r_dma_cmd_paddr; // output physical address + sc_signal r_dma_cmd_paddr; // output paddr + + sc_signal r_dma_cmd_to_miss_wti_cmd_req; + sc_signal r_dma_cmd_to_miss_wti_cmd_addr; + sc_signal r_dma_cmd_to_miss_wti_cmd_cmd; + sc_signal r_dma_cmd_to_miss_wti_cmd_srcid; + sc_signal r_dma_cmd_to_miss_wti_cmd_trdid; + sc_signal r_dma_cmd_to_miss_wti_cmd_pktid; + sc_signal r_dma_cmd_to_miss_wti_cmd_wdata; + + sc_signal r_dma_cmd_to_dma_rsp_req; + sc_signal r_dma_cmd_to_dma_rsp_rsrcid; + sc_signal r_dma_cmd_to_dma_rsp_rtrdid; + sc_signal r_dma_cmd_to_dma_rsp_rpktid; + sc_signal r_dma_cmd_to_dma_rsp_rerror; + sc_signal r_dma_cmd_to_dma_rsp_rdata; + + sc_signal r_dma_cmd_to_tlb_req; + sc_signal r_dma_cmd_to_tlb_vaddr; // input vaddr /////////////////////////////////// @@ -266,7 +288,11 @@ /////////////////////////////////// sc_signal r_config_cmd_fsm; - sc_signal r_config_cmd_rdata; - sc_signal r_config_cmd_error; - sc_signal r_config_cmd_inval_vaddr; + + sc_signal r_config_cmd_to_tlb_req; + sc_signal r_config_cmd_to_tlb_vaddr; + + sc_signal r_config_cmd_to_config_rsp_req; + sc_signal r_config_cmd_to_config_rsp_rerror; + sc_signal r_config_cmd_to_config_rsp_rdata; sc_signal r_config_cmd_wdata; @@ -293,26 +319,22 @@ // TLB FSM REGISTERS /////////////////////////////////// - sc_signal r_tlb_fsm; // state register - sc_signal r_waiting_transaction; // Flag for returning from + sc_signal r_tlb_fsm; // state register + sc_signal r_waiting_transaction; // Flag for returning from sc_signal r_tlb_miss_type; sc_signal r_tlb_miss_error; - sc_signal r_tlb_paddr; // physical address of pte - sc_signal r_tlb_pte_flags; // pte1 or first word of pte2 - sc_signal r_tlb_pte_ppn; // second word of pte2 - sc_signal r_tlb_way; // selected way in tlb - sc_signal r_tlb_set; // selected set in tlb - - uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs - sc_signal r_tlb_buf_valid; // one valit flag for all PTEs - sc_signal r_tlb_buf_tag; // cache line number - sc_signal r_tlb_buf_vaddr; // virtual address first PTE - sc_signal r_tlb_buf_big_page; // ??? - - /////////////////////////////////// - // MISS_WTI_CMD FSM REGISTERS - /////////////////////////////////// - sc_signal r_miss_wti_cmd_fsm; - sc_signal r_miss_wti_cmd_index; + sc_signal r_tlb_paddr; // physical address of pte + sc_signal r_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_tlb_pte_ppn; // second word of pte2 + sc_signal r_tlb_way; // selected way in tlb + sc_signal r_tlb_set; // selected set in tlb + + uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs + sc_signal r_tlb_buf_valid; // one valit flag for all PTEs + sc_signal r_tlb_buf_tag; // cache line number + sc_signal r_tlb_buf_vaddr; // vaddr for first PTE + sc_signal r_tlb_buf_big_page; // ??? + + sc_signal r_tlb_to_miss_wti_cmd_req; /////////////////////////////////// @@ -320,6 +342,14 @@ /////////////////////////////////// sc_signal r_miss_wti_rsp_fsm; - sc_signal r_miss_wti_rsp_error; - sc_signal r_miss_wti_rsp_count; + sc_signal r_miss_wti_rsp_error_wti; // VCI error on WTI + sc_signal r_miss_wti_rsp_error_miss; // VCI error on MISS + sc_signal r_miss_wti_rsp_count; // flits counter + + sc_signal r_miss_wti_rsp_to_dma_rsp_req; + sc_signal r_miss_wti_rsp_to_dma_rsp_rerror; + sc_signal r_miss_wti_rsp_to_dma_rsp_rsrcid; + sc_signal r_miss_wti_rsp_to_dma_rsp_rtrdid; + sc_signal r_miss_wti_rsp_to_dma_rsp_rpktid; + ///////////////////////////////////////////////////// @@ -327,11 +357,5 @@ ///////////////////////////////////////////////////// sc_signal r_alloc_fifo_config_rsp_local; - sc_signal r_alloc_fifo_dma_rsp_local; - - ////////////////////////////////// - // IRQ FSM registers - ////////////////////////////////// - sc_signal* r_irq_pending; // array[32] - sc_signal* r_irq_request; // array[32] + ////////////////////////////////////////////////////////////////// @@ -340,16 +364,4 @@ GenericTlb r_iotlb; - ////////////////////////////////////////////////////////////////// - // Inter-FSM communications - ////////////////////////////////////////////////////////////////// - - // between DMA_CMD and TLB FSM - sc_signal r_dma_tlb_req; - - // between CONFIG_CMD FSM and TLB FSM - sc_signal r_config_tlb_req; - - // between TLB FSM and MISS_WTI FSM - sc_signal r_tlb_miss_req; ///////////////////////// @@ -405,5 +417,20 @@ GenericFifo m_config_rsp_rerror_fifo; - + // output FIFO to VCI_INI port on INT network (VCI command) + GenericFifo m_miss_wti_cmd_addr_fifo; + GenericFifo m_miss_wti_cmd_srcid_fifo; + GenericFifo m_miss_wti_cmd_trdid_fifo; + GenericFifo m_miss_wti_cmd_pktid_fifo; + GenericFifo m_miss_wti_cmd_be_fifo; + GenericFifo m_miss_wti_cmd_cmd_fifo; + GenericFifo m_miss_wti_cmd_contig_fifo; + GenericFifo m_miss_wti_cmd_data_fifo; + GenericFifo m_miss_wti_cmd_eop_fifo; + GenericFifo m_miss_wti_cmd_cons_fifo; + GenericFifo m_miss_wti_cmd_plen_fifo; + GenericFifo m_miss_wti_cmd_wrap_fifo; + GenericFifo m_miss_wti_cmd_cfixed_fifo; + GenericFifo m_miss_wti_cmd_clen_fifo; + //////////////////////////////// // Activity counters @@ -432,11 +459,12 @@ uint32_t m_cpt_fsm_config_cmd [32]; uint32_t m_cpt_fsm_config_rsp [32]; - uint32_t m_cpt_fsm_miss_wti_cmd [32]; uint32_t m_cpt_fsm_miss_wti_rsp [32]; protected: + SC_HAS_PROCESS(VciIoBridge); public: + VciIoBridge( sc_module_name insname, @@ -447,5 +475,4 @@ const soclib::common::IntTab &int_srcid, // INT network SRCID const soclib::common::IntTab &iox_tgtid, // IOX network TGTID - const bool has_irqs, // component has irq ports const size_t dcache_words, const size_t iotlb_ways, @@ -462,4 +489,6 @@ private: + + bool is_wti( vci_addr_t paddr ); void transition(); void genMoore(); Index: /trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp =================================================================== --- /trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 711) +++ /trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 712) @@ -43,5 +43,5 @@ #define DEBUG_CONFIG_CMD 1 #define DEBUG_CONFIG_RSP 1 -#define DEBUG_MISS_WTI 1 +#define DEBUG_MISS_WTI_CMD 1 namespace soclib { @@ -53,14 +53,20 @@ { "DMA_CMD_IDLE", - "DMA_CMD_FIFO_PUT_CMD", - "DMA_CMD_FIFO_PUT_RSP", - "DMA_CMD_MISS_WAIT", - "DMA_CMD_WAIT_EOP", + "DMA_CMD_DMA_REQ", + "DMA_CMD_WTI_IOX_REQ", + "DMA_CMD_ERR_WAIT_EOP", + "DMA_CMD_ERR_WTI_REQ", + "DMA_CMD_ERR_RSP_REQ", + "DMA_CMD_TLB_MISS_WAIT", }; const char *dma_rsp_fsm_state_str[] = { - "DMA_RSP_IDLE", - "DMA_RSP_FIFO_PUT", + "DMA_RSP_IDLE_DMA", + "DMA_RSP_IDLE_WTI", + "DMA_RSP_IDLE_ERR", + "DMA_RSP_PUT_DMA", + "DMA_RSP_PUT_WTI", + "DMA_RSP_PUT_ERR", }; @@ -90,20 +96,17 @@ const char *config_rsp_fsm_state_str[] = { - "CONFIG_RSP_IDLE", - "CONFIG_RSP_PUT_LO", + "CONFIG_RSP_IDLE_IOX", + "CONFIG_RSP_IDLE_LOC", + "CONFIG_RSP_PUT_LOW", "CONFIG_RSP_PUT_HI", "CONFIG_RSP_PUT_UNC", + "CONFIG_RSP_PUT_LOC", }; -const char *miss_wti_cmd_state_str[] = - { - "MISS_WTI_CMD_IDLE", - "MISS_WTI_CMD_WTI", - "MISS_WTI_CMD_MISS", - }; const char *miss_wti_rsp_state_str[] = { "MISS_WTI_RSP_IDLE", - "MISS_WTI_RSP_WTI", + "MISS_WTI_RSP_WTI_IOX", + "MISS_WTI_RSP_WTI_MMU", "MISS_WTI_RSP_MISS", }; @@ -121,5 +124,4 @@ const soclib::common::IntTab &int_srcid, // INT network SRCID const soclib::common::IntTab &iox_tgtid, // IOX network TGTID - const bool has_irqs, const size_t dcache_words, const size_t iotlb_ways, @@ -138,5 +140,4 @@ m_words( dcache_words ), - m_has_irqs( has_irqs ), // INT & IOX Network @@ -157,12 +158,26 @@ r_iommu_etr("r_iommu_etr"), r_iommu_bad_id("r_iommu_bad_id"), - r_iommu_wti_paddr("r_iommu_wti_paddr"), - r_iommu_peri_wti(alloc_elems >("r_peri_wti_paddr", 32)), + r_iommu_wti_enable("r_iommu_wti_enable"), + r_iommu_wti_addr_lo("r_iommu_wti_addr_lo"), // DMA_CMD FSM registers r_dma_cmd_fsm("r_dma_cmd_fsm"), - r_dma_cmd_vaddr("r_dma_cmd_vaddr"), r_dma_cmd_paddr("r_dma_cmd_paddr"), + r_dma_cmd_to_miss_wti_cmd_req("r_dma_cmd_to_miss_wti_cmd_req"), + r_dma_cmd_to_miss_wti_cmd_addr("r_dma_cmd_to_miss_wti_cmd_addr"), + r_dma_cmd_to_miss_wti_cmd_srcid("r_dma_cmd_to_miss_wti_cmd_srcid"), + r_dma_cmd_to_miss_wti_cmd_trdid("r_dma_cmd_to_miss_wti_cmd_trdid"), + r_dma_cmd_to_miss_wti_cmd_pktid("r_dma_cmd_to_miss_wti_cmd_pktid"), + r_dma_cmd_to_miss_wti_cmd_wdata("r_dma_cmd_to_miss_wti_cmd_wdata"), + + r_dma_cmd_to_dma_rsp_req("r_dma_cmd_to_dma_rsp_req"), + r_dma_cmd_to_dma_rsp_rsrcid("r_dma_cmd_to_dma_rsp_rsrcid"), + r_dma_cmd_to_dma_rsp_rtrdid("r_dma_cmd_to_dma_rsp_rtrdid"), + r_dma_cmd_to_dma_rsp_rpktid("r_dma_cmd_to_dma_rsp_rpktid"), + + r_dma_cmd_to_tlb_req("r_dma_cmd_to_tlb_req"), + r_dma_cmd_to_tlb_vaddr("r_dma_cmd_to_tlb_vaddr"), + //DMA_RSP FSM registers r_dma_rsp_fsm("r_dma_rsp_fsm"), @@ -170,7 +185,12 @@ // CONFIG_CMD FSM registers r_config_cmd_fsm("r_config_cmd_fsm"), - r_config_cmd_rdata("r_config_cmd_rdata"), - r_config_cmd_error("r_config_cmd_error"), - r_config_cmd_inval_vaddr("r_config_cmd_inval_vaddr"), + + r_config_cmd_to_tlb_req("r_config_cmd_to_tlb_req"), + r_config_cmd_to_tlb_vaddr("r_config_cmd_to_tlb_vaddr"), + + r_config_cmd_to_config_rsp_req("r_config_cmd_to_config_rsp_req"), + r_config_cmd_to_config_rsp_rerror("r_config_cmd_to_config_rsp_rerror"), + r_config_cmd_to_config_rsp_rdata("r_config_cmd_to_config_rsp_rdata"), + r_config_cmd_wdata("r_config_cmd_wdata"), r_config_cmd_be("r_config_cmd_be"), @@ -196,9 +216,11 @@ r_tlb_miss_type("r_tlb_miss_type"), r_tlb_miss_error("r_tlb_miss_error"), + r_tlb_paddr("r_tlb_paddr"), r_tlb_pte_flags("r_tlb_pte_flags"), r_tlb_pte_ppn("r_tlb_pte_ppn"), r_tlb_way("r_tlb_way"), - r_tlb_set("r_tlb_set"), + r_tlb_set("r_tlb_set"), + r_tlb_buf_valid("r_tlb_buf_valid"), r_tlb_buf_tag("r_tlb_buf_tag"), @@ -206,28 +228,21 @@ r_tlb_buf_big_page("r_tlb_buf_big_page"), - // MISS_WTI_CMD FSM registers - r_miss_wti_cmd_fsm("r_miss_wti_cmd_fsm"), - r_miss_wti_cmd_index("r_miss_wti_cmd_index"), - - // MISS_WTI_CMD FSM registers + r_tlb_to_miss_wti_cmd_req("r_tlb_to_miss_wti_cmd_req"), + + // MISS_WTI_RSP FSM registers r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), - r_miss_wti_rsp_error("r_miss_wti_rsp_error"), - - // allocator for CONFIG_RSP & DMA_RSP fifos - r_alloc_fifo_config_rsp_local("r_alloc_fifo_config_rsp_local"), - r_alloc_fifo_dma_rsp_local("r_alloc_fifo_dma_rsp_local"), - - // IRQs registers - r_irq_pending(alloc_elems >("r_irq_pending", 32)), - r_irq_request(alloc_elems >("r_irq_request", 32)), - + r_miss_wti_rsp_error_wti("r_miss_wti_rsp_error_wti"), + r_miss_wti_rsp_error_miss("r_miss_wti_rsp_error_miss"), + r_miss_wti_rsp_count("r_miss_wti_rsp_count"), + + r_miss_wti_rsp_to_dma_rsp_req("r_miss_wti_rsp_to_dma_rsp_req"), + r_miss_wti_rsp_to_dma_rsp_rerror("r_miss_wti_rsp_to_dma_rsp_rerror"), + r_miss_wti_rsp_to_dma_rsp_rsrcid("r_miss_wti_rsp_to_dma_rsp_rsrcid"), + r_miss_wti_rsp_to_dma_rsp_rtrdid("r_miss_wti_rsp_to_dma_rsp_rtrdid"), + r_miss_wti_rsp_to_dma_rsp_rpktid("r_miss_wti_rsp_to_dma_rsp_rpktid"), + // TLB for IOMMU r_iotlb("iotlb", 0, iotlb_ways, iotlb_sets, vci_param_int::N), - // Inter-FSM communications - r_dma_tlb_req("r_dma_tlb_req"), - r_config_tlb_req("r_config_tlb_req"), - r_tlb_miss_req("r_tlb_miss_req"), - // DMA_CMD FIFOs m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",2), @@ -276,5 +291,21 @@ m_config_rsp_rpktid_fifo("m_config_rsp_rpktid_fifo",2), m_config_rsp_reop_fifo("m_config_rsp_reop_fifo",2), - m_config_rsp_rerror_fifo("m_config_rsp_rerror_fifo",2) + m_config_rsp_rerror_fifo("m_config_rsp_rerror_fifo",2), + + // MISS_WTI_CMD FIFOs + m_miss_wti_cmd_addr_fifo("m_miss_wti_cmd_addr_fifo",2), + m_miss_wti_cmd_srcid_fifo("m_miss_wti_cmd_srcid_fifo",2), + m_miss_wti_cmd_trdid_fifo("m_miss_wti_cmd_trdid_fifo",2), + m_miss_wti_cmd_pktid_fifo("m_miss_wti_cmd_pktid_fifo",2), + m_miss_wti_cmd_be_fifo("m_miss_wti_cmd_be_fifo",2), + m_miss_wti_cmd_cmd_fifo("m_miss_wti_cmd_cmd_fifo",2), + m_miss_wti_cmd_contig_fifo("m_miss_wti_cmd_contig_fifo",2), + m_miss_wti_cmd_data_fifo("m_miss_wti_cmd_data_fifo",2), + m_miss_wti_cmd_eop_fifo("m_miss_wti_cmd_eop_fifo",2), + m_miss_wti_cmd_cons_fifo("m_miss_wti_cmd_cons_fifo",2), + m_miss_wti_cmd_plen_fifo("m_miss_wti_cmd_plen_fifo",2), + m_miss_wti_cmd_wrap_fifo("m_miss_wti_cmd_wrap_fifo",2), + m_miss_wti_cmd_cfixed_fifo("m_miss_wti_cmd_cfixed_fifo",2), + m_miss_wti_cmd_clen_fifo("m_miss_wti_cmd_clen_fifo",2) { std::cout << " - Building VciIoBridge : " << name << std::endl; @@ -320,10 +351,4 @@ "VCI_IO_BRIDGE ERROR: SRCID widths must be equal on the 3 networks"); - // contruct 32 IRQ ports if required - if ( has_irqs ) - { - for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_core::sc_in; - } - // Cache line buffer r_tlb_buf_data = new uint32_t[dcache_words]; @@ -343,9 +368,5 @@ ///////////////////////////////////// { - delete [] r_iommu_peri_wti; delete [] r_tlb_buf_data; - soclib::common::dealloc_elems(p_irq, 32); - soclib::common::dealloc_elems(r_irq_request, 32); - soclib::common::dealloc_elems(r_irq_pending, 32); } @@ -363,5 +384,4 @@ << " | " << config_cmd_fsm_state_str[r_config_cmd_fsm.read()] << " | " << config_rsp_fsm_state_str[r_config_rsp_fsm.read()] - << " | " << miss_wti_cmd_state_str[r_miss_wti_cmd_fsm.read()] << " | " << miss_wti_rsp_state_str[r_miss_wti_rsp_fsm.read()] << std::endl; @@ -396,4 +416,14 @@ } +//////////////////////////////////// +tmpl(bool)::is_wti(vci_addr_t paddr) +//////////////////////////////////// +{ + uint32_t addr32 = (uint32_t)paddr; + uint32_t base = r_xicu_base.read(); + uint32_t size = r_xicu_size.read(); + return ( (addr32 >= base) and (addr32 < (base + size)) ); +} + ///////////////////////// tmpl(void)::transition() @@ -403,18 +433,17 @@ { r_dma_cmd_fsm = DMA_CMD_IDLE; - r_dma_rsp_fsm = DMA_RSP_IDLE; + r_dma_rsp_fsm = DMA_RSP_IDLE_DMA; r_tlb_fsm = TLB_IDLE; r_config_cmd_fsm = CONFIG_CMD_IDLE; - r_config_rsp_fsm = CONFIG_RSP_IDLE; - r_miss_wti_cmd_fsm = MISS_WTI_CMD_IDLE; + r_config_rsp_fsm = CONFIG_RSP_IDLE_IOX; r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; - - r_alloc_fifo_config_rsp_local = true; - r_alloc_fifo_dma_rsp_local = true; r_tlb_buf_valid = false; r_iommu_active = false; r_iommu_wti_enable = false; - + + r_xicu_size = 0; + r_xicu_base = 0; + // initializing FIFOs m_dma_cmd_addr_fifo.init(); @@ -455,4 +484,19 @@ m_config_cmd_clen_fifo.init(); + m_miss_wti_cmd_addr_fifo.init(); + m_miss_wti_cmd_srcid_fifo.init(); + m_miss_wti_cmd_trdid_fifo.init(); + m_miss_wti_cmd_pktid_fifo.init(); + m_miss_wti_cmd_be_fifo.init(); + m_miss_wti_cmd_cmd_fifo.init(); + m_miss_wti_cmd_contig_fifo.init(); + m_miss_wti_cmd_data_fifo.init(); + m_miss_wti_cmd_eop_fifo.init(); + m_miss_wti_cmd_cons_fifo.init(); + m_miss_wti_cmd_plen_fifo.init(); + m_miss_wti_cmd_wrap_fifo.init(); + m_miss_wti_cmd_cfixed_fifo.init(); + m_miss_wti_cmd_clen_fifo.init(); + m_config_rsp_rsrcid_fifo.init(); m_config_rsp_rtrdid_fifo.init(); @@ -463,28 +507,30 @@ // SET/RESET Communication flip-flops - r_dma_tlb_req = false; - r_config_tlb_req = false; - r_tlb_miss_req = false; + r_dma_cmd_to_miss_wti_cmd_req = false; + r_dma_cmd_to_dma_rsp_req = false; + r_dma_cmd_to_tlb_req = false; + r_config_cmd_to_tlb_req = false; + r_config_cmd_to_config_rsp_req = false; + r_tlb_to_miss_wti_cmd_req = false; + r_miss_wti_rsp_to_dma_rsp_req = false; + + // error flip_flops + r_miss_wti_rsp_error_miss = false; + r_miss_wti_rsp_error_wti = false; // Debug variable - m_debug_activated = false; + m_debug_activated = false; - for ( size_t n=0 ; n<32 ; n++ ) - { - r_irq_pending[n] = false; - r_irq_request[n] = false; - } - // activity counters - m_cpt_total_cycles = 0; - m_cpt_iotlb_read = 0; - m_cpt_iotlb_miss = 0; - m_cpt_iotlbmiss_transaction = 0; - m_cost_iotlbmiss_transaction = 0; + m_cpt_total_cycles = 0; + m_cpt_iotlb_read = 0; + m_cpt_iotlb_miss = 0; + m_cpt_iotlbmiss_transaction = 0; + m_cost_iotlbmiss_transaction = 0; - m_cpt_trt_dma_full = 0; - m_cpt_trt_dma_full_cost = 0; - m_cpt_trt_config_full = 0; - m_cpt_trt_config_full_cost = 0; + m_cpt_trt_dma_full = 0; + m_cpt_trt_dma_full_cost = 0; + m_cpt_trt_config_full = 0; + m_cpt_trt_config_full_cost = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_cmd [i] = 0; @@ -493,5 +539,4 @@ for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_cmd [i] = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_rsp [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_wti_cmd [i] = 0; for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_wti_rsp [i] = 0; @@ -499,16 +544,37 @@ } - // default values for FIFOs - bool dma_cmd_fifo_put = false; - bool dma_cmd_fifo_get = false; - - bool dma_rsp_fifo_put = false; - bool dma_rsp_fifo_get = false; + // default values for the 5 FIFOs + bool dma_cmd_fifo_put = false; + bool dma_cmd_fifo_get = p_vci_ini_ram.cmdack.read(); - bool config_cmd_fifo_put = false; - bool config_cmd_fifo_get = false; - - bool config_rsp_fifo_put = false; - bool config_rsp_fifo_get = false; + bool dma_rsp_fifo_put = false; + bool dma_rsp_fifo_get = p_vci_tgt_iox.rspack.read(); + vci_rerror_t dma_rsp_fifo_rerror = 0; + vci_srcid_t dma_rsp_fifo_rsrcid = 0; + vci_trdid_t dma_rsp_fifo_rtrdid = 0; + vci_pktid_t dma_rsp_fifo_rpktid = 0; + ext_data_t dma_rsp_fifo_rdata = 0; + bool dma_rsp_fifo_reop = false; + + bool config_cmd_fifo_put = false; + bool config_cmd_fifo_get = p_vci_ini_iox.cmdack.read(); + + bool config_rsp_fifo_put = false; + bool config_rsp_fifo_get = p_vci_tgt_int.rspack.read(); + vci_rerror_t config_rsp_fifo_rerror = 0; + vci_srcid_t config_rsp_fifo_rsrcid = 0; + vci_trdid_t config_rsp_fifo_rtrdid = 0; + vci_pktid_t config_rsp_fifo_rpktid = 0; + ext_data_t config_rsp_fifo_rdata = 0; + bool config_rsp_fifo_reop = false; + + bool miss_wti_cmd_fifo_put = false; + bool miss_wti_cmd_fifo_get = p_vci_ini_int.cmdack.read(); + vci_addr_t miss_wti_cmd_fifo_address = 0; + vci_cmd_t miss_wti_cmd_fifo_cmd = 0; + vci_srcid_t miss_wti_cmd_fifo_srcid = 0; + vci_trdid_t miss_wti_cmd_fifo_trdid = 0; + vci_pktid_t miss_wti_cmd_fifo_pktid = 0; + int_data_t miss_wti_cmd_fifo_wdata = 0; #ifdef INSTRUMENTATION @@ -518,5 +584,4 @@ m_cpt_fsm_config_cmd [r_config_cmd_fsm.read() ] ++; m_cpt_fsm_config_rsp [r_config_rsp_fsm.read() ] ++; - m_cpt_fsm_miss_wti_cmd [r_miss_wti_cmd_fsm.read() ] ++; m_cpt_fsm_miss_wti_rsp [r_miss_wti_rsp_fsm.read() ] ++; #endif @@ -527,6 +592,17 @@ ////////////////////////////////////////////////////////////////////////////// - // The DMA_CMD_FSM handles DMA transactions requested by peripherals - // It makes the address translation if IOMMU is activated. + // The DMA_CMD_FSM handles transactions requested by peripherals. + // - it can be DMA transactions to RAM network (DMA_REQ state). + // - it can be WTI transactions to INT network (EXT_WTI_REQ state). + // It makes the address translation if IOMMU is activated, requesting + // the TLB_MISS FSM in case of TLB miss (TLB_MISS_WAIT state). + // When the IOMMU is activated, a DMA request can fail in two cases: + // - write to a read-only address : detected in IDLE state + // - virtual address unmapped : detected in MISS_WAIT state + // In both cases of violation, the DMA_CMD FSM makes the following actions : + // 1. register the error in r_iommu_*** registers + // 2. wait the faulty command EOP (ERR_WAIT_EOP state) + // 3. request a IOMMU WTI to MISS_WTI FSM, (ERR_WTI_REQ state) + // 4. request a response error to DMA_RSP FSM (ERR_RSP_REQ state) /////////////////////////////////////////////////////////////////////////////// @@ -534,25 +610,38 @@ { ////////////////// - case DMA_CMD_IDLE: // waiting DMA VCI transaction - { - if ( p_vci_tgt_iox.cmdval.read() ) // compute physical address + case DMA_CMD_IDLE: // wait a DMA or WTI VCI transaction and route it + // after an IOMMU translation if IOMMU activated. + // no VCI flit is consumed in this state + { + if ( p_vci_tgt_iox.cmdval.read() ) { if ( not r_iommu_active.read() ) // tlb not activated { + // save paddr address + r_dma_cmd_paddr = p_vci_tgt_iox.address.read(); + + // analyse paddr for WTI/DMA routing + // WTI requests must be single flit (READ or WRITE) + if ( is_wti( p_vci_tgt_iox.address.read() ) ) + { + assert( p_vci_tgt_iox.eop.read() and + "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); + + r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ; + } + else + { + r_dma_cmd_fsm = DMA_CMD_DMA_REQ; + } + #if DEBUG_DMA_CMD if( m_debug_activated ) -std::cout << " @@@ dma command" << std::endl - << " address = " << std::hex << p_vci_tgt_iox.address.read() +std::cout << " DMA command" << std::endl + << " : address = " << std::hex << p_vci_tgt_iox.address.read() << " / srcid = " << p_vci_tgt_iox.srcid.read() - << " / trdid = " << p_vci_tgt_iox.trdid.read() << " / wdata = " << std::hex << p_vci_tgt_iox.wdata.read() - << " / be = " << p_vci_tgt_iox.be.read() << " / plen = " << std::dec << p_vci_tgt_iox.plen.read() << " / eop = " << p_vci_tgt_iox.eop.read() << std::endl; - -#endif - // put DMA transaction into DMA_CMD fifo - r_dma_cmd_paddr = p_vci_tgt_iox.address.read(); - r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_CMD; +#endif } else if (r_tlb_fsm.read() == TLB_IDLE || @@ -581,9 +670,16 @@ (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) { - // put DMA response error into DMA_RSP fifo + // register error r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; r_iommu_bvar = p_vci_tgt_iox.address.read(); r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); - r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; + + // prepare response error request to DMA_RSP FSM + r_dma_cmd_to_dma_rsp_rsrcid = p_vci_tgt_iox.srcid.read(); + r_dma_cmd_to_dma_rsp_rtrdid = p_vci_tgt_iox.trdid.read(); + r_dma_cmd_to_dma_rsp_rpktid = p_vci_tgt_iox.pktid.read(); + + // jumps IOMMU error sequence + r_dma_cmd_fsm = DMA_CMD_ERR_WAIT_EOP; #if DEBUG_DMA_CMD if( m_debug_activated ) @@ -597,7 +693,20 @@ std::cout << " TLB HIT" << std::endl; #endif - // put DMA transaction into DMA_CMD fifo - r_dma_cmd_paddr = iotlb_paddr; - r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_CMD; + // save paddr address + r_dma_cmd_paddr = iotlb_paddr; + + // analyse address for WTI/DMA routing + if ( is_wti( iotlb_paddr ) ) + { + assert( p_vci_tgt_iox.eop.read() and + (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and + "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); + + r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ; + } + else + { + r_dma_cmd_fsm = DMA_CMD_DMA_REQ; + } } } @@ -608,20 +717,22 @@ m_cpt_iotlb_miss++; #endif - // register virtual address, and send request to TLB FSM - r_dma_cmd_vaddr = p_vci_tgt_iox.address.read(); - r_dma_tlb_req = true; - r_dma_cmd_fsm = DMA_CMD_MISS_WAIT; + // register virtual address, and send request to TLB FSM + r_dma_cmd_to_tlb_vaddr = p_vci_tgt_iox.address.read(); + r_dma_cmd_to_tlb_req = true; + r_dma_cmd_fsm = DMA_CMD_TLB_MISS_WAIT; #if DEBUG_DMA_CMD if( m_debug_activated ) std::cout << " TLB MISS" << std::endl; #endif - } // end !hit + } // end tlb miss } // end if tlb_activated } // end if cmdval break; } - ////////////////////////// - case DMA_CMD_FIFO_PUT_CMD: // put a DMA transaction in DMA_CMD fifo - // if contig, VCI address must be incremented + ///////////////////// + case DMA_CMD_DMA_REQ: // put a flit in DMA_CMD FIFO + // if contig, VCI address must be incremented + // after initial translation by IOMMU. + // flit is consumed if DMA_CMD FIFO not full { if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) @@ -639,55 +750,103 @@ << " address = " << std::hex << r_dma_cmd_paddr.read() << " srcid = " << p_vci_tgt_iox.srcid.read() - << " trdid = " << p_vci_tgt_iox.trdid.read() << " wdata = " << p_vci_tgt_iox.wdata.read() - << " be = " << p_vci_tgt_iox.be.read() - << " contig = " << p_vci_tgt_iox.contig.read() - << " eop = " << std::dec << p_vci_tgt_iox.eop.read() - << " plen = " << std::dec << p_vci_tgt_iox.plen.read() << std::endl; + << " plen = " << std::dec << p_vci_tgt_iox.plen.read() + << " eop = " << std::dec << p_vci_tgt_iox.eop.read() << std::endl; #endif } break; } - ////////////////////// - case DMA_CMD_WAIT_EOP: // An error has been detected on the VCI DMA command - // consume the VCI packet before sending the error response - { - if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; - break; - } - ////////////////////////// - case DMA_CMD_FIFO_PUT_RSP: // try to put a response error in DMA_RSP fifo - // The FIFO is shared with DMA_RSP FSM - // and we must we wait for allocation... - { - if ( r_alloc_fifo_dma_rsp_local.read() ) + ///////////////////////// + case DMA_CMD_WTI_IOX_REQ: // post a WTI_IOX request to MISS_WTI FSM + // if no prending previous request + // command arguments are stored in dedicated registers + // VCI flit is consumed if no previous request + { + if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no previous pending request { - dma_rsp_fifo_put = true; - - if( m_dma_rsp_data_fifo.wok() ) - { - + r_dma_cmd_to_miss_wti_cmd_req = true; + r_dma_cmd_to_miss_wti_cmd_addr = p_vci_tgt_iox.address.read(); + r_dma_cmd_to_miss_wti_cmd_cmd = p_vci_tgt_iox.cmd.read(); + r_dma_cmd_to_miss_wti_cmd_wdata = (uint32_t)p_vci_tgt_iox.wdata.read(); + r_dma_cmd_to_miss_wti_cmd_srcid = p_vci_tgt_iox.srcid.read(); + r_dma_cmd_to_miss_wti_cmd_trdid = p_vci_tgt_iox.trdid.read(); + r_dma_cmd_to_miss_wti_cmd_pktid = PKTID_WTI_IOX; + + r_dma_cmd_fsm = DMA_CMD_IDLE; + #if DEBUG_DMA_CMD if( m_debug_activated ) -std::cout << " Put a response error to a DMA transaction." - << std::endl; -#endif - r_dma_cmd_fsm = DMA_CMD_IDLE; - } +std::cout << " request WTI transaction from ext peripheral" + << " : address = " << std::hex << r_dma_cmd_paddr.read() + << " / srcid = " << p_vci_tgt_iox.srcid.read() + << " / wdata = " << p_vci_tgt_iox.wdata.read() << std::endl; +#endif } break; } - /////////////////////// - case DMA_CMD_MISS_WAIT: // waiting completion of a TLB miss - // we must test a possible page fault error... - { - if ( not r_dma_tlb_req.read() ) // TLB miss completed + ////////////////////////// + case DMA_CMD_ERR_WAIT_EOP: // wait EOP before requesting WTI & error response + // VCI flit is always consumed + { + if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_ERR_WTI_REQ; + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << " wait EOP for faulty DMA command" << std::endl; +#endif + break; + } + + ///////////////////////// + case DMA_CMD_ERR_WTI_REQ: // post a WTI_MMU request to MISS_WTI_CMD FSM + // if no prending previous request + // response arguments are stored in dedicated registers + // no VCI flit is consumed + { + if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no pending previous request + { + r_dma_cmd_to_miss_wti_cmd_req = true; + r_dma_cmd_to_miss_wti_cmd_addr = (vci_addr_t)r_iommu_wti_addr_lo.read() | + (((vci_addr_t)r_iommu_wti_addr_hi.read())<<32); + r_dma_cmd_to_miss_wti_cmd_wdata = 0; + r_dma_cmd_to_miss_wti_cmd_srcid = m_int_srcid; + r_dma_cmd_to_miss_wti_cmd_trdid = 0; + r_dma_cmd_to_miss_wti_cmd_pktid = PKTID_WTI_MMU; + + r_dma_cmd_fsm = DMA_CMD_ERR_RSP_REQ; + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << " request an IOMMU WTI" << std::endl; +#endif + } + break; + } + ///////////////////////// + case DMA_CMD_ERR_RSP_REQ: // post an error response request to DMA_RSP FSM + // if no prending previous request + // response arguments are stored in dedicated registers + // no VCI flit is consumed + { + if ( not r_dma_cmd_to_dma_rsp_req.read() ) // no pending previous request + { + r_dma_cmd_to_dma_rsp_req = true; + r_dma_cmd_to_dma_rsp_rerror = 0x1; + r_dma_cmd_to_dma_rsp_rdata = 0; + } + break; + } + /////////////////////////// + case DMA_CMD_TLB_MISS_WAIT: // waiting completion of a TLB miss + // we must test a possible page fault error... + { + if ( not r_dma_cmd_to_tlb_req.read() ) // TLB miss completed { if ( r_tlb_miss_error.read() ) // Error reported by TLB FSM { r_iommu_etr = MMU_READ_PT2_UNMAPPED; - r_iommu_bvar = r_dma_cmd_vaddr.read(); + r_iommu_bvar = r_dma_cmd_to_tlb_vaddr.read(); r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); - r_dma_cmd_fsm = DMA_CMD_FIFO_PUT_RSP; + r_dma_cmd_fsm = DMA_CMD_ERR_WAIT_EOP; } else // No error @@ -700,44 +859,133 @@ } // end switch DMA_CMD FSM - ////////////////////////////////////////////////////////////////////////////// - // The DMA_RSP_FSM handles the RAM responses to peripherals DMA transactions. - ////////////////////////////////////////////////////////////////////////////// - - switch( r_dma_rsp_fsm.read() ) - { - ////////////////// - case DMA_RSP_IDLE: // waiting a response from RAM betwork - { - if ( p_vci_ini_ram.rspval.read() ) - { - r_dma_rsp_fsm = DMA_RSP_FIFO_PUT; - } - break; - } - ////////////////////// - case DMA_RSP_FIFO_PUT: - { - if(p_vci_ini_ram.rspval.read() and not r_alloc_fifo_dma_rsp_local.read() ) - { - dma_rsp_fifo_put = true; - - if(p_vci_ini_ram.reop.read()) r_dma_rsp_fsm = DMA_RSP_IDLE; + //////////////////////////////////////////////////////////////////////////////// + // The DMA_RSP_FSM controls access to the DMA_RSP FIFO to the IOX network. + // There exist 3 "clients" to send VCI responses on the IOX network: + // - request from p_vci_ini_ram : normal DMA response from RAM network, + // - request from MISS_WTI_RSP FSM : normal WTI response from INT network, + // - request from DMA_CMD FSM : bad address error response + // This FSM implements a round robin priority, with a "dead cycle" between + // two transactions. It could be optimized if throughput is critical... + //////////////////////////////////////////////////////////////////////////////// + + // does nothing if FIFO is full + if ( m_dma_rsp_rerror_fifo.wok() ) + { + switch( r_dma_rsp_fsm.read() ) + { + ////////////////////// + case DMA_RSP_IDLE_DMA: // normal DMA response has highest priority + { + if (p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + else if(r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; + break; + } + ////////////////////// + case DMA_RSP_IDLE_WTI: // normal WTI response has highest priority + { + if (r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + else if(r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; + else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + break; + } + ////////////////////// + case DMA_RSP_IDLE_ERR: // error response has highest priority + { + if (r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; + else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + break; + } + /////////////////////// + case DMA_RSP_PUT_DMA: // put one flit of the DMA response into FIFO + { + dma_rsp_fifo_put = true; + dma_rsp_fifo_rerror = p_vci_ini_ram.rerror.read(); + dma_rsp_fifo_rdata = p_vci_ini_ram.rdata.read(); + dma_rsp_fifo_rsrcid = p_vci_ini_ram.rsrcid.read(); + dma_rsp_fifo_rtrdid = p_vci_ini_ram.rtrdid.read(); + dma_rsp_fifo_rpktid = p_vci_ini_ram.rpktid.read(); + dma_rsp_fifo_reop = p_vci_ini_ram.reop.read(); + + // update priority + if ( p_vci_ini_ram.reop.read() ) r_dma_rsp_fsm = DMA_RSP_IDLE_WTI; #if DEBUG_DMA_RSP if( m_debug_activated ) -std::cout << " Push response into DMA_RSP fifo:" - << " / rsrcid = " << std::hex << p_vci_ini_ram.rsrcid.read() +std::cout << " Push DMA response into DMA_RSP FIFO" + << " : rsrcid = " << std::hex << p_vci_ini_ram.rsrcid.read() << " / rtrdid = " << p_vci_ini_ram.rtrdid.read() - << " / rdata = " << std::hex << p_vci_ini_ram.rdata.read() + << " / rpktid = " << p_vci_ini_ram.rpktid.read() + << " / rdata = " << p_vci_ini_ram.rdata.read() << " / rerror = " << p_vci_ini_ram.rerror.read() - << " / reop = " << p_vci_ini_ram.reop.read() << std::endl; -#endif - } - break; - } - } // end switch DMA_RSP_FSM + << " / reop = " << p_vci_ini_ram.reop.read() << std::endl; +#endif + break; + } + /////////////////////// + case DMA_RSP_PUT_WTI: // put single flit WTI response into FIFO + { + dma_rsp_fifo_put = true; + dma_rsp_fifo_rerror = r_miss_wti_rsp_to_dma_rsp_rerror.read(); + dma_rsp_fifo_rdata = 0; + dma_rsp_fifo_rsrcid = r_miss_wti_rsp_to_dma_rsp_rsrcid.read(); + dma_rsp_fifo_rtrdid = r_miss_wti_rsp_to_dma_rsp_rtrdid.read(); + dma_rsp_fifo_rpktid = r_miss_wti_rsp_to_dma_rsp_rpktid.read(); + dma_rsp_fifo_reop = true; + + // acknowledge request + r_miss_wti_rsp_to_dma_rsp_req = false; + + // update priority + r_dma_rsp_fsm = DMA_RSP_IDLE_ERR; + +#if DEBUG_DMA_RSP +if( m_debug_activated ) +std::cout << " Push WTI response into DMA_RSP FIFO" + << " : rsrcid = " << std::hex << r_miss_wti_rsp_to_dma_rsp_rsrcid.read() + << " / rtrdid = " << r_miss_wti_rsp_to_dma_rsp_rtrdid.read() + << " / rpktid = " << r_miss_wti_rsp_to_dma_rsp_rpktid.read() + << " / rdata = " << 0 + << " / rerror = " << r_miss_wti_rsp_to_dma_rsp_rerror.read() + << " / reop = " << true << std::endl; +#endif + break; + } + /////////////////////// + case DMA_RSP_PUT_ERR: // put sinfle flit error response into FIFO + { + dma_rsp_fifo_put = true; + dma_rsp_fifo_rerror = 0x1; + dma_rsp_fifo_rdata = 0; + dma_rsp_fifo_rsrcid = r_dma_cmd_to_dma_rsp_rsrcid.read(); + dma_rsp_fifo_rtrdid = r_dma_cmd_to_dma_rsp_rtrdid.read(); + dma_rsp_fifo_rpktid = r_dma_cmd_to_dma_rsp_rpktid.read(); + dma_rsp_fifo_reop = true; + + // acknowledge request + r_dma_cmd_to_dma_rsp_req = false; + + // update priority + r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + +#if DEBUG_DMA_RSP +if( m_debug_activated ) +std::cout << " Push IOMMU ERROR response into DMA_RSP FIFO" + << " : rsrcid = " << std::hex << r_dma_cmd_to_dma_rsp_rsrcid.read() + << " / rtrdid = " << r_dma_cmd_to_dma_rsp_rtrdid.read() + << " / rpktid = " << r_dma_cmd_to_dma_rsp_rpktid.read() + << " / rdata = " << 0 + << " / rerror = " << r_dma_cmd_to_dma_rsp_rerror.read() + << " / reop = " << true << std::endl; +#endif + break; + } + } // end switch DMA_RSP FSM + } // end if FIFO full + ////////////////////////////////////////////////////////////////////////////////// - // The TLB FSM handles TLB miss request (from DMA_CMD FSM), + // The TLB FSM handles the TLB miss requests from DMA_CMD FSM, // and the PTE inval request (from CONFIG_CMD FSM). // PTE inval request have highest priority. In case of TLB miss, @@ -745,5 +993,5 @@ // In case of buffer miss, it request the MISS_WTI FSM to access the memory. // It bypass the first level page table access if possible. - // It reset the r_dma_tlb_req flip-flop to signal TLB miss completion. + // It reset the r_dma_cmd_to_tlb_req flip-flop to signal TLB miss completion. // An unexpected, but possible page fault is signaled in r_tlb_miss_error flip_flop. //////////////////////////////////////////////////////////////////////////////////// @@ -755,12 +1003,12 @@ // PTE inval request are handled as unmaskable interrupts { - if ( r_config_tlb_req ) // Request from CONFIG FSM for a PTE invalidation + if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation { - r_config_tlb_req = false; - r_waiting_transaction = false; - r_tlb_fsm = TLB_INVAL_CHECK; + r_config_cmd_to_tlb_req = false; + r_waiting_transaction = false; + r_tlb_fsm = TLB_INVAL_CHECK; } - else if ( r_dma_tlb_req.read() ) // request from DMA_CMD for a TLB Miss + else if ( r_dma_cmd_to_tlb_req.read() ) // request for a TLB Miss { // Checking prefetch buffer @@ -769,7 +1017,7 @@ if( r_tlb_buf_valid && // Hit on prefetch buffer (r_tlb_buf_vaddr.read() == - (r_dma_cmd_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) - { - size_t pte_offset = (r_dma_cmd_vaddr.read()& PTE2_LINE_OFFSET)>>12; + (r_dma_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) + { + size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; uint32_t pte_flags = r_tlb_buf_data[2*pte_offset]; uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; @@ -782,5 +1030,5 @@ r_tlb_miss_error = true; - r_dma_tlb_req = false; + r_dma_cmd_to_tlb_req = false; #if DEBUG_TLB_MISS if ( m_debug_activated ) @@ -810,7 +1058,7 @@ if( r_tlb_buf_valid && // Hit on prefetch buffer (r_tlb_buf_vaddr.read() == - (r_dma_cmd_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) - { - size_t pte_offset = (r_dma_cmd_vaddr.read()& PTE1_LINE_OFFSET)>>21; + (r_dma_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) + { + size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; uint32_t pte_flags = r_tlb_buf_data[pte_offset]; @@ -822,5 +1070,5 @@ r_tlb_miss_error = true; - r_dma_tlb_req = false; + r_dma_cmd_to_tlb_req = false; #if DEBUG_TLB_MISS if ( m_debug_activated ) @@ -851,5 +1099,5 @@ if ( m_debug_activated ) std::cout << " Miss on prefetch buffer" - << std::hex << " / vaddr = " << r_dma_cmd_vaddr.read() << std::endl; + << std::hex << " / vaddr = " << r_dma_cmd_to_tlb_vaddr.read() << std::endl; #endif } @@ -867,5 +1115,5 @@ #endif // evaluate bypass in order to skip first level page table access - bypass = r_iotlb.get_bypass(r_dma_cmd_vaddr.read(), &ptba); + bypass = r_iotlb.get_bypass(r_dma_cmd_to_tlb_vaddr.read(), &ptba); // Request MISS_WTI_FSM a transaction on INT Network @@ -878,10 +1126,10 @@ #endif pte_paddr = (vci_addr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) | - (vci_addr_t)((r_dma_cmd_vaddr.read() >> PAGE_M_NBITS) << 2); + (vci_addr_t)((r_dma_cmd_to_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); r_tlb_paddr = pte_paddr; - r_tlb_miss_req = true; - r_tlb_miss_type = PTE1_MISS; - r_tlb_fsm = TLB_WAIT; + r_tlb_to_miss_wti_cmd_req = true; + r_tlb_miss_type = PTE1_MISS; + r_tlb_fsm = TLB_WAIT; } else // Read PTE2 in XRAM @@ -894,11 +1142,11 @@ //&PTE2 = PTBA + IX2 * 8 pte_paddr = (vci_addr_t)ptba << PAGE_K_NBITS | - (vci_addr_t)(r_dma_cmd_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); + (vci_addr_t)(r_dma_cmd_to_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); r_tlb_paddr = pte_paddr; - r_tlb_miss_req = true; - r_tlb_miss_type = PTE2_MISS; - r_tlb_fsm = TLB_WAIT; + r_tlb_to_miss_wti_cmd_req = true; + r_tlb_miss_type = PTE2_MISS; + r_tlb_fsm = TLB_WAIT; } @@ -929,6 +1177,6 @@ r_tlb_miss_error = true; - r_dma_tlb_req = false; - r_tlb_fsm = TLB_IDLE; + r_dma_cmd_to_tlb_req = false; + r_tlb_fsm = TLB_IDLE; #if DEBUG_TLB_MISS @@ -946,15 +1194,16 @@ { // register bypass - r_iotlb.set_bypass( r_dma_cmd_vaddr.read(), + r_iotlb.set_bypass( r_dma_cmd_to_tlb_vaddr.read(), entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), 0); //nline, unused - //&PTE2 = PTBA + IX2 * 8 + // &PTE2 = PTBA + IX2 * 8 // ps: PAGE_K_NBITS corresponds also to the size of a second level page table r_tlb_paddr = (vci_addr_t)(entry & ((1<<(vci_param_int::N-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | - (vci_addr_t)(((r_dma_cmd_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); - r_tlb_miss_req = true; - r_tlb_miss_type = PTE2_MISS; - r_tlb_fsm = TLB_WAIT; + (vci_addr_t)(((r_dma_cmd_to_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); + + r_tlb_to_miss_wti_cmd_req = true; + r_tlb_miss_type = PTE2_MISS; + r_tlb_fsm = TLB_WAIT; #ifdef INSTRUMENTATION @@ -990,5 +1239,5 @@ size_t set; - r_iotlb.select( r_dma_cmd_vaddr.read(), + r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), true, // PTE1 &way, @@ -1016,5 +1265,5 @@ r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_flags.read() & PPN1_MASK) << 21) - | (r_dma_cmd_vaddr.read()& M_PAGE_OFFSET_MASK) ); + | (r_dma_cmd_to_tlb_vaddr.read()& M_PAGE_OFFSET_MASK) ); // update TLB @@ -1022,8 +1271,9 @@ pte, 0, // argument unused for a PTE1 - r_dma_cmd_vaddr.read(), + r_dma_cmd_to_tlb_vaddr.read(), r_tlb_way.read(), r_tlb_set.read(), 0 ); //we set nline = 0 + #ifdef INSTRUMENTATION m_cpt_iotlb_write++; @@ -1066,5 +1316,5 @@ r_tlb_miss_error = true; - r_dma_tlb_req = false; + r_dma_cmd_to_tlb_req = false; r_tlb_fsm = TLB_IDLE; @@ -1096,5 +1346,5 @@ size_t set; - r_iotlb.select( r_dma_cmd_vaddr.read(), + r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), false, // PTE2 &way, @@ -1106,9 +1356,7 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -{ - std::cout << " Select a slot in IOTLB:"; - std::cout << " way = " << std::dec << way - << " / set = " << set << std::endl; -} +std::cout << " Select a slot in IOTLB:" + << " way = " << std::dec << way + << " / set = " << set << std::endl; #endif r_tlb_way = way; @@ -1125,5 +1373,5 @@ r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_ppn.read() & PPN2_MASK) << 12) - | (r_dma_cmd_vaddr.read()& K_PAGE_OFFSET_MASK) ); + | (r_dma_cmd_to_tlb_vaddr.read()& K_PAGE_OFFSET_MASK) ); // update TLB for a PTE2 @@ -1131,5 +1379,5 @@ pte_flags, pte_ppn, - r_dma_cmd_vaddr.read(), + r_dma_cmd_to_tlb_vaddr.read(), r_tlb_way.read(), r_tlb_set.read(), @@ -1142,8 +1390,8 @@ if ( m_debug_activated ) { - std::cout << " write PTE2 in IOTLB"; - std::cout << " / set = " << std::dec << r_tlb_set.read() - << " / way = " << r_tlb_way.read() << std::endl; - r_iotlb.printTrace(); +std::cout << " write PTE2 in IOTLB" + << " / set = " << std::dec << r_tlb_set.read() + << " / way = " << r_tlb_way.read() << std::endl; +r_iotlb.printTrace(); } #endif @@ -1156,9 +1404,9 @@ // PTE inval request are handled as unmaskable interrupts { - if ( r_config_tlb_req ) // Request from CONFIG FSM for a PTE invalidation + if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation { - r_config_tlb_req = false; - r_waiting_transaction = true; - r_tlb_fsm = TLB_INVAL_CHECK; + r_config_cmd_to_tlb_req = false; + r_waiting_transaction = true; + r_tlb_fsm = TLB_INVAL_CHECK; } @@ -1166,12 +1414,12 @@ m_cost_iotlbmiss_transaction++; #endif - if ( not r_tlb_miss_req ) // Miss transaction is done + if ( not r_tlb_to_miss_wti_cmd_req.read() ) // Miss transaction completed { - if ( r_miss_wti_rsp_error.read() ) // bus error + if ( r_miss_wti_rsp_error_miss.read() ) // bus error reported { - r_miss_wti_rsp_error = false; - r_tlb_miss_error = true; - r_dma_tlb_req = false; - r_tlb_fsm = TLB_IDLE; + r_miss_wti_rsp_error_miss = false; + r_tlb_miss_error = true; + r_dma_cmd_to_tlb_req = false; + r_tlb_fsm = TLB_IDLE; } else if(r_tlb_miss_type == PTE1_MISS) @@ -1187,6 +1435,6 @@ } //////////////// - case TLB_RETURN: // reset r_dma_tlb_req flip-flop to signal TLB miss completion - // possible errors are signaled through r_tlb_miss_error + case TLB_RETURN: // reset r_dma_cmd_to_tlb_req to signal TLB miss completion + // possible errors are signaled through r_tlb_miss_error { #if DEBUG_TLB_MISS @@ -1194,5 +1442,5 @@ std::cout << " IOTLB MISS completed" << std::endl; #endif - r_dma_tlb_req = false; + r_dma_cmd_to_tlb_req = false; r_tlb_fsm = TLB_IDLE; break; @@ -1210,5 +1458,5 @@ { if( r_tlb_buf_vaddr.read() == - (r_config_cmd_inval_vaddr.read()& ~PTE2_LINE_OFFSET) ) + (r_config_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET) ) // The virtual address corresponds to one entry on the buffer line { @@ -1219,5 +1467,5 @@ { if( r_tlb_buf_vaddr.read() == - (r_config_cmd_inval_vaddr.read()& ~PTE1_LINE_OFFSET) ) + (r_config_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET) ) // The virtual address corresponds to one entry on the buffer line { @@ -1229,5 +1477,5 @@ // Invalidation on IOTLB bool ok; - ok = r_iotlb.inval(r_config_cmd_inval_vaddr.read()); + ok = r_iotlb.inval(r_config_cmd_to_tlb_vaddr.read()); if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; @@ -1239,13 +1487,14 @@ //////////////////////////////////////////////////////////////////////////////// // The CONFIG_CMD_FSM handles the VCI commands from the INT network. - // This FSM can handle single flit config transactions, but it can also handle - // software driven, multi-flits data transactions to ROM (read) or FBF (write). + // - it can be single flit config transactions + // - it can be multi-flits data transactions to ROM (read) or FBF (write). // The write burst transactions must be serialised from 32 to 64 bits width. // The configuration requests can be local (IO_BRIDGE config registers) // or remote (config registers of peripherals on IOX network). - // - The local configuration segment is identified by the "special" atribute. + // - The local configuration segment is identified by the "special" atribute + // in the mapping table. // - All configuration requests are checkeg against segmentation violation. // - In case of local config request, or in case of segmentation violation, - // the FSM put a VCI response request in CONFIG_RSP fifo. + // the FSM send a response request to CONFIG_RSP FSM. // - In case of remote transaction, it put the VCI command in CONFIG_CMD fifo, // and this require two cycles per IOX flit in case of write burst. @@ -1296,5 +1545,5 @@ assert( (p_vci_tgt_int.be.read() == 0xF) and - "ERROR in vci_io_bridge : BE != 0xF for a config access"); + "ERROR in vci_io_bridge : BE must be 0xF for a config access"); assert( ( eop ) and @@ -1307,5 +1556,5 @@ else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR { - r_config_cmd_rdata = r_iommu_ptpr.read(); + r_config_cmd_to_config_rsp_rdata = r_iommu_ptpr.read(); } else if( not read && (cell == IOB_WTI_ENABLE)) // WRITE WTI_ENABLE @@ -1315,60 +1564,54 @@ else if( read && (cell == IOB_WTI_ENABLE)) // READ WTI ENABLE { - r_config_cmd_rdata = r_iommu_wti_enable.read(); + r_config_cmd_to_config_rsp_rdata = r_iommu_wti_enable.read(); } else if( read && (cell == IOB_IOMMU_BVAR)) // READ BVAR { - r_config_cmd_rdata = r_iommu_bvar.read(); + r_config_cmd_to_config_rsp_rdata = r_iommu_bvar.read(); } else if( read && (cell == IOB_IOMMU_ETR)) // READ ETR { - r_config_cmd_rdata = r_iommu_etr.read(); + r_config_cmd_to_config_rsp_rdata = r_iommu_etr.read(); } else if( read && (cell == IOB_IOMMU_BAD_ID)) // READ BAD_ID { - r_config_cmd_rdata = r_iommu_bad_id.read(); + r_config_cmd_to_config_rsp_rdata = r_iommu_bad_id.read(); } else if( not read && (cell == IOB_INVAL_PTE)) // WRITE INVAL_PTE { - r_config_tlb_req = true; - r_config_cmd_inval_vaddr = (uint32_t)p_vci_tgt_int.wdata.read(); + r_config_cmd_to_tlb_req = true; + r_config_cmd_to_tlb_vaddr = (uint32_t)p_vci_tgt_int.wdata.read(); } else if( not read && (cell == IOB_WTI_ADDR_LO)) // WRITE WTI_PADDR_LO { - r_iommu_wti_paddr = (vci_addr_t)p_vci_tgt_int.wdata.read(); + r_iommu_wti_addr_lo = (vci_addr_t)p_vci_tgt_int.wdata.read(); } else if( read && (cell == IOB_WTI_ADDR_LO)) // READ WTI_PADDR_LO { - r_config_cmd_rdata = (uint32_t)r_iommu_wti_paddr.read(); + r_config_cmd_to_config_rsp_rdata = r_iommu_wti_addr_lo.read(); } else if( not read && (cell == IOB_WTI_ADDR_HI)) // WRITE WTI_PADDR_HI { - r_iommu_wti_paddr = (r_iommu_wti_paddr.read() & 0x00000000FFFFFFFFLL) | - ((vci_addr_t)p_vci_tgt_int.wdata.read())<<32; + r_iommu_wti_addr_hi = (vci_addr_t)p_vci_tgt_int.wdata.read(); } else if( read && (cell == IOB_WTI_ADDR_HI)) // READ WTI_PADDR_HI { - r_config_cmd_rdata = (uint32_t)(r_iommu_wti_paddr.read()>>32); - } - else if( not read && ((cell >= IOB_PERI_WTI_BEGIN) // WRITE PERI WTI - && (cell< (IOB_PERI_WTI_BEGIN + 64))) ) - { - size_t index = (cell - IOB_PERI_WTI_BEGIN)/2; - bool high = (cell - IOB_PERI_WTI_BEGIN)%2; - if ( high ) r_iommu_peri_wti[index] = // set 32 MSB bits - (r_iommu_peri_wti[index].read() & 0x00000000FFFFFFFFLL) | - ((vci_addr_t)p_vci_tgt_int.wdata.read())<<32; - else r_iommu_peri_wti[index] = // set 32 LSB bits - (vci_addr_t)p_vci_tgt_int.wdata.read(); - } - else if( read && ((cell >= IOB_PERI_WTI_BEGIN) // READ PERI WTI - && (cell< (IOB_PERI_WTI_BEGIN + 64))) ) - { - size_t index = (cell - IOB_PERI_WTI_BEGIN)/2; - bool high = (cell - IOB_PERI_WTI_BEGIN)%2; - if ( high ) r_config_cmd_rdata = - (uint32_t)(r_iommu_peri_wti[index].read()>>32); - else r_config_cmd_rdata = - (uint32_t)(r_iommu_peri_wti[index].read()); + r_config_cmd_to_config_rsp_rdata = r_iommu_wti_addr_hi.read(); + } + else if( not read && (cell == IOB_XICU_BASE)) // WRITE XICU_BASE + { + r_xicu_base = (vci_addr_t)p_vci_tgt_int.wdata.read(); + } + else if( read && (cell == IOB_XICU_BASE)) // READ XICU_BASE + { + r_config_cmd_to_config_rsp_rdata = r_xicu_base.read(); + } + else if( not read && (cell == IOB_XICU_SIZE)) // WRITE XICU_SIZE + { + r_xicu_size = (vci_addr_t)p_vci_tgt_int.wdata.read(); + } + else if( read && (cell == IOB_XICU_SIZE)) // READ XICU_SIZE + { + r_config_cmd_to_config_rsp_rdata = r_xicu_size.read(); } else // Error: Wrong address, or invalid operation. @@ -1376,6 +1619,6 @@ rerror = true; } - r_config_cmd_error = rerror; - r_config_cmd_fsm = CONFIG_CMD_RSP; + r_config_cmd_to_config_rsp_rerror = rerror; + r_config_cmd_fsm = CONFIG_CMD_RSP; } else if ( found ) // remote peripheral @@ -1431,7 +1674,7 @@ else // out of segment address { - r_config_cmd_rdata = 0; - r_config_cmd_error = true; - if( eop ) r_config_cmd_fsm = CONFIG_CMD_RSP; + r_config_cmd_to_config_rsp_rdata = 0; + r_config_cmd_to_config_rsp_rerror = true; + if( eop ) r_config_cmd_fsm = CONFIG_CMD_RSP; } } // end if cmdval @@ -1460,5 +1703,5 @@ } //////////////////// - case CONFIG_CMD_PUT: // try to post a command to CONFIG_CMD fifo (to IOX network) + case CONFIG_CMD_PUT: // post a command to CONFIG_CMD fifo (to IOX network) { config_cmd_fifo_put = true; @@ -1480,23 +1723,19 @@ } //////////////////// - case CONFIG_CMD_RSP: // Try to put a response in CONFIG_RSP fifo, for - // a local configuration transaction or a segment error. - // The FIFO is shared with CONFIG_RSP FSM - // and must we wait for allocation... - { - if ( r_alloc_fifo_config_rsp_local.read() ) + case CONFIG_CMD_RSP: // Post a request to CONFIG_RSP FSM, + // if no previous pending request. + // r_config_cmd_to_config_rsp_rerror + // has been set in IDLE state. + { + if ( not r_config_cmd_to_config_rsp_req.read() ) { - config_rsp_fifo_put = true; - - if ( m_config_rsp_data_fifo.wok() ) - { + r_config_cmd_to_config_rsp_req = true; #if DEBUG_CONFIG_CMD if( m_debug_activated ) -std::cout << " Response to a local configuration request" - << std::endl; -#endif - r_config_cmd_fsm = CONFIG_CMD_IDLE; - } +std::cout << " Request a response to CONFIG_RSP FSM" + << " / error = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; +#endif + r_config_cmd_fsm = CONFIG_CMD_IDLE; } break; @@ -1505,8 +1744,11 @@ ////////////////////////////////////////////////////////////////////////////// - // The CONFIG_RSP_FSM handles the 64 bits VCI responses from the periherals - // on the IOX network and writes the responses in the CONFIG_RSP fifo. - // This FSM handle both single flit config responses, and multi-flits - // read responses (ROM), where data must be serialised (64 bits -> 32 bits). + // The CONFIG_RSP_FSM controls access to the CONFIG_RSP FIFO to INT network. + // It implements a round robin priority between 2 clients FSMs : + // - CONFIG_CMD : response to a local config command. + // - CONFIG_RSP : responses from peripherals on IOX network + // Regarding the responses from IOX network it handles both single flit + // config responses, and multi-flits read responses (ROM), where data must + // be serialised (64 bits -> 32 bits). // Note: We use the VCI RPKTID field to distinguish between read cached // (multi-flits response) and others (single flit response). @@ -1514,37 +1756,68 @@ ////////////////////////////////////////////////////////////////////////////// - switch( r_config_rsp_fsm.read() ) - { - ///////////////////// - case CONFIG_RSP_IDLE: // waiting a VCI response from IOX network - // flit on IOX network is not consumed - { - if ( p_vci_ini_iox.rspval.read() ) - { - if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits response + // does nothing if FIFO full + if ( m_config_rsp_rerror_fifo.wok() ) + { + switch( r_config_rsp_fsm.read() ) + { + ///////////////////////// + case CONFIG_RSP_IDLE_IOX: // IOX requests have highest priority + // no flit on IOX network is consumed + { + if ( p_vci_ini_iox.rspval.read() ) // IOX request + { + if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LOW; + } + else // single flit + { + r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; + } + } + else if ( r_config_cmd_to_config_rsp_req.read() ) // LOC request + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; + } + break; + } + ///////////////////////// + case CONFIG_RSP_IDLE_LOC: // LOC requests have highest priority + // no flit on IOX network is consumed + { + if ( r_config_cmd_to_config_rsp_req.read() ) // LOC request + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; + } + else if ( p_vci_ini_iox.rspval.read() ) // IOX request + { + if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LOW; + } + else // single flit + { + r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; + } + } + break; + } + //////////////////////// + case CONFIG_RSP_PUT_LOW: // put 32 low bits into CONFIG_RSP fifo + // no flit on IOX network is consumed { - r_config_rsp_fsm = CONFIG_RSP_PUT_LO; - } - else // single flit response - { - r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; - - assert( p_vci_ini_iox.reop.read() and - "ERROR in vci_io_bridge : a remote config response should be one flit"); - } - } - break; - } - /////////////////////// - case CONFIG_RSP_PUT_LO: // try to write 32 low bits into CONFIG_RSP fifo - // flit on IOX network is not consumed - { - if ( not r_alloc_fifo_config_rsp_local.read() and m_config_rsp_data_fifo.wok() ) - { - r_config_rsp_fsm = CONFIG_RSP_PUT_HI; + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); + config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); + config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read(); + config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read(); + config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); + config_rsp_fifo_reop = false; + + r_config_rsp_fsm = CONFIG_RSP_PUT_HI; #if DEBUG_CONFIG_RSP if( m_debug_activated ) -std::cout << " Push multi-flit response into CONFIG_RSP fifo:" +std::cout << " Push multi-flit response into CONFIG_RSP FIFO" << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() @@ -1554,40 +1827,54 @@ << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; #endif - } - break; - } - /////////////////////// - case CONFIG_RSP_PUT_HI: // try to write 32 high bits into CONFIG_RSP fifo - // flit on IOX network is consumed if success - { - if ( not r_alloc_fifo_config_rsp_local.read() and m_config_rsp_data_fifo.wok() ) - { - if( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE; - else r_config_rsp_fsm = CONFIG_RSP_PUT_LO; + break; + } + /////////////////////// + case CONFIG_RSP_PUT_HI: // put 32 high bits into CONFIG_RSP fifo + // flit on IOX network is consumed + { + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); + config_rsp_fifo_rdata = (uint32_t)(p_vci_ini_iox.rdata.read() >> 32); + config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read(); + config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read(); + config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); + config_rsp_fifo_reop = p_vci_ini_iox.reop.read(); + + if( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE_LOC; + else r_config_rsp_fsm = CONFIG_RSP_PUT_LOW; #if DEBUG_CONFIG_RSP if( m_debug_activated ) -std::cout << " Push multi-flit response into CONFIG_RSP fifo:" +std::cout << " Push multi-flit response into CONFIG_RSP FIFO" << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() << " / rpktid = " << p_vci_ini_iox.rpktid.read() - << " / rdata = " << (uint32_t)(p_vci_ini_iox.rdata.read()>>32) + << " / rdata = " << (uint32_t)(p_vci_ini_iox.rdata.read() >> 32) << " / reop = " << p_vci_ini_iox.reop.read() << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; #endif - } - break; - } - //////////////////////// - case CONFIG_RSP_PUT_UNC: // try to write single flit into CONFIG_RSP fifo - // flit on IOX network is consumed if success - { - if ( not r_alloc_fifo_config_rsp_local.read() and m_config_rsp_data_fifo.wok() ) - { - r_config_rsp_fsm = CONFIG_RSP_IDLE; + break; + } + //////////////////////// + case CONFIG_RSP_PUT_UNC: // put single flit into CONFIG_RSP fifo + // flit on IOX network is consumed + { + assert( p_vci_ini_iox.reop.read() and + "ERROR in vci_io_bridge : a remote config response should be one flit"); + + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); + config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); + config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read(); + config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read(); + config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); + config_rsp_fifo_reop = true; + + // update priority + r_config_rsp_fsm = CONFIG_RSP_IDLE_LOC; #if DEBUG_CONFIG_RSP if( m_debug_activated ) -std::cout << " Push single flit response into CONFIG_RSP fifo:" +std::cout << " Push single flit response into CONFIG_RSP FIFO" << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() @@ -1597,146 +1884,188 @@ << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; #endif - } - break; - } - } // end switch CONFIG_RSP FSM - - ///////////////////////////////////////////////////////////////////////////////// - // If the IOB component has IRQ ports, the IRQ FSM detects all changes - // on the 32 p_irq[i] ports and request a VCI write transaction to the - // MISS_INIT FSM, using the 64 r_irq_request[i] and r_irq_pending[i] flip-flops. - ///////////////////////////////////////////////////////////////////////////////// - - if ( m_has_irqs ) - { - for ( size_t i = 0; i<32; ++i ) - { - r_irq_request[i] = ( p_irq[i]->read() == not r_irq_pending[i].read() ); - r_irq_pending[i] = p_irq[i]->read(); - } - } - + break; + } + //////////////////////// + case CONFIG_RSP_PUT_LOC: // put single flit into CONFIG_RSP fifo + // no flit on IOX network is consumed + { + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = r_config_cmd_to_config_rsp_rerror.read(); + config_rsp_fifo_rdata = r_config_cmd_to_config_rsp_rdata.read(); + config_rsp_fifo_rsrcid = r_config_cmd_srcid.read(); + config_rsp_fifo_rtrdid = r_config_cmd_trdid.read(); + config_rsp_fifo_rpktid = r_config_cmd_pktid.read(); + config_rsp_fifo_reop = true; + + // acknowledge request + r_config_cmd_to_config_rsp_req = false; + + // update priority + r_config_rsp_fsm = CONFIG_RSP_IDLE_IOX; + +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +std::cout << " Push single flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_cmd_srcid.read() + << " / rtrdid = " << r_config_cmd_trdid.read() + << " / rpktid = " << r_config_cmd_pktid.read() + << " / rdata = " << r_config_cmd_to_config_rsp_rdata.read() + << " / reop = " << true + << " / rerror = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; +#endif + break; + } + } // end switch CONFIG_RSP FSM + } // end if FIFO full + /////////////////////////////////////////////////////////////////////////////////// - // The MISS_WTI_CMD FSM send VCI commands on the Internal Network. - // It handles PTE MISS requests from TLB_MISS FSM and software IRQs. - // It supports several simultaneous VCI transactions. + // The MISS_WTI_CMD component is a combinational switch that push one single flit + // VCI command in the MISS_WTI FIFO to INT Network, depending on two clients : + // 1. MISS requests from TLB_MISS FSM : + // These requests have highest priority because a TLB MISS is a blocking event + // for the DMA FSM. The r_tlb_to_miss_wti_cmd_req flip-flop is reset by the + // MISS_WTI_RSP FSM only when the response is received. + // 2. WTI requests from DMA_CMD FSM : + // These requestsare non blocking events, and the r_dma_cmd_to_miss_wti_cmd_req + // flip-flop is reset as soon as the WTI command has been sent. + // There is two types of WTI requests: + // - external WTI from peripherals on IOX network. + // - internal WTI caused by illegal DMA requests. //////////////////////////////////////////////////////////////////////////////////// - switch ( r_miss_wti_cmd_fsm.read() ) + if ( r_tlb_to_miss_wti_cmd_req.read() and + m_miss_wti_cmd_addr_fifo.wok() ) // put MISS READ + { + miss_wti_cmd_fifo_put = true; + miss_wti_cmd_fifo_address = r_tlb_paddr.read(); + miss_wti_cmd_fifo_wdata = 0; + miss_wti_cmd_fifo_cmd = vci_param_int::CMD_READ; + miss_wti_cmd_fifo_pktid = PKTID_MISS; + miss_wti_cmd_fifo_srcid = m_int_srcid; + miss_wti_cmd_fifo_trdid = 0; + +#if DEBUG_MISS_WTI_CMD +if( m_debug_activated ) +std::cout << " push MISS TLB command into MISS_WTI FIFO" + << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; +#endif + + } + else if ( r_dma_cmd_to_miss_wti_cmd_req.read() and + m_miss_wti_cmd_addr_fifo.wok() ) // put WTI READ / WRITE + { + r_dma_cmd_to_miss_wti_cmd_req = false; + + miss_wti_cmd_fifo_put = true; + miss_wti_cmd_fifo_cmd = r_dma_cmd_to_miss_wti_cmd_cmd.read(); + miss_wti_cmd_fifo_address = r_dma_cmd_to_miss_wti_cmd_addr.read(); + miss_wti_cmd_fifo_wdata = r_dma_cmd_to_miss_wti_cmd_wdata.read(); + miss_wti_cmd_fifo_srcid = r_dma_cmd_to_miss_wti_cmd_srcid.read(); + miss_wti_cmd_fifo_trdid = r_dma_cmd_to_miss_wti_cmd_trdid.read(); + miss_wti_cmd_fifo_pktid = r_dma_cmd_to_miss_wti_cmd_pktid.read(); + +#if DEBUG_MISS_WTI_CMD +if( m_debug_activated ) +std::cout << " push WTI command into MISS_WTI FIFO" + << " / CMD = " << miss_wti_cmd_fifo_cmd + << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; +#endif + + } + + /////////////////////////////////////////////////////////////////////////////////// + // The MISS_WTI_RSP FSM handles VCI responses from the INT network: + // - for a TLB MISS (multi-flits read transaction), the cache line + // is written in r_tlb_buf_data[], and r_tlb_to_miss_wti_cmd_req flip-flop is reset. + // - for a WTI_IOX (single flit write transaction), the response must be + // forwarded to the source peripheral on the INT network + // - for a WTI_MMU (single flit write transaction), there is nothing to do. + // + // TODO VCI addressing errors for TLB MISS or for WTI_MMU (i.e. kernel errors...) + // are registered in the r_miss_wti_rsp_error_miss & r_miss_wti_rsp_error_wti + // flip-flops, and simulation stops... They could be signaled to OS by a WTI. + //////////////////////////////////////////////////////////////////////////////////// + + switch ( r_miss_wti_rsp_fsm.read() ) { /////////////////////// - case MISS_WTI_CMD_IDLE: // TLB MISS have highest priority + case MISS_WTI_RSP_IDLE: // waiting a VCI response + // no VCI flit is consumed { - if ( r_tlb_miss_req.read() ) + if ( p_vci_ini_int.rspval.read() ) { - r_miss_wti_cmd_fsm = MISS_WTI_CMD_MISS; - } - else if ( r_iommu_wti_enable.read() ) + if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_IOX ) + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_IOX; + } + else if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_MMU ) + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_MMU; + } + else if ( p_vci_ini_int.rpktid.read() == PKTID_MISS ) + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_MISS; + r_miss_wti_rsp_count = 0; + } + else + { + assert ( false and + "VCI_IO_BRIDGE ERROR : illegal response type on INT network"); + } + } + break; + } + ////////////////////////// + case MISS_WTI_RSP_WTI_IOX: // Handling response to a peripheral WTI + // consume VCI flit and transfer response + // to DMA_RSP FSM in dedicated registers + // if no pending previous request. + { + assert( p_vci_ini_int.reop.read() and + "VCI_IO_BRIDGE ERROR: WTI_IOX response should have one single flit" ); + + if ( not r_miss_wti_rsp_to_dma_rsp_req.read() ) // no previous pending request { - // checking if there is a new pending interrupt - bool found = false; - size_t n; - for ( n = 0 ; (n < 32) and not found ; n++ ) - { - if ( r_irq_request[n] ) found = true; - } - if ( found ) - { - r_miss_wti_cmd_index = n; - r_miss_wti_cmd_fsm = MISS_WTI_CMD_WTI; - } - } - break; + r_miss_wti_rsp_to_dma_rsp_req = true; + r_miss_wti_rsp_to_dma_rsp_rerror = p_vci_ini_int.rerror.read(); + r_miss_wti_rsp_to_dma_rsp_rsrcid = p_vci_ini_int.rsrcid.read(); + r_miss_wti_rsp_to_dma_rsp_rtrdid = p_vci_ini_int.rtrdid.read(); + r_miss_wti_rsp_to_dma_rsp_rpktid = p_vci_ini_int.rpktid.read(); + + r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; + +#if DEBUG_MISS_WTI_RSP +if( m_debug_activated ) +std::cout << " Transfer response to a WTI_IOX" << std::endl; +#endif + } + break; } - ////////////////////// - case MISS_WTI_CMD_WTI: // send a single flit IRQ WRITE on INT Network - // address is defined by IRQ_VECTOR[r_miss_wti_index] - // data is defined by r_irq_pending[r_miss_wti_index] + ////////////////////////// + case MISS_WTI_RSP_WTI_MMU: // Handling response to an iommu WTI + // consume VCI flit and test VCI error. { - if ( p_vci_ini_int.cmdack ) + assert( p_vci_ini_int.reop.read() and + "VCI_IO_BRIDGE ERROR: WTI_MMU response should have one single flit" ); + + if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported { - // reset the request - r_irq_request[r_miss_wti_cmd_index.read()] = false; - r_miss_wti_cmd_fsm = MISS_WTI_RSP_WTI; - -#if DEBUG_MISS_WTI -if( m_debug_activated ) -std::cout << " Send WTI write command on Internal Network" - << " / IRQID = " << std::dec << r_miss_wti_cmd_index.read() << std::endl; -#endif - } + // set the specific error flip-flop + r_miss_wti_rsp_error_wti = true; + assert( false and + "VCI_IO_BRIDGE ERROR: VCI error response for a WTI_MMU transaction"); + } + +#if DEBUG_MISS_WTI_RSP +if( m_debug_activated ) +std::cout << " Receive response to a WTI_MMU" << std::endl; +#endif break; } /////////////////////// - case MISS_WTI_CMD_MISS: // send a TLB MISS request on INT Network - { - if ( p_vci_ini_int.cmdack ) - { - r_tlb_buf_tag = ( (r_tlb_paddr.read()) & CACHE_LINE_MASK ); - r_tlb_buf_valid = true; - - if( r_tlb_miss_type.read() == PTE1_MISS ) - r_tlb_buf_vaddr = (r_dma_cmd_vaddr.read() & - ~M_PAGE_OFFSET_MASK & ~PTE1_LINE_OFFSET); - else - r_tlb_buf_vaddr = (r_dma_cmd_vaddr.read() & - ~K_PAGE_OFFSET_MASK & ~PTE2_LINE_OFFSET); - - r_miss_wti_cmd_fsm = MISS_WTI_RSP_MISS; - -#if DEBUG_MISS_WTI -if( m_debug_activated ) -std::cout << " Send TLB MISS command on Internal Network" << std::hex - << " / address = " <<(vci_addr_t)((r_tlb_paddr.read())& CACHE_LINE_MASK) << std::endl; -#endif - } - break; - } - } // end switch r_miss_wti_cmd_fsm - - /////////////////////////////////////////////////////////////////////////////////// - // The MISS_WTI_RSP FSM handles VCI responses on the Internal Network. - // it can be response to TLB MISS (read transaction) or WTI (write transaction). - // It supports several simultaneous VCI transactions. - //////////////////////////////////////////////////////////////////////////////////// - - switch ( r_miss_wti_rsp_fsm.read() ) - { - case MISS_WTI_RSP_IDLE: // waiting a VCI response - { - if ( p_vci_ini_int.rspval.read() ) - { - if ( p_vci_ini_int.rpktid.read() == PKTID_READ ) // it's a TLB MISS response - { - r_miss_wti_rsp_fsm = MISS_WTI_RSP_MISS; - r_miss_wti_rsp_count = 0; - } - else // it's a WTI WRITE response - { - r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI; - - } - } - break; - } - ////////////////////// - case MISS_WTI_RSP_WTI: // Handling response to a WTI transaction - { - assert( p_vci_ini_int.reop.read() and - "VCI_IO_BRIDGE ERROR: IRQ Write response should have one single flit" ); - - assert( ( (p_vci_ini_int.rerror.read()&0x1) == 0 ) and - "VCI_IO_BRIDGE ERROR: IRQ Write response error !!!" ); - // TODO handling error when using the IOMMU IRQ - -#if DEBUG_MISS_WTI -if( m_debug_activated ) -std::cout << " Response to WTI write" << std::endl; -#endif - r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; - break; - } - /////////////////////// - case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS transaction + case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS + // write cache line in r_tlb_buf buffer + // and analyse possible VCI error + // VCI flit is consumed. { if ( p_vci_ini_int.rspval.read() ) @@ -1744,36 +2073,35 @@ if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported { - r_miss_wti_rsp_error = true; - if ( p_vci_ini_int.reop.read() ) - { - r_miss_wti_cmd_fsm = MISS_WTI_RSP_IDLE; - r_tlb_miss_req = false; - } -#if DEBUG_MISS_WTI + // set the specific error flip-flop + r_miss_wti_rsp_error_miss = true; + assert( false and + "VCI_IO_BRIDGE ERROR: VCI error response for a TLB MISS transaction"); + + } + else // no error + { + +#if DEBUG_MISS_WTI_CMD if( m_debug_activated ) -std::cout << " ERROR " << std::endl; -#endif - } - else // no error - { - bool eop = p_vci_ini_int.reop.read(); - -#if DEBUG_MISS_WTI -if( m_debug_activated ) -std::cout << " Response to a tlb miss transaction" +std::cout << " Receive response to a TLB MISS" << " / Count = " << r_miss_wti_rsp_count.read() << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; #endif + r_tlb_buf_data[r_miss_wti_rsp_count.read()] = p_vci_ini_int.rdata.read(); + } + + if ( p_vci_ini_int.reop.read() ) // last flit + { + bool eop = p_vci_ini_int.eop.read(); assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and "VCI_IO_BRIDGE ERROR: invalid length for a TLB MISS response"); - r_tlb_buf_data[r_miss_wti_rsp_count.read()] = p_vci_ini_int.rdata.read(); + r_miss_wti_rsp_count = 0; + r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; + r_tlb_to_miss_wti_cmd_req = false; + } + else // not the last flit + { r_miss_wti_rsp_count = r_miss_wti_rsp_count.read() + 1; - - if ( eop ) - { - r_tlb_miss_req = false; //reset the request flip-flop - r_miss_wti_cmd_fsm = MISS_WTI_RSP_IDLE; - } } } @@ -1782,59 +2110,8 @@ } // end switch r_miss_wti_rsp_fsm - ///////////////////////////////////////////////////////////////////////// - // This flip-flop allocates the access to the CONFIG_RSP fifo - // with a round robin priority between 2 clients FSMs : - // - CONFIG_CMD : to put a response to a local config command. - // - CONFIG_RSP : to put a response to a peripheral config command. - // The ressource is always allocated. - // A new allocation occurs when the owner FSM is not using it, - // and the other FSM is requiring it. - ///////////////////////////////////////////////////////////////////////// - - if ( r_alloc_fifo_config_rsp_local.read() ) - { - if ( (r_config_rsp_fsm.read() != CONFIG_RSP_IDLE) and // config_rsp_fsm requiring - (r_config_cmd_fsm.read() != CONFIG_CMD_RSP) ) // config_cmd_fsm not requiring - r_alloc_fifo_config_rsp_local = false; - } - else - { - if ( (r_config_cmd_fsm.read() == CONFIG_CMD_RSP) and // config_cmd_fsm requiring - (r_config_rsp_fsm.read() == CONFIG_RSP_IDLE) ) // config_rsp_fsm not requiring - r_alloc_fifo_config_rsp_local = true; - } - - ///////////////////////////////////////////////////////////////////////// - // This flip-flop allocates the access to the DMA_RSP fifo - // with a round robin priority between 2 clients FSMs : - // - DMA_CMD : to put a error response in case of bad address translation - // - DMA_RSP : to put a normal response to a DMA transaction. - // The ressource is always allocated. - // A new allocation occurs when the owner FSM is not using it, - // and the other FSM is requiring it. - ///////////////////////////////////////////////////////////////////////// - - if ( r_alloc_fifo_dma_rsp_local.read() ) - { - if ( (r_dma_rsp_fsm.read() == DMA_RSP_FIFO_PUT) and - (r_dma_cmd_fsm.read() != DMA_CMD_FIFO_PUT_RSP) ) - r_alloc_fifo_dma_rsp_local = false; - } - else - { - if ( (r_dma_cmd_fsm.read() == DMA_CMD_FIFO_PUT_RSP) and - (r_dma_rsp_fsm.read() != DMA_RSP_FIFO_PUT) ) - r_alloc_fifo_dma_rsp_local = true; - } - - // Define GET signals for all output FIFOs - dma_cmd_fifo_get = p_vci_ini_ram.cmdack.read(); - dma_rsp_fifo_get = p_vci_tgt_iox.rspack.read(); - config_cmd_fifo_get = p_vci_ini_iox.cmdack.read(); - config_rsp_fifo_get = p_vci_tgt_int.rspack.read(); /////////////////////////////////////////////////////////// // DMA_CMD fifo update - // One writer : DMA_CMD FSM + // writer : DMA_CMD FSM /////////////////////////////////////////////////////////// @@ -1884,55 +2161,29 @@ ////////////////////////////////////////////////////////////// // DMA_RSP fifo update - // Two writers : DMA_CMD FSM & DMA_RSP FSM + // writer : DMA_RSP FSM ////////////////////////////////////////////////////////////// - if (r_alloc_fifo_dma_rsp_local.read() ) // owner is DMA_CMD FSM - // local response for a translation error - { - m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - 0 ); // no data if error - m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_tgt_iox.rsrcid.read() ); - m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_tgt_iox.rtrdid.read() ); - m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_tgt_iox.rpktid.read() ); - m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - true ); // single flit response - m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - 1 ); // error - } - else // owner is DMA_RSP FSM - // normal response to a DMA transaction - { - m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_ram.rdata.read() ); - m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_ram.rsrcid.read() ); - m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_ram.rtrdid.read() ); - m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_ram.rpktid.read() ); - m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_ram.reop.read() ); - m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, - dma_rsp_fifo_put, - p_vci_ini_ram.rerror.read() ); - } + m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rdata ); + m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rsrcid ); + m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rtrdid ); + m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rpktid ); + m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_reop ); + m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rerror ); //////////////////////////////////////////////////////////////// // CONFIG_CMD fifo update - // One writer : CONFIG_CMD FSM + // writer : CONFIG_CMD FSM //////////////////////////////////////////////////////////////// @@ -1982,89 +2233,84 @@ ////////////////////////////////////////////////////////////////////////// // CONFIG_RSP fifo update - // There is two writers : CONFIG_CMD FSM & CONFIG_RSP FSM + // writer : CONFIG_RSP FSM ////////////////////////////////////////////////////////////////////////// - if ( r_alloc_fifo_config_rsp_local.read() ) // owner is CONFIG_CMD FSM - // response for a local config transaction - { - m_config_rsp_data_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - r_config_cmd_rdata.read() ); - m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_tgt_int.srcid.read() ); - m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_tgt_int.trdid.read() ); - m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_tgt_int.pktid.read() ); - m_config_rsp_reop_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - true ); // local config are one flit - m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - r_config_cmd_error.read() ); - } - else // owner is CONFIG_RSP FSM - // response for a remote transaction - { - // PUT depends on CONFIG_RSP FSM state - uint32_t rdata; - bool reop; - if ( r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI ) - { - config_rsp_fifo_put = true; - rdata = (uint32_t)(p_vci_ini_iox.rdata.read()>>32); - reop = p_vci_ini_iox.reop.read(); - } - else if ( r_config_rsp_fsm.read() == CONFIG_RSP_PUT_LO ) - { - config_rsp_fifo_put = true; - rdata = (uint32_t)(p_vci_ini_iox.rdata.read()); - reop = false; - } - else if ( r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC ) - { - config_rsp_fifo_put = true; - rdata = (uint32_t)(p_vci_ini_iox.rdata.read()); - reop = true; - } - else - { - config_rsp_fifo_put = false; - rdata = 0; - reop = false;; - } - - m_config_rsp_data_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - rdata ); - m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_iox.rsrcid.read() ); - m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_iox.rtrdid.read() ); - m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_iox.rpktid.read() ); - m_config_rsp_reop_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - reop ); - m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, - config_rsp_fifo_put, - p_vci_ini_iox.rerror.read() ); - } + m_config_rsp_data_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rdata ); + m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rsrcid ); + m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rtrdid ); + m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rpktid ); + m_config_rsp_reop_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_reop ); + m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rerror ); + + //////////////////////////////////////////////////////////////// + // MISS_WTI_CMD fifo update + // One writer : MISS_WTI switch + //////////////////////////////////////////////////////////////// + + m_miss_wti_cmd_addr_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_address ); + m_miss_wti_cmd_cmd_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_cmd ); + m_miss_wti_cmd_contig_fifo.update( config_cmd_fifo_get, + miss_wti_cmd_fifo_put, + true ); + m_miss_wti_cmd_cons_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + false ); + m_miss_wti_cmd_plen_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + 4 ); + m_miss_wti_cmd_wrap_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + false ); + m_miss_wti_cmd_cfixed_fifo.update( config_cmd_fifo_get, + miss_wti_cmd_fifo_put, + false ); + m_miss_wti_cmd_clen_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + 0 ); + m_miss_wti_cmd_srcid_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_srcid ); + m_miss_wti_cmd_trdid_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_trdid ); + m_miss_wti_cmd_pktid_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_pktid ); + m_miss_wti_cmd_data_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_wdata ); + m_miss_wti_cmd_be_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + 0xF ); + m_miss_wti_cmd_eop_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + true ); } // end transition() -/////////////////////// +////////////////////////////////////////////////////////////////////////// tmpl(void)::genMoore() -/////////////////////// +////////////////////////////////////////////////////////////////////////// { + ///////////////// p_vci_ini_ram ///////////////////////////// + // VCI initiator command on RAM network // directly the content of the dma_cmd FIFO - p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); p_vci_ini_ram.address = m_dma_cmd_addr_fifo.read(); @@ -2083,27 +2329,13 @@ p_vci_ini_ram.srcid = m_dma_cmd_srcid_fifo.read(); - // VCI target command ack on IOX network - // depends on the DMA_CMD FSM state - - switch ( r_dma_cmd_fsm.read() ) - { - case DMA_CMD_IDLE: - case DMA_CMD_MISS_WAIT: - p_vci_tgt_iox.cmdack = false; - break; - case DMA_CMD_WAIT_EOP: - p_vci_tgt_iox.cmdack = true; - break; - case DMA_CMD_FIFO_PUT_CMD: - p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); - break; - case DMA_CMD_FIFO_PUT_RSP: - p_vci_tgt_iox.cmdack = m_dma_rsp_data_fifo.wok(); - break; - } - - // VCI target response on IOX network + // VCI initiator response on the RAM Network + // depends on the DMA_RSP FSM state + p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and + (r_dma_rsp_fsm.read() == DMA_RSP_PUT_DMA); + + ///////////////// p_vci_tgt_iox ///////////////////////////// + + // VCI target response on IOX network is // directly the content of the DMA_RSP FIFO - p_vci_tgt_iox.rspval = m_dma_rsp_data_fifo.rok(); p_vci_tgt_iox.rsrcid = m_dma_rsp_rsrcid_fifo.read(); @@ -2114,14 +2346,35 @@ p_vci_tgt_iox.reop = m_dma_rsp_reop_fifo.read(); - // VCI initiator response on the RAM Network - // depends on the DMA_RSP FSM state - - p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and - (r_dma_rsp_fsm.read() == DMA_RSP_FIFO_PUT) and - not r_alloc_fifo_dma_rsp_local.read(); - - // VCI initiator command on IOX network + // VCI target command ack on IOX network + // depends on the DMA_CMD FSM state + switch ( r_dma_cmd_fsm.read() ) + { + case DMA_CMD_IDLE: + p_vci_tgt_iox.cmdack = false; + break; + case DMA_CMD_DMA_REQ: + p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); + break; + case DMA_CMD_WTI_IOX_REQ: + p_vci_tgt_iox.cmdack = not r_dma_cmd_to_miss_wti_cmd_req.read(); + break; + case DMA_CMD_ERR_WTI_REQ: + p_vci_tgt_iox.cmdack = false; + break; + case DMA_CMD_ERR_WAIT_EOP: + p_vci_tgt_iox.cmdack = true; + break; + case DMA_CMD_ERR_RSP_REQ: + p_vci_tgt_iox.cmdack = false; + break; + case DMA_CMD_TLB_MISS_WAIT: + p_vci_tgt_iox.cmdack = false; + break; + } + + ////////////////// p_vci_ini_iox ///////////////////////////// + + // VCI initiator command on IOX network is // directly the content of the CONFIG_CMD FIFO - p_vci_ini_iox.cmdval = m_config_cmd_addr_fifo.rok(); p_vci_ini_iox.address = m_config_cmd_addr_fifo.read(); @@ -2140,7 +2393,24 @@ p_vci_ini_iox.srcid = m_config_cmd_srcid_fifo.read(); + // VCI initiator response on IOX Network + // it depends on the CONFIG_RSP FSM state + p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and + ( (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC) or + (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI) ); + + ///////////////// p_vci_tgt_int //////////////////////////////// + + // VCI target response on INT network + // directly the content of the CONFIG_RSP FIFO + p_vci_tgt_int.rspval = m_config_rsp_data_fifo.rok(); + p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); + p_vci_tgt_int.rtrdid = m_config_rsp_rtrdid_fifo.read(); + p_vci_tgt_int.rpktid = m_config_rsp_rpktid_fifo.read(); + p_vci_tgt_int.rdata = m_config_rsp_data_fifo.read(); + p_vci_tgt_int.rerror = m_config_rsp_rerror_fifo.read(); + p_vci_tgt_int.reop = m_config_rsp_reop_fifo.read(); + // VCI target command ack on INT network // it depends on the CONFIG_CMD FSM state - switch ( r_config_cmd_fsm.read() ) { @@ -2159,74 +2429,39 @@ } - // VCI target response on INT network - // directly the content of the CONFIG_RSP FIFO - - p_vci_tgt_int.rspval = m_config_rsp_data_fifo.rok(); - p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); - p_vci_tgt_int.rtrdid = m_config_rsp_rtrdid_fifo.read(); - p_vci_tgt_int.rpktid = m_config_rsp_rpktid_fifo.read(); - p_vci_tgt_int.rdata = m_config_rsp_data_fifo.read(); - p_vci_tgt_int.rerror = m_config_rsp_rerror_fifo.read(); - p_vci_tgt_int.reop = m_config_rsp_reop_fifo.read(); - - // VCI initiator response on IOX Network - // it depends on the CONFIG_RSP FSM state - - p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and - not r_alloc_fifo_config_rsp_local.read() and - ( (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC) or - (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI) ); + ///////////////// p_vci_ini_int //////////////////////////////// // VCI initiator command on INT network - // it depends on the MISS_WTI_CMD FSM state - // - WTI : single flit WRITE - // - MISS TLB : multi-flit READ for a complete cache line - - // default values - p_vci_ini_int.srcid = m_int_srcid; - p_vci_ini_int.trdid = 0; - p_vci_ini_int.cfixed = false; - p_vci_ini_int.eop = true; - p_vci_ini_int.wrap = false; - p_vci_ini_int.clen = 0; - p_vci_ini_int.contig = true; - p_vci_ini_int.cons = false; - p_vci_ini_int.be = 0xF; - - switch ( r_miss_wti_cmd_fsm.read() ) - { - case MISS_WTI_CMD_IDLE: - p_vci_ini_int.cmdval = false; - p_vci_ini_int.address = 0; - p_vci_ini_int.cmd = vci_param_int::CMD_NOP; - p_vci_ini_int.pktid = PKTID_READ; - p_vci_ini_int.wdata = 0; - p_vci_ini_int.plen = 0; - break; - - case MISS_WTI_CMD_WTI: - p_vci_ini_int.cmdval = true; - p_vci_ini_int.address = r_iommu_peri_wti[r_miss_wti_cmd_index.read()].read(); - p_vci_ini_int.cmd = vci_param_int::CMD_WRITE; - p_vci_ini_int.pktid = PKTID_WRITE; - p_vci_ini_int.wdata = (int_data_t)r_irq_pending[r_miss_wti_cmd_index.read()].read(); - p_vci_ini_int.plen = vci_param_int::B; - break; - - case MISS_WTI_CMD_MISS: - p_vci_ini_int.cmdval = true; - p_vci_ini_int.address = r_tlb_paddr.read() & CACHE_LINE_MASK; - p_vci_ini_int.cmd = vci_param_int::CMD_READ; - p_vci_ini_int.pktid = PKTID_READ; - p_vci_ini_int.wdata = 0; - p_vci_ini_int.plen = m_words*(vci_param_int::B); - break; - } + // directly the content of the MISS_WTI_CMD FIFO + p_vci_ini_int.cmdval = m_miss_wti_cmd_addr_fifo.rok(); + p_vci_ini_int.address = m_miss_wti_cmd_addr_fifo.read(); + p_vci_ini_int.be = m_miss_wti_cmd_be_fifo.read(); + p_vci_ini_int.cmd = m_miss_wti_cmd_cmd_fifo.read(); + p_vci_ini_int.contig = m_miss_wti_cmd_contig_fifo.read(); + p_vci_ini_int.wdata = m_miss_wti_cmd_data_fifo.read(); + p_vci_ini_int.eop = m_miss_wti_cmd_eop_fifo.read(); + p_vci_ini_int.cons = m_miss_wti_cmd_cons_fifo.read(); + p_vci_ini_int.plen = m_miss_wti_cmd_plen_fifo.read(); + p_vci_ini_int.wrap = m_miss_wti_cmd_wrap_fifo.read(); + p_vci_ini_int.cfixed = m_miss_wti_cmd_cfixed_fifo.read(); + p_vci_ini_int.clen = m_miss_wti_cmd_clen_fifo.read(); + p_vci_ini_int.trdid = m_miss_wti_cmd_trdid_fifo.read(); + p_vci_ini_int.pktid = m_miss_wti_cmd_pktid_fifo.read(); + p_vci_ini_int.srcid = m_miss_wti_cmd_srcid_fifo.read(); // VCI initiator response on INT network // It depends on the MISS_WTI_RSP FSM state - if ( r_miss_wti_rsp_fsm.read() == MISS_WTI_RSP_IDLE ) p_vci_ini_int.rspack = false; - else p_vci_ini_int.rspack = true; + if ( r_miss_wti_rsp_fsm.read() == MISS_WTI_RSP_IDLE ) + { + p_vci_ini_int.rspack = false; + } + else if ( r_miss_wti_rsp_fsm.read() == MISS_WTI_RSP_WTI_IOX ) + { + p_vci_ini_int.rspack = not r_miss_wti_rsp_to_dma_rsp_req.read(); + } + else // MISS_WTI_RSP_MISS or MISS_WTI_RESP_WTI_MMU + { + p_vci_ini_int.rspack = true; + } } // end genMoore Index: /trunk/modules/vci_io_bridge/include/soclib/io_bridge.h =================================================================== --- /trunk/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 711) +++ /trunk/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 712) @@ -29,5 +29,5 @@ // IOB Configuration registers -// Minimal required segment size = 512 bytes (128 words) +// Minimal required segment size = 64 bytes (16 words) enum { @@ -39,9 +39,10 @@ IOB_INVAL_PTE = 5, // W : Invalidate PTE (using virtual address) IOB_WTI_ENABLE = 6, // R/W : Enable WTI (both IOB and external IRQs) - IOB_WTI_ADDR_LO = 7, // R/W : WTI for IOB itself (32 LSB address bits) - IOB_WTI_ADDR_HI = 8, // R/W : WTI for IOB itself (32 MSB address bits) - IOB_PERI_WTI_BEGIN = 64, // R/W : two 32 bits words per IRQ + IOB_WTI_ADDR_LO = 7, // R/W : IOB WTI address (32 LSB bits) + IOB_WTI_ADDR_HI = 8, // R/W : IOB WTI address (32 MSB bits) + IOB_XICU_BASE = 9, // R/W : XICU pbase address in cluster 0 + IOB_XICU_SIZE = 10, // R/W : XICU segment size /**/ - IOB_SPAN = 128, + IOB_SPAN = 16, }; @@ -51,10 +52,10 @@ { MMU_NONE = 0x0000, // None - MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access to a non writable page - MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write Bus Error accessing Table 1 - MMU_READ_PT1_UNMAPPED = 0x1001, // Read Page fault on Page Table 1 - MMU_READ_PT2_UNMAPPED = 0x1002, // Read Page fault on Page Table 2 - MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read Bus Error in Table1 access - MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read Bus Error in Table2 access + MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access to non writable page + MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write Bus Error accessing Table 1 + MMU_READ_PT1_UNMAPPED = 0x1001, // Read Page fault on Page Table 1 + MMU_READ_PT2_UNMAPPED = 0x1002, // Read Page fault on Page Table 2 + MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read Bus Error in Table1 access + MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read Bus Error in Table2 access MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read Bus Error in cache access };