Changeset 714 for trunk/platforms/tsar_generic_iob
- Timestamp:
- Jun 20, 2014, 2:42:53 PM (10 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 3 edited
- 1 moved
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arch.py (moved) (moved from trunk/platforms/tsar_generic_iob/genmap.py) (7 diffs)
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top.cpp (modified) (16 diffs)
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tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (1 diff)
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tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/platforms/tsar_generic_iob/arch.py
r710 r714 4 4 5 5 ####################################################################################### 6 # file : genmap.py6 # file : arch.py (for the tsar_generic_iob architecture) 7 7 # date : may 2014 8 8 # author : Alain Greiner … … 14 14 # components located in cluster [0,0] and cluster [x_size-1, y_size-1]. 15 15 # Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. 16 # The parameters are: 17 # - x_size : number of clusters in a row 18 # - y_size : number of clusters in a column 19 # - procs_max : number of processors per cluster 20 # - nb_ttys : number of TTY channels 21 # - nb_nics : number of NIC channels 22 # - fbf_size : frame_buffer width = frame_buffer heigth 23 # - x_io : cluster_io x coordinate 24 # - y_io : cluster_io y coordinate 16 # 17 # The "constructor" parameters are: 18 # - x_size : number of clusters in a row 19 # - y_size : number of clusters in a column 20 # - nb_procs : number of processors per cluster 21 # 22 # The "hidden" platform parameters are: 23 # - nb_ttys : number of TTY channels 24 # - nb_nics : number of NIC channels 25 # - fbf_width : frame_buffer width = frame_buffer heigth 26 # - x_io : cluster_io x coordinate 27 # - y_io : cluster_io y coordinate 28 # - x_width : number of bits for x coordinate 29 # - y_width : number of bits for y coordinate 30 # - paddr_width : number of bits for physical address 31 # - irq_per_proc : number of input IRQs per processor 32 # - use_ramdisk : use a ramdisk when True 33 # - peri_increment : address increment for replicated peripherals 25 34 #################################################################################### 26 35 27 ########################## 28 def genmap( x_size = 2, 29 y_size = 2, 30 nb_procs = 2, 31 nb_ttys = 1, 32 nb_nics = 2, 33 fbf_width = 128, 34 x_io = 0, 35 y_io = 0 ): 36 36 ######################## 37 def arch( x_size = 2, 38 y_size = 2, 39 nb_procs = 2 ): 40 41 ### define architecture constants 42 43 nb_ttys = 1 44 nb_nics = 2 45 fbf_width = 1024 46 x_io = 0 47 y_io = 0 48 x_width = 4 49 y_width = 4 50 paddr_width = 40 51 irq_per_proc = 4 52 use_ramdisk = False 53 peri_increment = 0x10000 54 37 55 ### parameters checking 56 38 57 assert( nb_procs <= 4 ) 39 58 … … 44 63 or (y_size == 8) or (y_size == 16) ) 45 64 46 assert( nb_ttys <= 2)65 assert( nb_ttys == 1 ) 47 66 48 67 assert( ((x_io == 0) and (y_io == 0)) or 49 68 ((x_io == x_size-1) and (y_io == y_size-1)) ) 50 69 51 ### define architecture constants 52 53 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) 54 x_width = 4 55 y_width = 4 56 paddr_width = 40 57 irq_per_proc = 4 58 use_ramdisk = False 59 70 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) 71 60 72 ### define physical segments 61 73 62 74 ram_base = 0x0000000000 63 ram_size = 0x4000000 75 ram_size = 0x4000000 # 64 Mbytes 64 76 65 77 xcu_base = 0x00B0000000 66 xcu_size = 0x1000 78 xcu_size = 0x1000 # 4 Kbytes 67 79 68 80 dma_base = 0x00B1000000 69 dma_size = 0x1000 * nb_procs 81 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 70 82 71 83 mmc_base = 0x00B2000000 72 mmc_size = 0x1000 84 mmc_size = 0x1000 # 4 Kbytes 73 85 74 86 offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) 75 87 76 88 bdv_base = 0x00B3000000 + offset_io 77 bdv_size = 0x1000 89 bdv_size = 0x1000 # 4kbytes 78 90 79 91 tty_base = 0x00B4000000 + offset_io 80 tty_size = 0x4000 92 tty_size = 0x4000 # 16 Kbytes 81 93 82 94 nic_base = 0x00B5000000 + offset_io 83 nic_size = 0x80000 95 nic_size = 0x80000 # 512 kbytes 84 96 85 97 cma_base = 0x00B6000000 + offset_io 86 cma_size = 0x1000 * 2 * nb_nics 98 cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics 87 99 88 100 fbf_base = 0x00B7000000 + offset_io 89 fbf_size = fbf_width * fbf_width 101 fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes 90 102 91 103 pic_base = 0x00B8000000 + offset_io 92 pic_size = 0x1000 104 pic_size = 0x1000 # 4 Kbytes 93 105 94 106 iob_base = 0x00BE000000 + offset_io 95 iob_size = 0x1000 107 iob_size = 0x1000 # 4kbytes 96 108 97 109 rom_base = 0x00BFC00000 + offset_io 98 rom_size = 0x4000 110 rom_size = 0x4000 # 16 Kbytes 99 111 100 112 ### define bootloader vsegs base addresses 101 113 102 boot_mapping_vbase = 0x00000000 103 boot_mapping_size = 0x00010000 104 105 boot_code_vbase = 0x00010000 106 boot_code_size = 0x00020000 114 boot_mapping_vbase = 0x00000000 # ident 115 boot_mapping_size = 0x00010000 # 64 Kbytes 116 117 boot_code_vbase = 0x00010000 # ident 118 boot_code_size = 0x00020000 # 128 Kbytes 107 119 108 boot_data_vbase = 0x00030000 109 boot_data_size = 0x00010000 110 111 boot_buffer_vbase = 0x00040000 112 boot_buffer_size = 0x00060000 113 114 boot_stack_vbase = 0x000A0000 115 boot_stack_size = 0x00050000 120 boot_data_vbase = 0x00030000 # ident 121 boot_data_size = 0x00010000 # 64 Kbytes 122 123 boot_buffer_vbase = 0x00040000 # ident 124 boot_buffer_size = 0x00060000 # 384 Kbytes 125 126 boot_stack_vbase = 0x000A0000 # ident 127 boot_stack_size = 0x00050000 # 320 Kbytes 116 128 117 129 ### define kernel vsegs base addresses 118 130 119 131 kernel_code_vbase = 0x80000000 120 kernel_code_size = 0x00020000 132 kernel_code_size = 0x00020000 # 128 Kbytes 121 133 122 134 kernel_data_vbase = 0x80020000 123 kernel_data_size = 0x00060000 135 kernel_data_size = 0x00060000 # 384 Kbytes 124 136 125 137 kernel_uncdata_vbase = 0x80080000 126 kernel_uncdata_size = 0x00040000 138 kernel_uncdata_size = 0x00040000 # 256 Kbytes 127 139 128 140 kernel_init_vbase = 0x800C0000 129 kernel_init_size = 0x00010000 141 kernel_init_size = 0x00010000 # 64 Kbytes 130 142 131 143 kernel_sched_vbase = 0xF0000000 # distributed in all clusters … … 134 146 ### create mapping 135 147 136 mapping = Mapping( name = platform_name, 137 x_size = x_size, 138 y_size = y_size, 139 procs_max = nb_procs, 140 x_width = x_width, 141 y_width = y_width, 142 paddr_width = paddr_width, 143 coherence = True, 144 irq_per_proc = irq_per_proc, 145 use_ramdisk = use_ramdisk, 146 x_io = x_io, 147 y_io = y_io ) 148 mapping = Mapping( name = platform_name, 149 x_size = x_size, 150 y_size = y_size, 151 procs_max = nb_procs, 152 x_width = x_width, 153 y_width = y_width, 154 paddr_width = paddr_width, 155 coherence = True, 156 irq_per_proc = irq_per_proc, 157 use_ramdisk = use_ramdisk, 158 x_io = x_io, 159 y_io = y_io, 160 peri_increment = peri_increment ) 148 161 149 162 ### external peripherals (accessible in cluster[0,0] only for this mapping) … … 159 172 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) 160 173 161 fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = 128)174 fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) 162 175 163 176 rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' ) … … 198 211 ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) 199 212 200 # DMA IRQs replicated in all clusters201 for p in xrange( nb_procs ):202 mapping.addIrq( xcu, index = (p+1), isrtype = 'ISR_DMA', channel = p )203 204 213 # MMC IRQ replicated in all clusters 205 214 mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) … … 266 275 vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True ) 267 276 268 ### Global vsegs for replicated peripherals, and for scheduler. 269 ### A replicated vseg is replicated in all clusters: vseg name is indexed by (x,y), 270 ### and vseg base address is incremented by (cluster_xy * 0x10000) 271 272 mapping.addGlobal( 'seg_xcu' , xcu_base , xcu_size , '__W_', 273 vtype = 'PERI' , x = 0, y = 0, pseg = 'XCU', replicated = True ) 274 275 mapping.addGlobal( 'seg_dma' , dma_base , dma_size , '__W_', 276 vtype = 'PERI' , x = 0, y = 0, pseg = 'DMA', replicated = True ) 277 278 mapping.addGlobal( 'seg_mmc' , mmc_base , mmc_size , '__W_', 279 vtype = 'PERI' , x = 0, y = 0, pseg = 'MMC', replicated = True ) 280 281 mapping.addGlobal( 'seg_sched', kernel_sched_vbase, kernel_sched_size, 'C_W_', 282 vtype = 'SCHED', x = 0, y = 0, pseg = 'RAM', replicated = True ) 277 ### Global vsegs for replicated peripherals, and for schedulers 278 ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment) 279 280 for x in xrange( x_size ): 281 for y in xrange( y_size ): 282 cluster_xy = (x << y_width) + y; 283 offset = cluster_xy * peri_increment 284 285 mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, 286 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) 287 288 mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size, 289 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA' ) 290 291 mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, 292 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC' ) 293 294 mapping.addGlobal( 'seg_sched_%d_%d' %(x,y), kernel_sched_vbase + offset, kernel_sched_size, 295 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM' ) 283 296 284 297 ### return mapping ### -
trunk/platforms/tsar_generic_iob/top.cpp
r710 r714 85 85 // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) 86 86 // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) 87 // - FBUF_X_SIZE : width of frame buffer (pixels) 88 // - FBUF_Y_SIZE : heigth of frame buffer (lines) 89 // - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs 87 90 // 88 91 // Some secondary hardware parameters must be defined in this top.cpp file: … … 94 97 // - L1_DWAYS 95 98 // - L1_DSETS 96 // - FBUF_X_SIZE : width of frame buffer (pixels)97 // - FBUF_Y_SIZE : heigth of frame buffer (lines)98 // - BDEV_SECTOR_SIZE : block size for block drvice99 99 // - BDEV_IMAGE_NAME : file pathname for block device 100 100 // - NIC_RX_NAME : file pathname for NIC received packets … … 209 209 #define L1_DSETS 64 210 210 211 #define FBUF_X_SIZE 128212 #define FBUF_Y_SIZE 128213 214 #define BDEV_SECTOR_SIZE 512215 211 #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" 216 212 … … 236 232 //////////////////////i///////////////////////////////////// 237 233 238 #define MAX_FROZEN_CYCLES 10000234 #define MAX_FROZEN_CYCLES 200000 239 235 240 236 ///////////////////////////////////////////////////////// … … 383 379 size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 384 380 size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 385 size_t block_size = BDEV_SECTOR_SIZE; // disk block size386 381 size_t x_width = 4; // at most 256 clusters 387 382 size_t y_width = 4; // at most 256 clusters … … 415 410 { 416 411 debug_memc_id = atoi(argv[n+1]); 417 418 std::cout << "@@@@@@@@@@@@@@ MEMCID = " << debug_memc_id << std::endl;419 420 412 size_t x = debug_memc_id >> 4; 421 413 size_t y = debug_memc_id & 0xF; … … 998 990 IntTab(0, IOX_BDEV_TGT_ID), 999 991 disk_name, 1000 block_size,992 512, // block size 1001 993 64, // burst size (bytes) 1002 994 0 ); // disk latency … … 1103 1095 L1_DSETS, 1104 1096 XRAM_LATENCY, 1097 XCU_NB_INPUTS, 1105 1098 1106 1099 loader, … … 1150 1143 bdev->p_resetn (signal_resetn); 1151 1144 bdev->p_irq (signal_irq_bdev); 1152 1153 // For AHCI1154 // bdev->p_channel_irq[0] (signal_irq_bdev);1155 1156 1145 bdev->p_vci_target (signal_vci_tgt_bdev); 1157 1146 bdev->p_vci_initiator (signal_vci_ini_bdev); … … 1481 1470 { 1482 1471 // stats display 1483 if( (n % 5000000) == 0)1472 if( (n % 1000000) == 0) 1484 1473 { 1485 1474 gettimeofday(&t2, NULL); … … 1489 1478 uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + 1490 1479 (uint64_t) t2.tv_usec / 1000; 1491 std::cerr << "platform clock frequency " 1480 std::cerr << "### cycle = " << n 1481 << " / frequency = " 1492 1482 << (double) 5000000 / (double) (ms2 - ms1) << "Khz" 1493 1483 << std::endl; … … 1519 1509 1520 1510 clusters[x][y]->proc[l]->print_trace(1); 1521 1522 1511 std::ostringstream proc_signame; 1523 1512 proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; … … 1525 1514 1526 1515 clusters[x][y]->xicu->print_trace(l); 1527 1528 1516 std::ostringstream xicu_signame; 1529 1517 xicu_signame << "[SIG]XICU_" << x << "_" << y; 1530 1518 clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); 1519 1520 // clusters[x][y]->mdma->print_trace(); 1521 // std::ostringstream mdma_signame; 1522 // mdma_signame << "[SIG]MDMA_" << x << "_" << y; 1523 // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); 1531 1524 1532 1525 if( clusters[x][y]->signal_proc_it[l].read() ) … … 1534 1527 << x << "_" << y << "_" << l << " ACTIVE" << std::endl; 1535 1528 } 1536 1537 // trace INT network1538 // clusters[0][0]->int_xbar_cmd_d->print_trace();1539 // clusters[0][0]->int_xbar_rsp_d->print_trace();1540 1541 // clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace("[SIG] INT_CMD_L2G_D_0_0");1542 // clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace("[SIG] INT_RSP_G2L_D_0_0");1543 1544 // clusters[0][0]->int_router_cmd->print_trace(0);1545 // clusters[0][0]->int_router_rsp->print_trace(0);1546 1547 // trace INT_CMD_D xbar and router in cluster 0_11548 // clusters[0][1]->int_router_cmd->print_trace(0);1549 // clusters[0][1]->int_router_rsp->print_trace(0);1550 1551 // clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace("[SIG] INT_CMD_G2L_D_0_0");1552 // clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace("[SIG] INT_RSP_L2G_D_0_0");1553 1554 // clusters[0][1]->int_xbar_cmd_d->print_trace();1555 // clusters[0][1]->int_xbar_rsp_d->print_trace();1556 1529 1557 1530 // trace memc[debug_memc_id] … … 1619 1592 signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 1620 1593 1594 mnic->print_trace(); 1595 signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); 1596 1621 1597 // fbuf->print_trace(); 1622 1598 // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); … … 1628 1604 1629 1605 // interrupts 1630 if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; 1631 if (signal_irq_mtty_rx) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; 1606 if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; 1607 if (signal_irq_mtty_rx) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; 1608 if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; 1609 if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; 1610 if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; 1611 if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; 1632 1612 } 1633 1613 } -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r707 r714 216 216 size_t l1_d_sets, 217 217 size_t xram_latency, 218 size_t xcu_nb_inputs, 218 219 219 220 const Loader &loader, // loader for XRAM -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r707 r714 70 70 size_t l1_d_sets, 71 71 size_t xram_latency, 72 size_t xcu_nb_inputs, 72 73 73 74 const Loader &loader, … … 183 184 mt_int, // mapping table INT network 184 185 IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space 185 32,// number of timer IRQs186 32,// number of hard IRQs187 32,// number of soft IRQs188 32); // number of output IRQs186 xcu_nb_inputs, // number of timer IRQs 187 xcu_nb_inputs, // number of hard IRQs 188 xcu_nb_inputs, // number of soft IRQs 189 16); // number of output IRQs 189 190 190 191 //////////// MDMA … … 452 453 } 453 454 454 int_wi_gate_d->p_clk 455 int_wi_gate_d->p_resetn 456 int_wi_gate_d->p_vci 457 int_wi_gate_d->p_dspin_cmd 458 int_wi_gate_d->p_dspin_rsp 459 460 int_wt_gate_d->p_clk 461 int_wt_gate_d->p_resetn 462 int_wt_gate_d->p_vci 463 int_wt_gate_d->p_dspin_cmd 464 int_wt_gate_d->p_dspin_rsp 455 int_wi_gate_d->p_clk (this->p_clk); 456 int_wi_gate_d->p_resetn (this->p_resetn); 457 int_wi_gate_d->p_vci (signal_int_vci_l2g); 458 int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); 459 int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); 460 461 int_wt_gate_d->p_clk (this->p_clk); 462 int_wt_gate_d->p_resetn (this->p_resetn); 463 int_wt_gate_d->p_vci (signal_int_vci_g2l); 464 int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); 465 int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); 465 466 466 467 ////////////////////// M2P DSPIN local crossbar coherence … … 512 513 xicu->p_resetn (this->p_resetn); 513 514 xicu->p_vci (signal_int_vci_tgt_xicu); 514 for ( size_t p=0 ; p < 32 ; p++)515 { 516 xicu->p_irq[ p] (signal_proc_it[p]);517 } 518 for ( size_t i=0 ; i <32; i++)515 for ( size_t i=0 ; i < 16 ; i++) 516 { 517 xicu->p_irq[i] (signal_proc_it[i]); 518 } 519 for ( size_t i=0 ; i < xcu_nb_inputs ; i++) 519 520 { 520 521 if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
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