Index: trunk/platforms/tsar_generic_iob/arch.py =================================================================== --- trunk/platforms/tsar_generic_iob/arch.py (revision 714) +++ trunk/platforms/tsar_generic_iob/arch.py (revision 714) @@ -0,0 +1,329 @@ +#!/usr/bin/env python + +from mapping import * + +####################################################################################### +# file : arch.py (for the tsar_generic_iob architecture) +# date : may 2014 +# author : Alain Greiner +####################################################################################### +# This file contains a mapping generator for the "tsar_generic_iob" platform. +# This includes both the hardware architecture (clusters, processors, peripherals, +# physical space segmentation) and the mapping of all kernel objects (global vsegs). +# This platform includes 6 external peripherals, accessible through two IO_Bridge +# components located in cluster [0,0] and cluster [x_size-1, y_size-1]. +# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. +# +# The "constructor" parameters are: +# - x_size : number of clusters in a row +# - y_size : number of clusters in a column +# - nb_procs : number of processors per cluster +# +# The "hidden" platform parameters are: +# - nb_ttys : number of TTY channels +# - nb_nics : number of NIC channels +# - fbf_width : frame_buffer width = frame_buffer heigth +# - x_io : cluster_io x coordinate +# - y_io : cluster_io y coordinate +# - x_width : number of bits for x coordinate +# - y_width : number of bits for y coordinate +# - paddr_width : number of bits for physical address +# - irq_per_proc : number of input IRQs per processor +# - use_ramdisk : use a ramdisk when True +# - peri_increment : address increment for replicated peripherals +#################################################################################### + +######################## +def arch( x_size = 2, + y_size = 2, + nb_procs = 2 ): + + ### define architecture constants + + nb_ttys = 1 + nb_nics = 2 + fbf_width = 1024 + x_io = 0 + y_io = 0 + x_width = 4 + y_width = 4 + paddr_width = 40 + irq_per_proc = 4 + use_ramdisk = False + peri_increment = 0x10000 + + ### parameters checking + + assert( nb_procs <= 4 ) + + assert( (x_size == 1) or (x_size == 2) or (x_size == 4) + or (y_size == 8) or (x_size == 16) ) + + assert( (y_size == 1) or (y_size == 2) or (y_size == 4) + or (y_size == 8) or (y_size == 16) ) + + assert( nb_ttys == 1 ) + + assert( ((x_io == 0) and (y_io == 0)) or + ((x_io == x_size-1) and (y_io == y_size-1)) ) + + platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) + + ### define physical segments + + ram_base = 0x0000000000 + ram_size = 0x4000000 # 64 Mbytes + + xcu_base = 0x00B0000000 + xcu_size = 0x1000 # 4 Kbytes + + dma_base = 0x00B1000000 + dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs + + mmc_base = 0x00B2000000 + mmc_size = 0x1000 # 4 Kbytes + + offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) + + bdv_base = 0x00B3000000 + offset_io + bdv_size = 0x1000 # 4kbytes + + tty_base = 0x00B4000000 + offset_io + tty_size = 0x4000 # 16 Kbytes + + nic_base = 0x00B5000000 + offset_io + nic_size = 0x80000 # 512 kbytes + + cma_base = 0x00B6000000 + offset_io + cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics + + fbf_base = 0x00B7000000 + offset_io + fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes + + pic_base = 0x00B8000000 + offset_io + pic_size = 0x1000 # 4 Kbytes + + iob_base = 0x00BE000000 + offset_io + iob_size = 0x1000 # 4kbytes + + rom_base = 0x00BFC00000 + offset_io + rom_size = 0x4000 # 16 Kbytes + + ### define bootloader vsegs base addresses + + boot_mapping_vbase = 0x00000000 # ident + boot_mapping_size = 0x00010000 # 64 Kbytes + + boot_code_vbase = 0x00010000 # ident + boot_code_size = 0x00020000 # 128 Kbytes + + boot_data_vbase = 0x00030000 # ident + boot_data_size = 0x00010000 # 64 Kbytes + + boot_buffer_vbase = 0x00040000 # ident + boot_buffer_size = 0x00060000 # 384 Kbytes + + boot_stack_vbase = 0x000A0000 # ident + boot_stack_size = 0x00050000 # 320 Kbytes + + ### define kernel vsegs base addresses + + kernel_code_vbase = 0x80000000 + kernel_code_size = 0x00020000 # 128 Kbytes + + kernel_data_vbase = 0x80020000 + kernel_data_size = 0x00060000 # 384 Kbytes + + kernel_uncdata_vbase = 0x80080000 + kernel_uncdata_size = 0x00040000 # 256 Kbytes + + kernel_init_vbase = 0x800C0000 + kernel_init_size = 0x00010000 # 64 Kbytes + + kernel_sched_vbase = 0xF0000000 # distributed in all clusters + kernel_sched_size = 0x1000 * nb_procs # 4 kbytes per processor + + ### create mapping + + mapping = Mapping( name = platform_name, + x_size = x_size, + y_size = y_size, + procs_max = nb_procs, + x_width = x_width, + y_width = y_width, + paddr_width = paddr_width, + coherence = True, + irq_per_proc = irq_per_proc, + use_ramdisk = use_ramdisk, + x_io = x_io, + y_io = y_io, + peri_increment = peri_increment ) + + ### external peripherals (accessible in cluster[0,0] only for this mapping) + + iob = mapping.addPeriph( 'IOB', base = iob_base, size = iob_size, ptype = 'IOB' ) + + bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, ptype = 'IOC', subtype = 'BDV' ) + + tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) + + nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) + + cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) + + fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) + + rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' ) + + pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) + + mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 ) + mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 ) + + mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 ) + mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 ) + + mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 ) + mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 ) + mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 ) + mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 ) + + mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 ) + + mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) + + ### hardware components replicated in all clusters + + for x in xrange( x_size ): + for y in xrange( y_size ): + cluster_xy = (x << y_width) + y; + offset = cluster_xy << (paddr_width - x_width - y_width) + + ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) + + mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, + ptype = 'MMC' ) + + dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, + ptype = 'DMA', channels = nb_procs ) + + xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, + ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) + + # MMC IRQ replicated in all clusters + mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) + + # processors + for p in xrange ( nb_procs ): + mapping.addProc( x, y, p ) + + ### global vsegs for boot_loader / identity mapping + + mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', + vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + ### global vsegs for kernel + + mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + ### global vsegs for external peripherals / identity mapping + + mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) + + mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) + + mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) + + mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) + + mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) + + mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) + + mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) + + mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', + vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True ) + + ### Global vsegs for replicated peripherals, and for schedulers + ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment) + + for x in xrange( x_size ): + for y in xrange( y_size ): + cluster_xy = (x << y_width) + y; + offset = cluster_xy * peri_increment + + mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) + + mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA' ) + + mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC' ) + + mapping.addGlobal( 'seg_sched_%d_%d' %(x,y), kernel_sched_vbase + offset, kernel_sched_size, + 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM' ) + + ### return mapping ### + + return mapping + +################################# platform test ####################################################### + +if __name__ == '__main__': + + mapping = genmap( x_size = 2, + y_size = 2, + nb_procs = 2, + nb_ttys = 1, + nb_nics = 2, + fbf_width = 128, + x_io = 0, + y_io = 0 ) + +# print mapping.netbsd_dts() + + print mapping.xml() + +# print mapping.giet_vsegs() + + +# Local Variables: +# tab-width: 4; +# c-basic-offset: 4; +# c-file-offsets:((innamespace . 0)(inline-open . 0)); +# indent-tabs-mode: nil; +# End: +# +# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: trunk/platforms/tsar_generic_iob/genmap.py =================================================================== --- trunk/platforms/tsar_generic_iob/genmap.py (revision 710) +++ (revision ) @@ -1,316 +1,0 @@ -#!/usr/bin/env python - -from mapping import * - -####################################################################################### -# file : genmap.py -# date : may 2014 -# author : Alain Greiner -####################################################################################### -# This file contains a mapping generator for the "tsar_generic_iob" platform. -# This includes both the hardware architecture (clusters, processors, peripherals, -# physical space segmentation) and the mapping of all kernel objects (global vsegs). -# This platform includes 6 external peripherals, accessible through two IO_Bridge -# components located in cluster [0,0] and cluster [x_size-1, y_size-1]. -# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. -# The parameters are: -# - x_size : number of clusters in a row -# - y_size : number of clusters in a column -# - procs_max : number of processors per cluster -# - nb_ttys : number of TTY channels -# - nb_nics : number of NIC channels -# - fbf_size : frame_buffer width = frame_buffer heigth -# - x_io : cluster_io x coordinate -# - y_io : cluster_io y coordinate -#################################################################################### - -########################## -def genmap( x_size = 2, - y_size = 2, - nb_procs = 2, - nb_ttys = 1, - nb_nics = 2, - fbf_width = 128, - x_io = 0, - y_io = 0 ): - - ### parameters checking - assert( nb_procs <= 4 ) - - assert( (x_size == 1) or (x_size == 2) or (x_size == 4) - or (y_size == 8) or (x_size == 16) ) - - assert( (y_size == 1) or (y_size == 2) or (y_size == 4) - or (y_size == 8) or (y_size == 16) ) - - assert( nb_ttys <= 2 ) - - assert( ((x_io == 0) and (y_io == 0)) or - ((x_io == x_size-1) and (y_io == y_size-1)) ) - - ### define architecture constants - - platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) - x_width = 4 - y_width = 4 - paddr_width = 40 - irq_per_proc = 4 - use_ramdisk = False - - ### define physical segments - - ram_base = 0x0000000000 - ram_size = 0x4000000 # 64 Mbytes - - xcu_base = 0x00B0000000 - xcu_size = 0x1000 # 4 Kbytes - - dma_base = 0x00B1000000 - dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs - - mmc_base = 0x00B2000000 - mmc_size = 0x1000 # 4 Kbytes - - offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) - - bdv_base = 0x00B3000000 + offset_io - bdv_size = 0x1000 # 4kbytes - - tty_base = 0x00B4000000 + offset_io - tty_size = 0x4000 # 16 Kbytes - - nic_base = 0x00B5000000 + offset_io - nic_size = 0x80000 # 512 kbytes - - cma_base = 0x00B6000000 + offset_io - cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics - - fbf_base = 0x00B7000000 + offset_io - fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes - - pic_base = 0x00B8000000 + offset_io - pic_size = 0x1000 # 4 Kbytes - - iob_base = 0x00BE000000 + offset_io - iob_size = 0x1000 # 4kbytes - - rom_base = 0x00BFC00000 + offset_io - rom_size = 0x4000 # 16 Kbytes - - ### define bootloader vsegs base addresses - - boot_mapping_vbase = 0x00000000 # ident - boot_mapping_size = 0x00010000 # 64 Kbytes - - boot_code_vbase = 0x00010000 # ident - boot_code_size = 0x00020000 # 128 Kbytes - - boot_data_vbase = 0x00030000 # ident - boot_data_size = 0x00010000 # 64 Kbytes - - boot_buffer_vbase = 0x00040000 # ident - boot_buffer_size = 0x00060000 # 384 Kbytes - - boot_stack_vbase = 0x000A0000 # ident - boot_stack_size = 0x00050000 # 320 Kbytes - - ### define kernel vsegs base addresses - - kernel_code_vbase = 0x80000000 - kernel_code_size = 0x00020000 # 128 Kbytes - - kernel_data_vbase = 0x80020000 - kernel_data_size = 0x00060000 # 384 Kbytes - - kernel_uncdata_vbase = 0x80080000 - kernel_uncdata_size = 0x00040000 # 256 Kbytes - - kernel_init_vbase = 0x800C0000 - kernel_init_size = 0x00010000 # 64 Kbytes - - kernel_sched_vbase = 0xF0000000 # distributed in all clusters - kernel_sched_size = 0x1000 * nb_procs # 4 kbytes per processor - - ### create mapping - - mapping = Mapping( name = platform_name, - x_size = x_size, - y_size = y_size, - procs_max = nb_procs, - x_width = x_width, - y_width = y_width, - paddr_width = paddr_width, - coherence = True, - irq_per_proc = irq_per_proc, - use_ramdisk = use_ramdisk, - x_io = x_io, - y_io = y_io ) - - ### external peripherals (accessible in cluster[0,0] only for this mapping) - - iob = mapping.addPeriph( 'IOB', base = iob_base, size = iob_size, ptype = 'IOB' ) - - bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, ptype = 'IOC', subtype = 'BDV' ) - - tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) - - nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) - - cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) - - fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = 128 ) - - rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' ) - - pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) - - mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 ) - mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 ) - - mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 ) - mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 ) - - mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 ) - mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 ) - mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 ) - mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 ) - - mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 ) - - mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) - - ### hardware components replicated in all clusters - - for x in xrange( x_size ): - for y in xrange( y_size ): - cluster_xy = (x << y_width) + y; - offset = cluster_xy << (paddr_width - x_width - y_width) - - ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) - - mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, - ptype = 'MMC' ) - - dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, - ptype = 'DMA', channels = nb_procs ) - - xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, - ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) - - # DMA IRQs replicated in all clusters - for p in xrange( nb_procs ): - mapping.addIrq( xcu, index = (p+1), isrtype = 'ISR_DMA', channel = p ) - - # MMC IRQ replicated in all clusters - mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) - - # processors - for p in xrange ( nb_procs ): - mapping.addProc( x, y, p ) - - ### global vsegs for boot_loader / identity mapping - - mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', - vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) - - mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', - vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) - - mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', - vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) - - mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', - vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) - - mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', - vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) - - ### global vsegs for kernel - - mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', - vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) - - mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', - vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) - - mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', - vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) - - mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', - vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) - - ### global vsegs for external peripherals / identity mapping - - mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) - - mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) - - mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) - - mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) - - mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) - - mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) - - mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) - - mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', - vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True ) - - ### Global vsegs for replicated peripherals, and for scheduler. - ### A replicated vseg is replicated in all clusters: vseg name is indexed by (x,y), - ### and vseg base address is incremented by (cluster_xy * 0x10000) - - mapping.addGlobal( 'seg_xcu' , xcu_base , xcu_size , '__W_', - vtype = 'PERI' , x = 0, y = 0, pseg = 'XCU', replicated = True ) - - mapping.addGlobal( 'seg_dma' , dma_base , dma_size , '__W_', - vtype = 'PERI' , x = 0, y = 0, pseg = 'DMA', replicated = True ) - - mapping.addGlobal( 'seg_mmc' , mmc_base , mmc_size , '__W_', - vtype = 'PERI' , x = 0, y = 0, pseg = 'MMC', replicated = True ) - - mapping.addGlobal( 'seg_sched', kernel_sched_vbase, kernel_sched_size, 'C_W_', - vtype = 'SCHED', x = 0, y = 0, pseg = 'RAM', replicated = True ) - - ### return mapping ### - - return mapping - -################################# platform test ####################################################### - -if __name__ == '__main__': - - mapping = genmap( x_size = 2, - y_size = 2, - nb_procs = 2, - nb_ttys = 1, - nb_nics = 2, - fbf_width = 128, - x_io = 0, - y_io = 0 ) - -# print mapping.netbsd_dts() - - print mapping.xml() - -# print mapping.giet_vsegs() - - -# Local Variables: -# tab-width: 4; -# c-basic-offset: 4; -# c-file-offsets:((innamespace . 0)(inline-open . 0)); -# indent-tabs-mode: nil; -# End: -# -# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 - Index: trunk/platforms/tsar_generic_iob/top.cpp =================================================================== --- trunk/platforms/tsar_generic_iob/top.cpp (revision 710) +++ trunk/platforms/tsar_generic_iob/top.cpp (revision 714) @@ -85,4 +85,7 @@ // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) // - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs // // Some secondary hardware parameters must be defined in this top.cpp file: @@ -94,7 +97,4 @@ // - L1_DWAYS // - L1_DSETS -// - FBUF_X_SIZE : width of frame buffer (pixels) -// - FBUF_Y_SIZE : heigth of frame buffer (lines) -// - BDEV_SECTOR_SIZE : block size for block drvice // - BDEV_IMAGE_NAME : file pathname for block device // - NIC_RX_NAME : file pathname for NIC received packets @@ -209,8 +209,4 @@ #define L1_DSETS 64 -#define FBUF_X_SIZE 128 -#define FBUF_Y_SIZE 128 - -#define BDEV_SECTOR_SIZE 512 #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" @@ -236,5 +232,5 @@ //////////////////////i///////////////////////////////////// -#define MAX_FROZEN_CYCLES 10000 +#define MAX_FROZEN_CYCLES 200000 ///////////////////////////////////////////////////////// @@ -383,5 +379,4 @@ size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 - size_t block_size = BDEV_SECTOR_SIZE; // disk block size size_t x_width = 4; // at most 256 clusters size_t y_width = 4; // at most 256 clusters @@ -415,7 +410,4 @@ { debug_memc_id = atoi(argv[n+1]); - -std::cout << "@@@@@@@@@@@@@@ MEMCID = " << debug_memc_id << std::endl; - size_t x = debug_memc_id >> 4; size_t y = debug_memc_id & 0xF; @@ -998,5 +990,5 @@ IntTab(0, IOX_BDEV_TGT_ID), disk_name, - block_size, + 512, // block size 64, // burst size (bytes) 0 ); // disk latency @@ -1103,4 +1095,5 @@ L1_DSETS, XRAM_LATENCY, + XCU_NB_INPUTS, loader, @@ -1150,8 +1143,4 @@ bdev->p_resetn (signal_resetn); bdev->p_irq (signal_irq_bdev); - - // For AHCI - // bdev->p_channel_irq[0] (signal_irq_bdev); - bdev->p_vci_target (signal_vci_tgt_bdev); bdev->p_vci_initiator (signal_vci_ini_bdev); @@ -1481,5 +1470,5 @@ { // stats display - if( (n % 5000000) == 0) + if( (n % 1000000) == 0) { gettimeofday(&t2, NULL); @@ -1489,5 +1478,6 @@ uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; - std::cerr << "platform clock frequency " + std::cerr << "### cycle = " << n + << " / frequency = " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; @@ -1519,5 +1509,4 @@ clusters[x][y]->proc[l]->print_trace(1); - std::ostringstream proc_signame; proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; @@ -1525,8 +1514,12 @@ clusters[x][y]->xicu->print_trace(l); - std::ostringstream xicu_signame; xicu_signame << "[SIG]XICU_" << x << "_" << y; clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); + +// clusters[x][y]->mdma->print_trace(); +// std::ostringstream mdma_signame; +// mdma_signame << "[SIG]MDMA_" << x << "_" << y; +// clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); if( clusters[x][y]->signal_proc_it[l].read() ) @@ -1534,24 +1527,4 @@ << x << "_" << y << "_" << l << " ACTIVE" << std::endl; } - - // trace INT network -// clusters[0][0]->int_xbar_cmd_d->print_trace(); -// clusters[0][0]->int_xbar_rsp_d->print_trace(); - -// clusters[0][0]->signal_int_dspin_cmd_l2g_d.print_trace("[SIG] INT_CMD_L2G_D_0_0"); -// clusters[0][0]->signal_int_dspin_rsp_g2l_d.print_trace("[SIG] INT_RSP_G2L_D_0_0"); - -// clusters[0][0]->int_router_cmd->print_trace(0); -// clusters[0][0]->int_router_rsp->print_trace(0); - - // trace INT_CMD_D xbar and router in cluster 0_1 -// clusters[0][1]->int_router_cmd->print_trace(0); -// clusters[0][1]->int_router_rsp->print_trace(0); - -// clusters[0][1]->signal_int_dspin_cmd_g2l_d.print_trace("[SIG] INT_CMD_G2L_D_0_0"); -// clusters[0][1]->signal_int_dspin_rsp_l2g_d.print_trace("[SIG] INT_RSP_L2G_D_0_0"); - -// clusters[0][1]->int_xbar_cmd_d->print_trace(); -// clusters[0][1]->int_xbar_rsp_d->print_trace(); // trace memc[debug_memc_id] @@ -1619,4 +1592,7 @@ signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + mnic->print_trace(); + signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); + // fbuf->print_trace(); // signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); @@ -1628,6 +1604,10 @@ // interrupts - if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; - if (signal_irq_mtty_rx) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; + if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; + if (signal_irq_mtty_rx) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; + if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; + if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; + if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; + if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; } } Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 710) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 714) @@ -216,4 +216,5 @@ size_t l1_d_sets, size_t xram_latency, + size_t xcu_nb_inputs, const Loader &loader, // loader for XRAM Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp =================================================================== --- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 710) +++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 714) @@ -70,4 +70,5 @@ size_t l1_d_sets, size_t xram_latency, + size_t xcu_nb_inputs, const Loader &loader, @@ -183,8 +184,8 @@ mt_int, // mapping table INT network IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space - 32, // number of timer IRQs - 32, // number of hard IRQs - 32, // number of soft IRQs - 32); // number of output IRQs + xcu_nb_inputs, // number of timer IRQs + xcu_nb_inputs, // number of hard IRQs + xcu_nb_inputs, // number of soft IRQs + 16); // number of output IRQs //////////// MDMA @@ -452,15 +453,15 @@ } - int_wi_gate_d->p_clk (this->p_clk); - int_wi_gate_d->p_resetn (this->p_resetn); - int_wi_gate_d->p_vci (signal_int_vci_l2g); - int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); - int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); - - int_wt_gate_d->p_clk (this->p_clk); - int_wt_gate_d->p_resetn (this->p_resetn); - int_wt_gate_d->p_vci (signal_int_vci_g2l); - int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); - int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); + int_wi_gate_d->p_clk (this->p_clk); + int_wi_gate_d->p_resetn (this->p_resetn); + int_wi_gate_d->p_vci (signal_int_vci_l2g); + int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); + int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); + + int_wt_gate_d->p_clk (this->p_clk); + int_wt_gate_d->p_resetn (this->p_resetn); + int_wt_gate_d->p_vci (signal_int_vci_g2l); + int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); + int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); ////////////////////// M2P DSPIN local crossbar coherence @@ -512,9 +513,9 @@ xicu->p_resetn (this->p_resetn); xicu->p_vci (signal_int_vci_tgt_xicu); - for ( size_t p=0 ; p < 32 ; p++) - { - xicu->p_irq[p] (signal_proc_it[p]); - } - for ( size_t i=0 ; i<32 ; i++) + for ( size_t i=0 ; i < 16 ; i++) + { + xicu->p_irq[i] (signal_proc_it[i]); + } + for ( size_t i=0 ; i < xcu_nb_inputs ; i++) { if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);