Changeset 715 for trunk/modules/vci_io_bridge/caba/source/src
- Timestamp:
- Jun 23, 2014, 3:43:33 PM (11 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp
r713 r715 5 5 * 6 6 * SOCLIB_LGPL_HEADER_BEGIN 7 * 7 * 8 8 * This file is part of SoCLib, GNU LGPLv2.1. 9 * 9 * 10 10 * SoCLib is free software; you can redistribute it and/or modify it 11 11 * under the terms of the GNU Lesser General Public License as published 12 12 * by the Free Software Foundation; version 2.1 of the License. 13 * 13 * 14 14 * SoCLib is distributed in the hope that it will be useful, but 15 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 17 * Lesser General Public License for more details. 18 * 18 * 19 19 * You should have received a copy of the GNU Lesser General Public 20 20 * License along with SoCLib; if not, write to the Free Software 21 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 22 22 * 02110-1301 USA 23 * 23 * 24 24 * SOCLIB_LGPL_HEADER_END 25 25 */ … … 38 38 ///////////////////////////////////////////////////////////////////////////////// 39 39 40 #define DEBUG_DMA_CMD 41 #define DEBUG_DMA_RSP 42 #define DEBUG_TLB_MISS 43 #define DEBUG_CONFIG_CMD 44 #define DEBUG_CONFIG_RSP 45 #define DEBUG_MISS_WTI_CMD 46 47 namespace soclib { 40 #define DEBUG_DMA_CMD 1 41 #define DEBUG_DMA_RSP 1 42 #define DEBUG_TLB_MISS 1 43 #define DEBUG_CONFIG_CMD 1 44 #define DEBUG_CONFIG_RSP 1 45 #define DEBUG_MISS_WTI_CMD 1 46 47 namespace soclib { 48 48 namespace caba { 49 49 50 50 namespace { 51 51 52 const char *dma_cmd_fsm_state_str[] = 52 const char *dma_cmd_fsm_state_str[] = 53 53 { 54 54 "DMA_CMD_IDLE", … … 61 61 }; 62 62 63 const char *dma_rsp_fsm_state_str[] = 63 const char *dma_rsp_fsm_state_str[] = 64 64 { 65 65 "DMA_RSP_IDLE_DMA", … … 71 71 }; 72 72 73 const char *tlb_fsm_state_str[] = 73 const char *tlb_fsm_state_str[] = 74 74 { 75 75 "TLB_IDLE", … … 78 78 "TLB_PTE1_SELECT", 79 79 "TLB_PTE1_UPDT", 80 "TLB_PTE2_GET", 80 "TLB_PTE2_GET", 81 81 "TLB_PTE2_SELECT", 82 82 "TLB_PTE2_UPDT", … … 86 86 }; 87 87 88 const char *config_cmd_fsm_state_str[] = 88 const char *config_cmd_fsm_state_str[] = 89 89 { 90 90 "CONFIG_CMD_IDLE", 91 "CONFIG_CMD_NEXT", 91 "CONFIG_CMD_HI", 92 "CONFIG_CMD_LO", 92 93 "CONFIG_CMD_PUT", 93 94 "CONFIG_CMD_RSP", 94 95 }; 95 96 96 const char *config_rsp_fsm_state_str[] = 97 const char *config_rsp_fsm_state_str[] = 97 98 { 98 99 "CONFIG_RSP_IDLE_IOX", 99 100 "CONFIG_RSP_IDLE_LOC", 100 "CONFIG_RSP_PUT_LO W",101 "CONFIG_RSP_PUT_HI", 102 "CONFIG_RSP_PUT_UNC", 103 "CONFIG_RSP_PUT_LOC", 101 "CONFIG_RSP_PUT_LO", 102 "CONFIG_RSP_PUT_HI", 103 "CONFIG_RSP_PUT_UNC", 104 "CONFIG_RSP_PUT_LOC", 104 105 }; 105 106 106 const char *miss_wti_rsp_state_str[] = 107 { 107 const char *miss_wti_rsp_state_str[] = 108 { 108 109 "MISS_WTI_RSP_IDLE", 109 110 "MISS_WTI_RSP_WTI_IOX", … … 117 118 //////////////////////// 118 119 tmpl(/**/)::VciIoBridge( 119 sc_module_name name, 120 const soclib::common::MappingTable &mt_ext, 121 const soclib::common::MappingTable &mt_int, 122 const soclib::common::MappingTable &mt_iox, 123 const soclib::common::IntTab &int_tgtid, // INT network TGTID 124 const soclib::common::IntTab &int_srcid, // INT network SRCID 125 const soclib::common::IntTab &iox_tgtid, // IOX network TGTID 120 sc_module_name name, 121 const soclib::common::MappingTable &mt_ext, 122 const soclib::common::MappingTable &mt_int, 123 const soclib::common::MappingTable &mt_iox, 124 const soclib::common::IntTab &int_tgtid, // INT network TGTID 125 const soclib::common::IntTab &int_srcid, // INT network SRCID 126 const soclib::common::IntTab &iox_tgtid, // IOX network TGTID 127 const soclib::common::IntTab &iox_srcid, // IOX network SRCID 126 128 const size_t dcache_words, 127 const size_t 128 const size_t 129 const uint32_t 130 const bool 129 const size_t iotlb_ways, 130 const size_t iotlb_sets, 131 const uint32_t debug_start_cycle, 132 const bool debug_ok) 131 133 : soclib::caba::BaseModule(name), 132 134 … … 143 145 // INT & IOX Network 144 146 m_int_seglist( mt_int.getSegmentList( int_tgtid )), 145 m_int_srcid( mt_int.indexForId( int_srcid )), 147 m_int_srcid( mt_int.indexForId( int_srcid )), 146 148 m_iox_seglist( mt_iox.getSegmentList( iox_tgtid )), 149 m_iox_srcid( mt_iox.indexForId( iox_srcid )), 150 151 m_srcid_gid_mask( mt_int.getSrcidLevelBits()[0], // use global bits 152 mt_int.getSrcidLevelBits()[1]), // drop local bits 153 m_srcid_lid_mask( mt_int.getSrcidLevelBits()[1], // use local bits 154 0), 147 155 148 156 m_iotlb_ways(iotlb_ways), … … 176 184 r_dma_cmd_to_dma_rsp_rtrdid("r_dma_cmd_to_dma_rsp_rtrdid"), 177 185 r_dma_cmd_to_dma_rsp_rpktid("r_dma_cmd_to_dma_rsp_rpktid"), 178 186 179 187 r_dma_cmd_to_tlb_req("r_dma_cmd_to_tlb_req"), 180 188 r_dma_cmd_to_tlb_vaddr("r_dma_cmd_to_tlb_vaddr"), 181 189 182 190 //DMA_RSP FSM registers 183 191 r_dma_rsp_fsm("r_dma_rsp_fsm"), 184 192 185 // CONFIG_CMD FSM registers 193 // CONFIG_CMD FSM registers 186 194 r_config_cmd_fsm("r_config_cmd_fsm"), 187 195 … … 192 200 r_config_cmd_to_config_rsp_rerror("r_config_cmd_to_config_rsp_rerror"), 193 201 r_config_cmd_to_config_rsp_rdata("r_config_cmd_to_config_rsp_rdata"), 202 r_config_cmd_to_config_rsp_rsrcid("r_config_cmd_to_config_rsp_rsrcid"), 203 r_config_cmd_to_config_rsp_rtrdid("r_config_cmd_to_config_rsp_rtrdid"), 204 r_config_cmd_to_config_rsp_rpktid("r_config_cmd_to_config_rsp_rpktid"), 194 205 195 206 r_config_cmd_wdata("r_config_cmd_wdata"), … … 198 209 r_config_cmd_address("r_config_cmd_address"), 199 210 r_config_cmd_srcid("r_config_cmd_srcid"), 211 r_config_cmd_trdid("r_config_cmd_trdid"), 200 212 r_config_cmd_pktid("r_config_cmd_pktid"), 201 r_config_cmd_trdid("r_config_cmd_trdid"),202 213 r_config_cmd_plen("r_config_cmd_plen"), 203 214 r_config_cmd_clen("r_config_cmd_clen"), … … 208 219 r_config_cmd_eop("r_config_cmd_eop"), 209 220 210 // CONFIG_RSP FSM registers 221 // ID translation table used by CONFIG_CMD and CONFIG_RSP FSMs 222 m_iox_transaction_tab(1), 223 224 // CONFIG_RSP FSM registers 211 225 r_config_rsp_fsm("r_config_rsp_fsm"), 226 r_config_rsp_rsrcid("r_config_rsp_rsrcid"), 227 r_config_rsp_rtrdid("r_config_rsp_rtrdid"), 212 228 213 229 // TLB FSM registers … … 217 233 r_tlb_miss_error("r_tlb_miss_error"), 218 234 219 r_tlb_paddr("r_tlb_paddr"), 235 r_tlb_paddr("r_tlb_paddr"), 220 236 r_tlb_pte_flags("r_tlb_pte_flags"), 221 237 r_tlb_pte_ppn("r_tlb_pte_ppn"), 222 238 r_tlb_way("r_tlb_way"), 223 r_tlb_set("r_tlb_set"), 224 239 r_tlb_set("r_tlb_set"), 240 225 241 r_tlb_buf_valid("r_tlb_buf_valid"), 226 242 r_tlb_buf_tag("r_tlb_buf_tag"), … … 231 247 232 248 // MISS_WTI_RSP FSM registers 233 r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), 249 r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), 234 250 r_miss_wti_rsp_error_wti("r_miss_wti_rsp_error_wti"), 235 251 r_miss_wti_rsp_error_miss("r_miss_wti_rsp_error_miss"), … … 244 260 // TLB for IOMMU 245 261 r_iotlb("iotlb", 0, iotlb_ways, iotlb_sets, vci_param_int::N), 246 262 247 263 // DMA_CMD FIFOs 248 264 m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",2), 249 m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",2), 250 m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",2), 251 m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",2), 252 m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",2), 253 m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",2), 254 m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",2), 255 m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",2), 265 m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",2), 266 m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",2), 267 m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",2), 268 m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",2), 269 m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",2), 270 m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",2), 271 m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",2), 256 272 m_dma_cmd_eop_fifo("m_dma_cmd_eop_fifo",2), 257 m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",2), 258 m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",2), 259 m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",2), 273 m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",2), 274 m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",2), 275 m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",2), 260 276 m_dma_cmd_cfixed_fifo("m_dma_cmd_cfixed_fifo",2), 261 m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",2), 277 m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",2), 262 278 263 279 // DMA_RSP FIFOs … … 268 284 m_dma_rsp_reop_fifo("m_dma_rsp_reop_fifo",2), 269 285 m_dma_rsp_rerror_fifo("m_dma_rsp_rerror_fifo",2), 270 286 271 287 // CONFIG_CMD FIFOs 272 288 m_config_cmd_addr_fifo("m_config_cmd_addr_fifo",2), … … 286 302 287 303 // CONFIG_RSP FIFOs 288 m_config_rsp_data_fifo("m_config_rsp_data_fifo",2), 304 m_config_rsp_data_fifo("m_config_rsp_data_fifo",2), 289 305 m_config_rsp_rsrcid_fifo("m_config_rsp_rsrcid_fifo",2), 290 306 m_config_rsp_rtrdid_fifo("m_config_rsp_rtrdid_fifo",2), … … 311 327 std::cout << " - Building VciIoBridge : " << name << std::endl; 312 328 313 // checking segments on INT network 329 // checking segments on INT network 314 330 assert ( ( not m_int_seglist.empty() ) and 315 331 "VCI_IO_BRIDGE ERROR : no segment allocated on INT network"); … … 320 336 std::cout << " => segment " << int_seg->name() 321 337 << " / base = " << std::hex << int_seg->baseAddress() 322 << " / size = " << int_seg->size() 323 << " / special = " << int_seg->special() << std::endl; 324 } 325 326 // checking segments on IOX network 338 << " / size = " << int_seg->size() 339 << " / special = " << int_seg->special() << std::endl; 340 } 341 342 // checking segments on IOX network 327 343 assert ( ( not m_iox_seglist.empty() ) and 328 344 "VCI_IO_BRIDGE ERROR : no segment allocated on IOX network"); … … 333 349 std::cout << " => segment " << iox_seg->name() 334 350 << " / base = " << std::hex << iox_seg->baseAddress() 335 << " / size = " << iox_seg->size() << std::endl; 336 } 337 338 assert( (vci_param_int::N == vci_param_ext::N) and 351 << " / size = " << iox_seg->size() << std::endl; 352 } 353 354 assert( (vci_param_int::N == vci_param_ext::N) and 339 355 "VCI_IO_BRIDGE ERROR: VCI ADDRESS widths must be equal on the 3 networks"); 340 356 … … 343 359 344 360 assert( (vci_param_int::B == 4) and 345 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 bits on internal network"); 361 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 bits on internal network"); 346 362 347 363 assert( (vci_param_ext::B == 8) and 348 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 64 bits on external network"); 364 "VCI_IO_BRIDGE ERROR: VCI DATA width must be 64 bits on external network"); 349 365 350 366 assert( (vci_param_int::S == vci_param_ext::S) and … … 357 373 dont_initialize(); 358 374 sensitive << p_clk.pos(); 359 375 360 376 SC_METHOD(genMoore); 361 377 dont_initialize(); … … 392 408 r_iotlb.printTrace(); 393 409 } 410 411 if(mode & 0x02) 412 { 413 std::cout << " IOX TRANSACTION TAB" << std::endl; 414 m_iox_transaction_tab.printTrace(); 415 } 394 416 } 395 417 … … 398 420 //////////////////////// 399 421 { 400 std::cout << name() << std::endl 401 << "- IOTLB MISS RATE = " << (float)m_cpt_iotlb_miss/m_cpt_iotlb_read << std::endl 402 << "- IOTLB MISS COST = " << (float)m_cost_iotlb_miss/m_cpt_iotlb_miss << std::endl 403 << "- IOTLB MISS TRANSACTION COST = " << (float)m_cost_iotlbmiss_transaction/m_cpt_iotlbmiss_transaction << std::endl 404 << "- IOTLB MISS TRANSACTION RATE (OVER ALL MISSES) = " << (float)m_cpt_iotlbmiss_transaction/m_cpt_iotlb_miss << std::endl; 422 std::cout << name() 423 << "\n- IOTLB MISS RATE = " 424 << (float)m_cpt_iotlb_miss/m_cpt_iotlb_read 425 << "\n- IOTLB MISS COST = " 426 << (float)m_cost_iotlb_miss/m_cpt_iotlb_miss 427 << "\n- IOTLB MISS TRANSACTION COST = " 428 << (float)m_cost_iotlbmiss_transaction/m_cpt_iotlbmiss_transaction 429 << "\n- IOTLB MISS TRANSACTION RATE (OVER ALL MISSES) = " 430 << (float)m_cpt_iotlbmiss_transaction/m_cpt_iotlb_miss 431 << std::endl; 405 432 } 406 433 … … 409 436 //////////////////////// 410 437 { 411 m_cpt_iotlb_read = 0; 412 m_cpt_iotlb_miss = 0; 438 m_cpt_iotlb_read = 0; 439 m_cpt_iotlb_miss = 0; 413 440 m_cost_iotlb_miss = 0; 414 m_cpt_iotlbmiss_transaction = 0; 415 m_cost_iotlbmiss_transaction = 0; 441 m_cpt_iotlbmiss_transaction = 0; 442 m_cost_iotlbmiss_transaction = 0; 416 443 } 417 444 … … 420 447 //////////////////////////////////// 421 448 { 422 uint32_t addr32 = (uint32_t)paddr; 423 uint32_t base = r_xicu_base.read(); 424 uint32_t size = r_xicu_size.read(); 425 return ( (addr32 >= base) and (addr32 < (base + size)) ); 449 std::list<soclib::common::Segment>::iterator seg; 450 for ( seg = m_iox_seglist.begin() ; 451 seg != m_iox_seglist.end() ; 452 seg++ ) 453 { 454 if ( seg->contains(paddr) ) return seg->special(); 455 } 456 return false; 426 457 } 427 458 … … 430 461 ///////////////////////// 431 462 { 432 if ( not p_resetn.read() ) 433 { 434 r_dma_cmd_fsm 435 r_dma_rsp_fsm 436 r_tlb_fsm 463 if ( not p_resetn.read() ) 464 { 465 r_dma_cmd_fsm = DMA_CMD_IDLE; 466 r_dma_rsp_fsm = DMA_RSP_IDLE_DMA; 467 r_tlb_fsm = TLB_IDLE; 437 468 r_config_cmd_fsm = CONFIG_CMD_IDLE; 438 469 r_config_rsp_fsm = CONFIG_RSP_IDLE_IOX; 439 470 r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; 440 471 441 r_tlb_buf_valid = false; 442 443 444 445 r_xicu_size = 0;446 r_xicu_base = 0;472 r_tlb_buf_valid = false; 473 r_iommu_active = false; 474 r_iommu_wti_enable = false; 475 476 // initializing translation table 477 m_iox_transaction_tab.init(); 447 478 448 479 // initializing FIFOs … … 461 492 m_dma_cmd_cfixed_fifo.init(); 462 493 m_dma_cmd_clen_fifo.init(); 463 494 464 495 m_dma_rsp_rsrcid_fifo.init(); 465 496 m_dma_rsp_rtrdid_fifo.init(); … … 468 499 m_dma_rsp_rerror_fifo.init(); 469 500 m_dma_rsp_reop_fifo.init(); 470 501 471 502 m_config_cmd_addr_fifo.init(); 472 503 m_config_cmd_srcid_fifo.init(); … … 483 514 m_config_cmd_cfixed_fifo.init(); 484 515 m_config_cmd_clen_fifo.init(); 485 516 486 517 m_miss_wti_cmd_addr_fifo.init(); 487 518 m_miss_wti_cmd_srcid_fifo.init(); … … 498 529 m_miss_wti_cmd_cfixed_fifo.init(); 499 530 m_miss_wti_cmd_clen_fifo.init(); 500 531 501 532 m_config_rsp_rsrcid_fifo.init(); 502 533 m_config_rsp_rtrdid_fifo.init(); … … 505 536 m_config_rsp_rerror_fifo.init(); 506 537 m_config_rsp_reop_fifo.init(); 507 508 // SET/RESET Communication flip-flops 538 539 // SET/RESET Communication flip-flops 509 540 r_dma_cmd_to_miss_wti_cmd_req = false; 510 541 r_dma_cmd_to_dma_rsp_req = false; 511 r_dma_cmd_to_tlb_req 512 r_config_cmd_to_tlb_req 542 r_dma_cmd_to_tlb_req = false; 543 r_config_cmd_to_tlb_req = false; 513 544 r_config_cmd_to_config_rsp_req = false; 514 545 r_tlb_to_miss_wti_cmd_req = false; … … 520 551 521 552 // Debug variable 522 m_debug_activated= false;523 524 525 526 m_cpt_iotlb_read = 0; 527 m_cpt_iotlb_miss = 0; 528 m_cpt_iotlbmiss_transaction = 0; 529 m_cost_iotlbmiss_transaction = 0; 530 553 m_debug_activated = false; 554 555 // activity counters 556 m_cpt_total_cycles = 0; 557 m_cpt_iotlb_read = 0; 558 m_cpt_iotlb_miss = 0; 559 m_cpt_iotlbmiss_transaction = 0; 560 m_cost_iotlbmiss_transaction = 0; 561 531 562 m_cpt_trt_dma_full = 0; 532 563 m_cpt_trt_dma_full_cost = 0; … … 547 578 bool dma_cmd_fifo_put = false; 548 579 bool dma_cmd_fifo_get = p_vci_ini_ram.cmdack.read(); 549 550 bool dma_rsp_fifo_put = false; 580 vci_srcid_t dma_cmd_fifo_srcid = 0; 581 582 bool dma_rsp_fifo_put = false; 551 583 bool dma_rsp_fifo_get = p_vci_tgt_iox.rspack.read(); 552 584 vci_rerror_t dma_rsp_fifo_rerror = 0; … … 579 611 580 612 #ifdef INSTRUMENTATION 581 m_cpt_fsm_dma_cmd 582 m_cpt_fsm_dma_rsp 583 m_cpt_fsm_tlb 584 m_cpt_fsm_config_cmd 585 m_cpt_fsm_config_rsp 613 m_cpt_fsm_dma_cmd [r_dma_cmd_fsm.read()] ++; 614 m_cpt_fsm_dma_rsp [r_dma_rsp_fsm.read() ] ++; 615 m_cpt_fsm_tlb [r_tlb_fsm.read() ] ++; 616 m_cpt_fsm_config_cmd [r_config_cmd_fsm.read() ] ++; 617 m_cpt_fsm_config_rsp [r_config_rsp_fsm.read() ] ++; 586 618 m_cpt_fsm_miss_wti_rsp [r_miss_wti_rsp_fsm.read() ] ++; 587 619 #endif … … 607 639 /////////////////////////////////////////////////////////////////////////////// 608 640 609 switch( r_dma_cmd_fsm.read() ) 641 switch( r_dma_cmd_fsm.read() ) 610 642 { 611 643 ////////////////// … … 614 646 // no VCI flit is consumed in this state 615 647 { 616 if ( p_vci_tgt_iox.cmdval.read() ) 617 { 618 if ( not r_iommu_active.read() ) // tlb not activated648 if ( p_vci_tgt_iox.cmdval.read() ) 649 { 650 if ( not r_iommu_active.read() ) // tlb not activated 619 651 { 620 652 // save paddr address … … 625 657 if ( is_wti( p_vci_tgt_iox.address.read() ) ) 626 658 { 627 assert( p_vci_tgt_iox.eop.read() and 659 assert( p_vci_tgt_iox.eop.read() and 628 660 "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); 629 661 … … 637 669 #if DEBUG_DMA_CMD 638 670 if( m_debug_activated ) 639 std::cout << " <IOB DMA_CMD_IDLE> DMA command" 671 std::cout << name() 672 << " <IOB DMA_CMD_IDLE> DMA command" 640 673 << " : address = " << std::hex << p_vci_tgt_iox.address.read() 641 674 << " / srcid = " << p_vci_tgt_iox.srcid.read() … … 646 679 } 647 680 else if (r_tlb_fsm.read() == TLB_IDLE || 648 r_tlb_fsm.read() == TLB_WAIT ) 649 { 650 vci_addr_t 651 pte_info_t iotlb_flags; 652 size_t iotlb_way; 681 r_tlb_fsm.read() == TLB_WAIT ) // tlb access possible 682 { 683 vci_addr_t iotlb_paddr; 684 pte_info_t iotlb_flags; 685 size_t iotlb_way; 653 686 size_t iotlb_set; 654 687 vci_addr_t iotlb_nline; 655 bool iotlb_hit;688 bool iotlb_hit; 656 689 657 690 #ifdef INSTRUMENTATION … … 662 695 &iotlb_flags, 663 696 &iotlb_nline, // unused 664 &iotlb_way, 697 &iotlb_way, // unused 665 698 &iotlb_set ); // unused 666 667 if ( iotlb_hit ) 668 { 669 if ( not iotlb_flags.w and // access right violation 670 (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) 699 700 if ( iotlb_hit ) // tlb hit 701 { 702 if ( not iotlb_flags.w and // access right violation 703 (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) 671 704 { 672 705 // register error 673 r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; 706 r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; 674 707 r_iommu_bvar = p_vci_tgt_iox.address.read(); 675 708 r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); 676 709 677 710 // prepare response error request to DMA_RSP FSM 678 711 r_dma_cmd_to_dma_rsp_rsrcid = p_vci_tgt_iox.srcid.read(); … … 684 717 #if DEBUG_DMA_CMD 685 718 if( m_debug_activated ) 686 std::cout << " <IOB DMA_CMD_IDLE> TLB HIT but writable violation" << std::endl; 719 std::cout << name() 720 << " <IOB DMA_CMD_IDLE> TLB HIT but writable violation" << std::endl; 687 721 #endif 688 722 } … … 691 725 #if DEBUG_DMA_CMD 692 726 if( m_debug_activated ) 693 std::cout << " <IOB DMA_CMD_IDLE> TLB HIT" << std::endl; 727 std::cout << name() 728 << " <IOB DMA_CMD_IDLE> TLB HIT" << std::endl; 694 729 #endif 695 730 // save paddr address … … 699 734 if ( is_wti( iotlb_paddr ) ) 700 735 { 701 assert( p_vci_tgt_iox.eop.read() and 736 assert( p_vci_tgt_iox.eop.read() and 702 737 (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and 703 738 "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); 704 739 705 r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ;740 r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ; 706 741 } 707 742 else … … 717 752 m_cpt_iotlb_miss++; 718 753 #endif 719 // register virtual address, and send request to TLB FSM 720 754 // register virtual address, and send request to TLB FSM 755 r_dma_cmd_to_tlb_vaddr = p_vci_tgt_iox.address.read(); 721 756 r_dma_cmd_to_tlb_req = true; 722 757 r_dma_cmd_fsm = DMA_CMD_TLB_MISS_WAIT; 723 758 #if DEBUG_DMA_CMD 724 759 if( m_debug_activated ) 725 std::cout << " <IOB DMA_CMD_IDLE> TLB MISS" << std::endl; 726 #endif 727 } // end tlb miss 760 std::cout << name() 761 << " <IOB DMA_CMD_IDLE> TLB MISS" << std::endl; 762 #endif 763 } // end tlb miss 728 764 } // end if tlb_activated 729 765 } // end if cmdval … … 732 768 ///////////////////// 733 769 case DMA_CMD_DMA_REQ: // put a flit in DMA_CMD FIFO 734 // if contig, VCI address must be incremented 770 // if contig, VCI address must be incremented 735 771 // after initial translation by IOMMU. 736 772 // flit is consumed if DMA_CMD FIFO not full 737 773 { 738 if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) 739 { 740 dma_cmd_fifo_put = true; 741 742 if ( p_vci_tgt_iox.contig.read() ) r_dma_cmd_paddr = r_dma_cmd_paddr.read() + 743 vci_param_ext::B; 744 745 if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_IDLE; 746 774 if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) 775 { 776 // SRCID in RAM network is the concatenation of the IO bridge 777 // cluster id with the DMA peripheral local id 778 assert((m_srcid_gid_mask[p_vci_tgt_iox.srcid.read()] == 0) && 779 "error: external DMA peripherals global id must be 0"); 780 781 dma_cmd_fifo_srcid = (m_srcid_gid_mask.mask() & m_int_srcid) | 782 p_vci_tgt_iox.srcid.read(); 783 dma_cmd_fifo_put = true; 784 785 if ( p_vci_tgt_iox.contig.read() ) 786 { 787 r_dma_cmd_paddr = r_dma_cmd_paddr.read() + vci_param_ext::B; 788 } 789 790 if ( p_vci_tgt_iox.eop.read() ) 791 { 792 r_dma_cmd_fsm = DMA_CMD_IDLE; 793 } 794 747 795 #if DEBUG_DMA_CMD 748 if( m_debug_activated ) 749 std::cout << " <IOB DMA_CMD_FIFO_PUT_CMD> Push into DMA_CMD fifo:" 796 if( m_debug_activated ) 797 std::cout << name() 798 << " <IOB DMA_CMD_FIFO_PUT_CMD> Push into DMA_CMD fifo:" 750 799 << " address = " << std::hex << r_dma_cmd_paddr.read() 751 << " srcid = " << p_vci_tgt_iox.srcid.read()800 << " srcid = " << dma_cmd_fifo_srcid 752 801 << " wdata = " << p_vci_tgt_iox.wdata.read() 753 802 << " plen = " << std::dec << p_vci_tgt_iox.plen.read() … … 758 807 } 759 808 ///////////////////////// 760 case DMA_CMD_WTI_IOX_REQ: // post a WTI_IOX request to MISS_WTI FSM 809 case DMA_CMD_WTI_IOX_REQ: // post a WTI_IOX request to MISS_WTI FSM 761 810 // if no prending previous request 762 // command arguments are stored in dedicated registers 811 // command arguments are stored in dedicated registers 763 812 // VCI flit is consumed if no previous request 764 813 { 765 814 if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no previous pending request 766 815 { 816 // SRCID in INT network for WTI transactions is the concatenation 817 // of the IO bridge cluster id with the DMA peripheral local id 818 assert((m_srcid_gid_mask[p_vci_tgt_iox.srcid.read()] == 0) && 819 "error: external DMA peripherals global id must be 0"); 820 821 vci_srcid_t wti_srcid = (m_srcid_gid_mask.mask() & m_int_srcid) | 822 p_vci_tgt_iox.srcid.read(); 823 767 824 r_dma_cmd_to_miss_wti_cmd_req = true; 768 825 r_dma_cmd_to_miss_wti_cmd_addr = p_vci_tgt_iox.address.read(); 769 826 r_dma_cmd_to_miss_wti_cmd_cmd = p_vci_tgt_iox.cmd.read(); 770 827 r_dma_cmd_to_miss_wti_cmd_wdata = (uint32_t)p_vci_tgt_iox.wdata.read(); 771 r_dma_cmd_to_miss_wti_cmd_srcid = p_vci_tgt_iox.srcid.read();828 r_dma_cmd_to_miss_wti_cmd_srcid = wti_srcid; 772 829 r_dma_cmd_to_miss_wti_cmd_trdid = p_vci_tgt_iox.trdid.read(); 773 830 r_dma_cmd_to_miss_wti_cmd_pktid = PKTID_WTI_IOX; 774 831 775 832 r_dma_cmd_fsm = DMA_CMD_IDLE; 776 833 777 834 #if DEBUG_DMA_CMD 778 if( m_debug_activated ) 779 std::cout << " <IOB DMA_CMD_WTI_IOX_REQ> request WTI transaction from ext peripheral" 835 if( m_debug_activated ) 836 std::cout << name() 837 << " <IOB DMA_CMD_WTI_IOX_REQ> request WTI transaction from ext peripheral" 780 838 << " : address = " << std::hex << r_dma_cmd_paddr.read() 781 << " / srcid = " << p_vci_tgt_iox.srcid.read()839 << " / srcid = " << wti_srcid 782 840 << " / wdata = " << p_vci_tgt_iox.wdata.read() << std::endl; 783 841 #endif … … 786 844 } 787 845 ////////////////////////// 788 case DMA_CMD_ERR_WAIT_EOP: 846 case DMA_CMD_ERR_WAIT_EOP: // wait EOP before requesting WTI & error response 789 847 // VCI flit is always consumed 790 848 { … … 792 850 793 851 #if DEBUG_DMA_CMD 794 if( m_debug_activated ) 795 std::cout << " <IOB DMA_CMD_WAIT_EOP> wait EOP for faulty DMA command" << std::endl; 796 #endif 797 break; 798 } 799 852 if( m_debug_activated ) 853 std::cout << name() 854 << " <IOB DMA_CMD_WAIT_EOP> wait EOP for faulty DMA command" << std::endl; 855 #endif 856 break; 857 } 858 800 859 ///////////////////////// 801 case DMA_CMD_ERR_WTI_REQ: 860 case DMA_CMD_ERR_WTI_REQ: // post a WTI_MMU request to MISS_WTI_CMD FSM 802 861 // if no prending previous request 803 862 // response arguments are stored in dedicated registers 804 // no VCI flit is consumed 863 // no VCI flit is consumed 805 864 { 806 865 if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no pending previous request … … 817 876 818 877 #if DEBUG_DMA_CMD 819 if( m_debug_activated ) 820 std::cout << " <IOB DMA_CMD_ERR_WTI_REQ> request an IOMMU WTI" << std::endl; 878 if( m_debug_activated ) 879 std::cout << name() 880 << " <IOB DMA_CMD_ERR_WTI_REQ> request an IOMMU WTI" << std::endl; 821 881 #endif 822 882 } … … 827 887 // if no prending previous request 828 888 // response arguments are stored in dedicated registers 829 // no VCI flit is consumed 889 // no VCI flit is consumed 830 890 { 831 891 if ( not r_dma_cmd_to_dma_rsp_req.read() ) // no pending previous request … … 839 899 /////////////////////////// 840 900 case DMA_CMD_TLB_MISS_WAIT: // waiting completion of a TLB miss 841 // we must test a possible page fault error... 901 // we must test a possible page fault error... 842 902 { 843 903 if ( not r_dma_cmd_to_tlb_req.read() ) // TLB miss completed … … 845 905 if ( r_tlb_miss_error.read() ) // Error reported by TLB FSM 846 906 { 847 r_iommu_etr = MMU_READ_PT2_UNMAPPED; 907 r_iommu_etr = MMU_READ_PT2_UNMAPPED; 848 908 r_iommu_bvar = r_dma_cmd_to_tlb_vaddr.read(); 849 909 r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); … … 872 932 if ( m_dma_rsp_rerror_fifo.wok() ) 873 933 { 874 switch( r_dma_rsp_fsm.read() ) 934 switch( r_dma_rsp_fsm.read() ) 875 935 { 876 936 ////////////////////// 877 937 case DMA_RSP_IDLE_DMA: // normal DMA response has highest priority 878 { 938 { 879 939 if (p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; 880 940 else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; … … 884 944 ////////////////////// 885 945 case DMA_RSP_IDLE_WTI: // normal WTI response has highest priority 886 { 887 if (r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; 946 { 947 if (r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; 888 948 else if(r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; 889 949 else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; … … 892 952 ////////////////////// 893 953 case DMA_RSP_IDLE_ERR: // error response has highest priority 894 { 954 { 895 955 if (r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; 896 956 else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; 897 else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; 957 else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; 898 958 break; 899 959 } 900 960 /////////////////////// 901 961 case DMA_RSP_PUT_DMA: // put one flit of the DMA response into FIFO 902 { 962 { 903 963 dma_rsp_fifo_put = true; 904 964 dma_rsp_fifo_rerror = p_vci_ini_ram.rerror.read(); 905 965 dma_rsp_fifo_rdata = p_vci_ini_ram.rdata.read(); 906 dma_rsp_fifo_rsrcid = p_vci_ini_ram.rsrcid.read();966 dma_rsp_fifo_rsrcid = m_srcid_lid_mask[p_vci_ini_ram.rsrcid.read()]; 907 967 dma_rsp_fifo_rtrdid = p_vci_ini_ram.rtrdid.read(); 908 968 dma_rsp_fifo_rpktid = p_vci_ini_ram.rpktid.read(); … … 913 973 914 974 #if DEBUG_DMA_RSP 915 if( m_debug_activated ) 916 std::cout << " <IOB DMA_RSP_PUT_DMA> Push DMA response into DMA_RSP FIFO" 917 << " : rsrcid = " << std::hex << p_vci_ini_ram.rsrcid.read() 975 if( m_debug_activated ) 976 std::cout << name() 977 << " <IOB DMA_RSP_PUT_DMA> Push DMA response into DMA_RSP FIFO" 978 << std::hex 979 << " : rsrcid = " << m_srcid_lid_mask[p_vci_ini_ram.rsrcid.read()] 918 980 << " / rtrdid = " << p_vci_ini_ram.rtrdid.read() 919 981 << " / rpktid = " << p_vci_ini_ram.rpktid.read() … … 923 985 #endif 924 986 break; 925 987 } 926 988 /////////////////////// 927 989 case DMA_RSP_PUT_WTI: // put single flit WTI response into FIFO 928 { 990 { 929 991 dma_rsp_fifo_put = true; 930 992 dma_rsp_fifo_rerror = r_miss_wti_rsp_to_dma_rsp_rerror.read(); 931 993 dma_rsp_fifo_rdata = 0; 932 dma_rsp_fifo_rsrcid = r_miss_wti_rsp_to_dma_rsp_rsrcid.read(); 994 dma_rsp_fifo_rsrcid = 995 m_srcid_lid_mask[r_miss_wti_rsp_to_dma_rsp_rsrcid.read()]; 933 996 dma_rsp_fifo_rtrdid = r_miss_wti_rsp_to_dma_rsp_rtrdid.read(); 934 997 dma_rsp_fifo_rpktid = r_miss_wti_rsp_to_dma_rsp_rpktid.read(); … … 937 1000 // acknowledge request 938 1001 r_miss_wti_rsp_to_dma_rsp_req = false; 939 1002 940 1003 // update priority 941 1004 r_dma_rsp_fsm = DMA_RSP_IDLE_ERR; 942 1005 943 1006 #if DEBUG_DMA_RSP 944 if( m_debug_activated ) 945 std::cout << " <IOB DMA_RSP_PUT_WTI> Push WTI response into DMA_RSP FIFO" 946 << " : rsrcid = " << std::hex << r_miss_wti_rsp_to_dma_rsp_rsrcid.read() 1007 if( m_debug_activated ) 1008 std::cout << name() 1009 << " <IOB DMA_RSP_PUT_WTI> Push WTI response into DMA_RSP FIFO" 1010 << std::hex 1011 << " : rsrcid = " << m_srcid_lid_mask[r_miss_wti_rsp_to_dma_rsp_rsrcid.read()] 947 1012 << " / rtrdid = " << r_miss_wti_rsp_to_dma_rsp_rtrdid.read() 948 1013 << " / rpktid = " << r_miss_wti_rsp_to_dma_rsp_rpktid.read() … … 966 1031 // acknowledge request 967 1032 r_dma_cmd_to_dma_rsp_req = false; 968 1033 969 1034 // update priority 970 1035 r_dma_rsp_fsm = DMA_RSP_PUT_DMA; 971 1036 972 1037 #if DEBUG_DMA_RSP 973 if( m_debug_activated ) 974 std::cout << " <IOB DMA_RSP_PUT_DMA> Push IOMMU ERROR response into DMA_RSP FIFO" 1038 if( m_debug_activated ) 1039 std::cout << name() 1040 << " <IOB DMA_RSP_PUT_DMA> Push IOMMU ERROR response into DMA_RSP FIFO" 975 1041 << " : rsrcid = " << std::hex << r_dma_cmd_to_dma_rsp_rsrcid.read() 976 1042 << " / rtrdid = " << r_dma_cmd_to_dma_rsp_rtrdid.read() … … 982 1048 break; 983 1049 } 984 1050 } // end switch DMA_RSP FSM 985 1051 } // end if FIFO full 986 1052 … … 989 1055 // The TLB FSM handles the TLB miss requests from DMA_CMD FSM, 990 1056 // and the PTE inval request (from CONFIG_CMD FSM). 991 // PTE inval request have highest priority. In case of TLB miss, 1057 // PTE inval request have highest priority. In case of TLB miss, 992 1058 // this fsm searchs the requested PTE on the prefetch buffer. 993 1059 // In case of buffer miss, it request the MISS_WTI FSM to access the memory. … … 1003 1069 // PTE inval request are handled as unmaskable interrupts 1004 1070 { 1005 if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation 1071 if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation 1006 1072 { 1007 1073 r_config_cmd_to_tlb_req = false; … … 1010 1076 } 1011 1077 1012 else if ( r_dma_cmd_to_tlb_req.read() ) // request for a TLB Miss 1078 else if ( r_dma_cmd_to_tlb_req.read() ) // request for a TLB Miss 1013 1079 { 1014 1080 // Checking prefetch buffer … … 1016 1082 { 1017 1083 if( r_tlb_buf_valid && // Hit on prefetch buffer 1018 (r_tlb_buf_vaddr.read() == 1084 (r_tlb_buf_vaddr.read() == 1019 1085 (r_dma_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) 1020 1086 { 1021 size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; 1087 size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; 1022 1088 uint32_t pte_flags = r_tlb_buf_data[2*pte_offset]; 1023 uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; 1024 1089 uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; 1090 1025 1091 // Bit valid checking 1026 if ( not ( pte_flags & PTE_V_MASK) ) 1092 if ( not ( pte_flags & PTE_V_MASK) ) // unmapped 1027 1093 { 1028 std::cout << "VCI_IO_BRIDGE ERROR : " << name() 1094 std::cout << "VCI_IO_BRIDGE ERROR : " << name() 1029 1095 << " Page Table entry unmapped" << std::endl; 1030 1096 1031 1097 r_tlb_miss_error = true; 1032 1098 r_dma_cmd_to_tlb_req = false; 1033 1099 #if DEBUG_TLB_MISS 1034 1100 if ( m_debug_activated ) 1035 std::cout << " <IOB TLB_IDLE> PTE2 Unmapped" << std::hex 1101 std::cout << name() 1102 << " <IOB TLB_IDLE> PTE2 Unmapped" << std::hex 1036 1103 << " / paddr = " << r_tlb_paddr.read() 1037 1104 << " / PTE_FLAGS = " << pte_flags 1038 1105 << " / PTE_PPN = " << pte_ppn << std::endl; 1039 1106 #endif 1040 break; 1107 break; 1041 1108 } 1042 1109 1043 1110 // valid PTE2 : we must update the TLB 1044 r_tlb_pte_flags = pte_flags; 1111 r_tlb_pte_flags = pte_flags; 1045 1112 r_tlb_pte_ppn = pte_ppn; 1046 1113 r_tlb_fsm = TLB_PTE2_SELECT; 1047 1114 #if DEBUG_TLB_MISS 1048 1115 if ( m_debug_activated ) 1049 std::cout << " <IOB TLB_IDLE> Hit on prefetch buffer: PTE2" << std::hex 1050 << " / PTE_FLAGS = " << pte_flags 1116 std::cout << name() 1117 << " <IOB TLB_IDLE> Hit on prefetch buffer: PTE2" << std::hex 1118 << " / PTE_FLAGS = " << pte_flags 1051 1119 << " / PTE_PPN = " << pte_ppn << std::endl; 1052 1120 #endif 1053 break; 1121 break; 1054 1122 } 1055 1123 } … … 1057 1125 { 1058 1126 if( r_tlb_buf_valid && // Hit on prefetch buffer 1059 (r_tlb_buf_vaddr.read() == 1060 (r_dma_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) 1061 { 1062 size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; 1127 (r_tlb_buf_vaddr.read() == 1128 (r_dma_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) 1129 { 1130 size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; 1063 1131 uint32_t pte_flags = r_tlb_buf_data[pte_offset]; 1064 1132 1065 1133 // Bit valid checking 1066 if ( not ( pte_flags & PTE_V_MASK) ) 1134 if ( not ( pte_flags & PTE_V_MASK) ) // unmapped 1067 1135 { 1068 std::cout << "VCI_IO_BRIDGE ERROR : " << name() 1136 std::cout << "VCI_IO_BRIDGE ERROR : " << name() 1069 1137 << " Page Table entry unmapped" << std::endl; 1070 1138 1071 1139 r_tlb_miss_error = true; 1072 1140 r_dma_cmd_to_tlb_req = false; 1073 1141 #if DEBUG_TLB_MISS 1074 1142 if ( m_debug_activated ) 1075 std::cout << " <IOB TLB_IDLE> PTE1 Unmapped" << std::hex 1143 std::cout << name() 1144 << " <IOB TLB_IDLE> PTE1 Unmapped" << std::hex 1076 1145 << " / paddr = " << r_tlb_paddr.read() 1077 1146 << " / PTE = " << pte_flags << std::endl; 1078 1147 #endif 1079 break; 1148 break; 1080 1149 } 1081 1150 … … 1085 1154 #if DEBUG_TLB_MISS 1086 1155 if ( m_debug_activated ) 1087 std::cout << " <IOB TLB_PTE1_GET> Hit on prefetch buffer: PTE1" << std::hex 1156 std::cout << name() 1157 << " <IOB TLB_PTE1_GET> Hit on prefetch buffer: PTE1" << std::hex 1088 1158 << " / paddr = " << r_tlb_paddr.read() 1089 1159 << std::hex << " / PTE1 = " << pte_flags << std::endl; … … 1092 1162 } 1093 1163 } 1094 1164 1095 1165 // prefetch buffer miss 1096 r_tlb_fsm = TLB_MISS; 1166 r_tlb_fsm = TLB_MISS; 1097 1167 1098 1168 #if DEBUG_TLB_MISS 1099 1169 if ( m_debug_activated ) 1100 std::cout << " <IOB TLB_IDLE> Miss on prefetch buffer" 1170 std::cout << name() 1171 << " <IOB TLB_IDLE> Miss on prefetch buffer" 1101 1172 << std::hex << " / vaddr = " << r_dma_cmd_to_tlb_vaddr.read() << std::endl; 1102 1173 #endif … … 1107 1178 case TLB_MISS: // handling tlb miss 1108 1179 { 1109 uint32_t ptba = 0;1110 bool 1111 vci_addr_t 1180 uint32_t ptba = 0; 1181 bool bypass; 1182 vci_addr_t pte_paddr; 1112 1183 1113 1184 #ifdef INSTRUMENTATION … … 1116 1187 // evaluate bypass in order to skip first level page table access 1117 1188 bypass = r_iotlb.get_bypass(r_dma_cmd_to_tlb_vaddr.read(), &ptba); 1118 1119 // Request MISS_WTI_FSM a transaction on INT Network 1189 1190 // Request MISS_WTI_FSM a transaction on INT Network 1120 1191 if ( not bypass ) // Read PTE1/PTD1 in XRAM 1121 1192 { … … 1123 1194 #if DEBUG_TLB_MISS 1124 1195 if ( m_debug_activated ) 1125 std::cout << " <IOB TLB_MISS> Read PTE1/PTD1 in memory" << std::endl; 1196 std::cout << name() 1197 << " <IOB TLB_MISS> Read PTE1/PTD1 in memory" << std::endl; 1126 1198 #endif 1127 1199 pte_paddr = (vci_addr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) | 1128 1200 (vci_addr_t)((r_dma_cmd_to_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); 1129 1201 r_tlb_paddr = pte_paddr; 1130 1202 1131 1203 r_tlb_to_miss_wti_cmd_req = true; 1132 1204 r_tlb_miss_type = PTE1_MISS; … … 1138 1210 #if DEBUG_TLB_MISS 1139 1211 if ( m_debug_activated ) 1140 std::cout << " <IOB TLB_MISS> Read PTE2 in memory" << std::endl; 1212 std::cout << name() 1213 << " <IOB TLB_MISS> Read PTE2 in memory" << std::endl; 1141 1214 #endif 1142 1215 //&PTE2 = PTBA + IX2 * 8 1143 1216 pte_paddr = (vci_addr_t)ptba << PAGE_K_NBITS | 1144 1217 (vci_addr_t)(r_dma_cmd_to_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); 1145 1218 1146 1219 r_tlb_paddr = pte_paddr; 1147 1220 1148 1221 r_tlb_to_miss_wti_cmd_req = true; 1149 1222 r_tlb_miss_type = PTE2_MISS; … … 1153 1226 break; 1154 1227 } 1155 ////////////////// 1156 case TLB_PTE1_GET: 1157 { 1158 1228 ////////////////// 1229 case TLB_PTE1_GET: // Try to read a PT1 entry in the miss buffer 1230 { 1231 1159 1232 uint32_t entry; 1160 1233 1161 1234 vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); 1162 1235 size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); 1163 1236 1164 // Hit test. Just to verify. 1237 // Hit test. Just to verify. 1165 1238 // Hit must happen, since we've just finished its' miss transaction 1166 bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); 1167 assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); 1168 1239 bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); 1240 assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); 1241 1169 1242 entry = r_tlb_buf_data[word_position]; 1170 1243 1171 1244 // Bit valid checking 1172 if ( not ( entry & PTE_V_MASK) ) 1245 if ( not ( entry & PTE_V_MASK) ) // unmapped 1173 1246 { 1174 1247 //must not occur! 1175 1248 std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl 1176 1249 << "The Page Table entry ins't valid (unmapped)" << std::endl; 1177 1250 1178 1251 r_tlb_miss_error = true; 1179 1252 r_dma_cmd_to_tlb_req = false; 1180 r_tlb_fsm = TLB_IDLE; 1253 r_tlb_fsm = TLB_IDLE; 1181 1254 1182 1255 #if DEBUG_TLB_MISS 1183 1256 if ( m_debug_activated ) 1184 1257 { 1185 std::cout << " <IOB DMA_PTE1_GET> First level entry Unmapped" 1258 std::cout << name() 1259 << " <IOB DMA_PTE1_GET> First level entry Unmapped" 1186 1260 << std::hex << " / paddr = " << r_tlb_paddr.read() 1187 1261 << std::hex << " / PTE = " << entry << std::endl; 1188 1262 } 1189 1263 #endif 1190 break; 1264 break; 1191 1265 } 1192 1193 if( entry & PTE_T_MASK ) 1266 1267 if( entry & PTE_T_MASK ) // PTD : me must access PT2 1194 1268 { 1195 1269 // register bypass 1196 1270 r_iotlb.set_bypass( r_dma_cmd_to_tlb_vaddr.read(), 1197 entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), 1198 0); //nline, unused 1271 entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), 1272 0); //nline, unused 1199 1273 1200 1274 // &PTE2 = PTBA + IX2 * 8 … … 1213 1287 #if DEBUG_TLB_MISS 1214 1288 if ( m_debug_activated ) 1215 std::cout << " <IOB TLB_PTE1_GET> Success. Search PTE2" << std::hex 1289 std::cout << name() 1290 << " <IOB TLB_PTE1_GET> Success. Search PTE2" << std::hex 1216 1291 << " / PADDR = " << r_tlb_paddr.read() 1217 1292 << " / PTD = " << entry << std::endl; 1218 1293 #endif 1219 1294 } 1220 else 1295 else // PTE1 : we must update the IOTLB 1221 1296 // Should not occur if working only with small pages 1222 1297 { … … 1226 1301 #if DEBUG_TLB_MISS 1227 1302 if ( m_debug_activated ) 1228 std::cout << " <IOB TLB_PTE1_GET> Success. Big page" 1303 std::cout << name() 1304 << " <IOB TLB_PTE1_GET> Success. Big page" 1229 1305 << std::hex << " / paddr = " << r_tlb_paddr.read() 1230 1306 << std::hex << " / PTE1 = " << entry << std::endl; … … 1234 1310 } 1235 1311 ///////////////////// 1236 case TLB_PTE1_SELECT: // select a slot for PTE11237 { 1238 size_t 1239 size_t 1240 1312 case TLB_PTE1_SELECT: // select a slot for PTE1 1313 { 1314 size_t way; 1315 size_t set; 1316 1241 1317 r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), 1242 true, // PTE1 1318 true, // PTE1 1243 1319 &way, 1244 1320 &set ); … … 1249 1325 #if DEBUG_TLB_MISS 1250 1326 if ( m_debug_activated ) 1251 std::cout << " <IOB TLB_PTE1_SELECT> Select a slot in TLB" 1327 std::cout << name() 1328 << " <IOB TLB_PTE1_SELECT> Select a slot in TLB" 1252 1329 << " / way = " << std::dec << way 1253 1330 << " / set = " << set << std::endl; … … 1263 1340 { 1264 1341 uint32_t pte = r_tlb_pte_flags.read(); 1265 1342 1266 1343 r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_flags.read() & PPN1_MASK) << 21) 1267 1344 | (r_dma_cmd_to_tlb_vaddr.read()& M_PAGE_OFFSET_MASK) ); 1268 1345 1269 1346 // update TLB 1270 r_iotlb.write( true, 1347 r_iotlb.write( true, // 2M page 1271 1348 pte, 1272 0, 1273 r_dma_cmd_to_tlb_vaddr.read(), 1274 r_tlb_way.read(), 1349 0, // argument unused for a PTE1 1350 r_dma_cmd_to_tlb_vaddr.read(), 1351 r_tlb_way.read(), 1275 1352 r_tlb_set.read(), 1276 1353 0 ); //we set nline = 0 … … 1283 1360 if ( m_debug_activated ) 1284 1361 { 1285 std::cout << " <IOB TLB_PTE1_UPDT> write PTE1 in TLB" 1362 std::cout << name() 1363 << " <IOB TLB_PTE1_UPDT> write PTE1 in TLB" 1286 1364 << " / set = " << std::dec << r_tlb_set.read() 1287 1365 << " / way = " << r_tlb_way.read() << std::endl; … … 1290 1368 #endif 1291 1369 // next state 1292 r_tlb_fsm = TLB_RETURN; 1370 r_tlb_fsm = TLB_RETURN; // exit sub-fsm 1293 1371 break; 1294 1372 } 1295 1373 ////////////////// 1296 case TLB_PTE2_GET: 1297 { 1298 uint32_t 1299 uint32_t 1300 1374 case TLB_PTE2_GET: // Try to read a PTE2 (64 bits) in the miss buffer 1375 { 1376 uint32_t pte_flags; 1377 uint32_t pte_ppn; 1378 1301 1379 vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); 1302 1380 size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); 1303 1304 1381 1382 1305 1383 // Hit test. Just to verify. 1306 bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); 1307 assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); 1384 bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); 1385 assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); 1308 1386 pte_flags= r_tlb_buf_data[word_position]; 1309 1387 pte_ppn= r_tlb_buf_data[word_position+1]; //because PTE2 is 2 words long 1310 1388 // Bit valid checking 1311 if ( not ( pte_flags & PTE_V_MASK) ) 1389 if ( not ( pte_flags & PTE_V_MASK) ) // unmapped 1312 1390 { 1313 1391 //must not occur! 1314 1392 std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl 1315 1393 << "The Page Table entry ins't valid (unmapped)" << std::endl; 1316 1394 1317 1395 r_tlb_miss_error = true; 1318 1396 r_dma_cmd_to_tlb_req = false; 1319 r_tlb_fsm = TLB_IDLE; 1397 r_tlb_fsm = TLB_IDLE; 1320 1398 1321 1399 #if DEBUG_TLB_MISS 1322 1400 if ( m_debug_activated ) 1323 std::cout << " <IOB TLB_PTE2_GET> PTE2 Unmapped" << std::hex 1401 std::cout << name() 1402 << " <IOB TLB_PTE2_GET> PTE2 Unmapped" << std::hex 1324 1403 << " / PADDR = " << r_tlb_paddr.read() 1325 1404 << " / PTE = " << pte_flags << std::endl; 1326 1405 #endif 1327 break; 1406 break; 1328 1407 } 1329 1330 r_tlb_pte_flags = pte_flags; 1408 1409 r_tlb_pte_flags = pte_flags; 1331 1410 r_tlb_pte_ppn = pte_ppn; 1332 1411 r_tlb_fsm = TLB_PTE2_SELECT; 1333 1412 1334 1413 #if DEBUG_TLB_MISS 1335 1414 if ( m_debug_activated ) 1336 std::cout << " <IOB TLB_PTE2_GET> Mapped" << std::hex 1337 << " / PTE_FLAGS = " << pte_flags 1415 std::cout << name() 1416 << " <IOB TLB_PTE2_GET> Mapped" << std::hex 1417 << " / PTE_FLAGS = " << pte_flags 1338 1418 << " / PTE_PPN = " << pte_ppn << std::endl; 1339 1419 #endif … … 1347 1427 1348 1428 r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), 1349 false, // PTE21429 false, // PTE2 1350 1430 &way, 1351 1431 &set ); … … 1356 1436 #if DEBUG_TLB_MISS 1357 1437 if ( m_debug_activated ) 1358 std::cout << " <IOB TLB_PTE2_SELECT> Select a slot in IOTLB:" 1438 std::cout << name() 1439 << " <IOB TLB_PTE2_SELECT> Select a slot in IOTLB:" 1359 1440 << " way = " << std::dec << way 1360 1441 << " / set = " << set << std::endl; … … 1366 1447 } 1367 1448 /////////////////// 1368 case TLB_PTE2_UPDT: 1449 case TLB_PTE2_UPDT: // write a new PTE2 in tlb 1369 1450 // not necessary to treat the L/R bit 1370 1451 { 1371 1452 uint32_t pte_flags = r_tlb_pte_flags.read(); 1372 1453 uint32_t pte_ppn = r_tlb_pte_ppn.read(); 1373 1454 1374 1455 r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_ppn.read() & PPN2_MASK) << 12) 1375 1456 | (r_dma_cmd_to_tlb_vaddr.read()& K_PAGE_OFFSET_MASK) ); 1376 1457 1377 1458 // update TLB for a PTE2 1378 r_iotlb.write( false, 1459 r_iotlb.write( false, // 4K page 1379 1460 pte_flags, 1380 1461 pte_ppn, 1381 r_dma_cmd_to_tlb_vaddr.read(), 1382 r_tlb_way.read(), 1462 r_dma_cmd_to_tlb_vaddr.read(), 1463 r_tlb_way.read(), 1383 1464 r_tlb_set.read(), 1384 1465 0 ); // nline = 0 … … 1390 1471 if ( m_debug_activated ) 1391 1472 { 1392 std::cout << " <IOB TLB_PTE2_UPDT> write PTE2 in IOTLB" 1473 std::cout << name() 1474 << " <IOB TLB_PTE2_UPDT> write PTE2 in IOTLB" 1393 1475 << " / set = " << std::dec << r_tlb_set.read() 1394 1476 << " / way = " << r_tlb_way.read() << std::endl; … … 1397 1479 #endif 1398 1480 // next state 1399 r_tlb_fsm = TLB_RETURN; 1481 r_tlb_fsm = TLB_RETURN; 1400 1482 break; 1401 1483 } … … 1404 1486 // PTE inval request are handled as unmaskable interrupts 1405 1487 { 1406 if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation 1488 if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation 1407 1489 { 1408 1490 r_config_cmd_to_tlb_req = false; … … 1414 1496 m_cost_iotlbmiss_transaction++; 1415 1497 #endif 1416 if ( not r_tlb_to_miss_wti_cmd_req.read() ) 1417 { 1418 1419 1498 if ( not r_tlb_to_miss_wti_cmd_req.read() ) // Miss transaction completed 1499 { 1500 if ( r_miss_wti_rsp_error_miss.read() ) // bus error reported 1501 { 1420 1502 r_miss_wti_rsp_error_miss = false; 1421 1503 r_tlb_miss_error = true; … … 1425 1507 else if(r_tlb_miss_type == PTE1_MISS) 1426 1508 { 1427 r_tlb_fsm = TLB_PTE1_GET; 1509 r_tlb_fsm = TLB_PTE1_GET; 1428 1510 } 1429 1511 else … … 1440 1522 #if DEBUG_TLB_MISS 1441 1523 if ( m_debug_activated ) 1442 std::cout << " <IOB TLB_RETURN> IOTLB MISS completed" << std::endl; 1524 std::cout << name() 1525 << " <IOB TLB_RETURN> IOTLB MISS completed" << std::endl; 1443 1526 #endif 1444 1527 r_dma_cmd_to_tlb_req = false; … … 1457 1540 if(!r_tlb_buf_big_page) 1458 1541 { 1459 if( r_tlb_buf_vaddr.read() == 1460 (r_config_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET) ) 1542 if( r_tlb_buf_vaddr.read() == 1543 (r_config_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET) ) 1461 1544 // The virtual address corresponds to one entry on the buffer line 1462 1545 { … … 1466 1549 else // First level entries on buffer. Unused if only small pages 1467 1550 { 1468 if( r_tlb_buf_vaddr.read() == 1469 (r_config_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET) ) 1551 if( r_tlb_buf_vaddr.read() == 1552 (r_config_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET) ) 1470 1553 // The virtual address corresponds to one entry on the buffer line 1471 1554 { … … 1474 1557 } 1475 1558 } 1476 1559 1477 1560 // Invalidation on IOTLB 1478 bool ok; 1479 ok = r_iotlb.inval(r_config_cmd_to_tlb_vaddr.read()); 1480 1481 if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; 1561 r_iotlb.inval(r_config_cmd_to_tlb_vaddr.read()); 1562 1563 if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; 1482 1564 else r_tlb_fsm = TLB_IDLE; 1483 break; 1565 break; 1484 1566 } 1485 1567 } //end switch r_tlb_fsm 1486 1568 1487 1569 //////////////////////////////////////////////////////////////////////////////// 1488 1570 // The CONFIG_CMD_FSM handles the VCI commands from the INT network. … … 1501 1583 /////////////////////////////////////////////////////////////////////////////// 1502 1584 1503 switch( r_config_cmd_fsm.read() ) 1585 switch( r_config_cmd_fsm.read() ) 1504 1586 { 1505 1587 ///////////////////// 1506 1588 case CONFIG_CMD_IDLE: // A VCI INT command is always consumed in this state 1507 1589 { 1508 if ( p_vci_tgt_int.cmdval.read() ) 1590 if ( p_vci_tgt_int.cmdval.read() ) 1509 1591 { 1510 1592 1511 1593 #if DEBUG_CONFIG_CMD 1512 1594 if( m_debug_activated ) 1513 std::cout << " <IOB CONFIG_CMD_IDLE> ### Config Command received" << std::endl 1595 std::cout << name() 1596 << " <IOB CONFIG_CMD_IDLE> ### Config Command received" << std::endl 1514 1597 << " address = " << std::hex << p_vci_tgt_int.address.read() 1515 1598 << " / srcid = " << p_vci_tgt_int.srcid.read() 1516 1599 << " / trdid = " << p_vci_tgt_int.trdid.read() 1600 << " / pktid = " << p_vci_tgt_int.pktid.read() 1517 1601 << " / wdata = " << std::hex << p_vci_tgt_int.wdata.read() 1518 1602 << " / be = " << p_vci_tgt_int.be.read() … … 1522 1606 vci_addr_t paddr = p_vci_tgt_int.address.read(); 1523 1607 bool read = (p_vci_tgt_int.cmd.read() == vci_param_int::CMD_READ); 1524 uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); 1608 uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); 1525 1609 bool eop = p_vci_tgt_int.eop.read(); 1526 1610 bool high = (paddr & 0x4); 1611 ext_data_t wdata = (ext_data_t)p_vci_tgt_int.wdata.read(); 1612 ext_be_t be = (ext_be_t)p_vci_tgt_int.be.read(); 1527 1613 1528 1614 // chek segments … … 1530 1616 bool found = false; 1531 1617 bool special = false; 1532 for ( seg = m_int_seglist.begin() ; 1618 for ( seg = m_int_seglist.begin() ; 1533 1619 seg != m_int_seglist.end() and not found ; seg++ ) 1534 1620 { 1535 if ( seg->contains(paddr) ) 1621 if ( seg->contains(paddr) ) 1536 1622 { 1537 1623 found = true; … … 1539 1625 } 1540 1626 } 1541 1627 1542 1628 if ( found and special ) // IO_BRIDGE itself 1543 1629 { 1544 1630 bool rerror = false; 1545 1546 assert( (p_vci_tgt_int.be.read() == 0xF) and 1631 int_data_t rdata; 1632 1633 assert( (be == 0xF) and 1547 1634 "ERROR in vci_io_bridge : BE must be 0xF for a config access"); 1548 1635 … … 1552 1639 if ( not read && (cell == IOB_IOMMU_PTPR) ) // WRITE PTPR 1553 1640 { 1554 r_iommu_ptpr = (uint32_t) p_vci_tgt_int.wdata.read();1555 } 1556 else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR 1557 { 1558 r _config_cmd_to_config_rsp_rdata = r_iommu_ptpr.read();1641 r_iommu_ptpr = (uint32_t)wdata; 1642 } 1643 else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR 1644 { 1645 rdata = r_iommu_ptpr.read(); 1559 1646 } 1560 1647 else if( not read && (cell == IOB_WTI_ENABLE)) // WRITE WTI_ENABLE 1561 1648 { 1562 r_iommu_wti_enable = p_vci_tgt_int.wdata.read();1649 r_iommu_wti_enable = wdata; 1563 1650 } 1564 1651 else if( read && (cell == IOB_WTI_ENABLE)) // READ WTI ENABLE 1565 1652 { 1566 r _config_cmd_to_config_rsp_rdata = r_iommu_wti_enable.read();1653 rdata = r_iommu_wti_enable.read(); 1567 1654 } 1568 1655 else if( read && (cell == IOB_IOMMU_BVAR)) // READ BVAR 1569 1656 { 1570 r _config_cmd_to_config_rsp_rdata = r_iommu_bvar.read();1657 rdata = r_iommu_bvar.read(); 1571 1658 } 1572 1659 else if( read && (cell == IOB_IOMMU_ETR)) // READ ETR 1573 1660 { 1574 r _config_cmd_to_config_rsp_rdata = r_iommu_etr.read();1661 rdata = r_iommu_etr.read(); 1575 1662 } 1576 1663 else if( read && (cell == IOB_IOMMU_BAD_ID)) // READ BAD_ID 1577 1664 { 1578 r _config_cmd_to_config_rsp_rdata = r_iommu_bad_id.read();1665 rdata = r_iommu_bad_id.read(); 1579 1666 } 1580 1667 else if( not read && (cell == IOB_INVAL_PTE)) // WRITE INVAL_PTE 1581 1668 { 1582 1669 r_config_cmd_to_tlb_req = true; 1583 r_config_cmd_to_tlb_vaddr = (uint32_t) p_vci_tgt_int.wdata.read();1670 r_config_cmd_to_tlb_vaddr = (uint32_t)wdata; 1584 1671 } 1585 1672 else if( not read && (cell == IOB_WTI_ADDR_LO)) // WRITE WTI_PADDR_LO 1586 1673 { 1587 r_iommu_wti_addr_lo = (vci_addr_t) p_vci_tgt_int.wdata.read();1674 r_iommu_wti_addr_lo = (vci_addr_t)wdata; 1588 1675 } 1589 1676 else if( read && (cell == IOB_WTI_ADDR_LO)) // READ WTI_PADDR_LO 1590 1677 { 1591 r _config_cmd_to_config_rsp_rdata = r_iommu_wti_addr_lo.read();1678 rdata = r_iommu_wti_addr_lo.read(); 1592 1679 } 1593 1680 else if( not read && (cell == IOB_WTI_ADDR_HI)) // WRITE WTI_PADDR_HI 1594 1681 { 1595 r_iommu_wti_addr_hi = (vci_addr_t) p_vci_tgt_int.wdata.read();1682 r_iommu_wti_addr_hi = (vci_addr_t)wdata; 1596 1683 } 1597 1684 else if( read && (cell == IOB_WTI_ADDR_HI)) // READ WTI_PADDR_HI 1598 1685 { 1599 r_config_cmd_to_config_rsp_rdata = r_iommu_wti_addr_hi.read(); 1600 } 1601 else if( not read && (cell == IOB_XICU_BASE)) // WRITE XICU_BASE 1602 { 1603 r_xicu_base = (vci_addr_t)p_vci_tgt_int.wdata.read(); 1604 } 1605 else if( read && (cell == IOB_XICU_BASE)) // READ XICU_BASE 1606 { 1607 r_config_cmd_to_config_rsp_rdata = r_xicu_base.read(); 1608 } 1609 else if( not read && (cell == IOB_XICU_SIZE)) // WRITE XICU_SIZE 1610 { 1611 r_xicu_size = (vci_addr_t)p_vci_tgt_int.wdata.read(); 1612 } 1613 else if( read && (cell == IOB_XICU_SIZE)) // READ XICU_SIZE 1614 { 1615 r_config_cmd_to_config_rsp_rdata = r_xicu_size.read(); 1686 rdata = r_iommu_wti_addr_hi.read(); 1616 1687 } 1617 1688 else // Error: Wrong address, or invalid operation. … … 1620 1691 } 1621 1692 r_config_cmd_to_config_rsp_rerror = rerror; 1622 r_config_cmd_fsm = CONFIG_CMD_RSP; 1693 r_config_cmd_to_config_rsp_rdata = rdata; 1694 r_config_cmd_to_config_rsp_rsrcid = p_vci_tgt_int.srcid.read(); 1695 r_config_cmd_to_config_rsp_rtrdid = p_vci_tgt_int.trdid.read(); 1696 r_config_cmd_to_config_rsp_rpktid = p_vci_tgt_int.pktid.read(); 1697 r_config_cmd_fsm = CONFIG_CMD_RSP; 1623 1698 } 1624 1699 else if ( found ) // remote peripheral 1625 1700 { 1701 // buffer VCI command 1626 1702 r_config_cmd_address = p_vci_tgt_int.address.read(); 1627 r_config_cmd_srcid = p_vci_tgt_int.srcid.read();1628 r_config_cmd_trdid = p_vci_tgt_int.trdid.read();1629 r_config_cmd_pktid = p_vci_tgt_int.pktid.read();1630 1703 r_config_cmd_pktid = p_vci_tgt_int.pktid.read(); 1631 1704 r_config_cmd_plen = p_vci_tgt_int.plen.read(); … … 1636 1709 r_config_cmd_contig = p_vci_tgt_int.contig.read(); 1637 1710 r_config_cmd_cfixed = p_vci_tgt_int.cfixed.read(); 1638 1639 if( eop ) // single flit command 1640 { 1641 if ( high ) // HI word 1642 { 1643 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read())<<32; 1644 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read())<<4; 1645 r_config_cmd_eop = true; 1646 r_config_cmd_fsm = CONFIG_CMD_PUT; 1647 } 1648 else // LO word 1649 { 1650 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read()); 1651 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read()); 1652 r_config_cmd_eop = true; 1653 r_config_cmd_fsm = CONFIG_CMD_PUT; 1654 } 1655 } 1656 else // multi-flits write 1657 { 1658 if ( high ) // MSB word 1659 { 1660 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read())<<32; 1661 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read())<<4; 1662 r_config_cmd_eop = false; 1663 r_config_cmd_fsm = CONFIG_CMD_PUT; 1664 } 1665 else // LSB word 1666 { 1667 r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read()); 1668 r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read()); 1669 r_config_cmd_eop = false; 1670 r_config_cmd_fsm = CONFIG_CMD_NEXT; 1671 } 1672 } 1673 } 1674 else // out of segment address 1675 { 1711 r_config_cmd_eop = eop; 1712 r_config_cmd_wdata = (wdata << (high ? 32 : 0)); 1713 r_config_cmd_be = (be << (high ? 4 : 0)); 1714 1715 size_t tab_index; 1716 if (m_iox_transaction_tab.full(tab_index)) 1717 { 1718 #ifdef INSTRUMENTATION 1719 m_cpt_trt_config_full++; 1720 #endif 1721 1722 // wait for an empty slot in the IOX transaction table. 1723 // buffer SRCID and TRDID of VCI command to store them 1724 // later in IOX transaction table. 1725 r_config_cmd_srcid = p_vci_tgt_int.srcid.read(); 1726 r_config_cmd_trdid = p_vci_tgt_int.trdid.read(); 1727 r_config_cmd_fsm = CONFIG_CMD_WAIT; 1728 break; 1729 } 1730 1731 // TRDID in IOX interconnect is the translation table index 1732 r_config_cmd_trdid = tab_index; 1733 1734 // create new entry in IOX transaction table 1735 m_iox_transaction_tab.set( tab_index, 1736 p_vci_tgt_int.srcid.read(), 1737 p_vci_tgt_int.trdid.read()); 1738 1739 if (eop) r_config_cmd_fsm = CONFIG_CMD_PUT; 1740 else r_config_cmd_fsm = CONFIG_CMD_HI; 1741 1742 #if DEBUG_CONFIG_CMD 1743 if( m_debug_activated ) 1744 { 1745 std::cout << name() 1746 << " <IOB CONFIG_CMD_IDLE> ### new entry in IOX transaction table" 1747 << std::endl; 1748 m_iox_transaction_tab.printTrace(); 1749 } 1750 #endif 1751 1752 } 1753 else if ( eop ) // out of segment address 1754 { 1755 r_config_cmd_to_config_rsp_rerror = true; 1676 1756 r_config_cmd_to_config_rsp_rdata = 0; 1677 r_config_cmd_to_config_rsp_rerror = true; 1678 if( eop ) r_config_cmd_fsm = CONFIG_CMD_RSP; 1757 r_config_cmd_to_config_rsp_rsrcid = p_vci_tgt_int.srcid.read(); 1758 r_config_cmd_to_config_rsp_rtrdid = p_vci_tgt_int.trdid.read(); 1759 r_config_cmd_to_config_rsp_rpktid = p_vci_tgt_int.pktid.read(); 1760 r_config_cmd_fsm = CONFIG_CMD_RSP; 1679 1761 } 1680 1762 } // end if cmdval … … 1682 1764 } 1683 1765 ///////////////////// 1684 case CONFIG_CMD_NEXT: // Consume the second flit for a multi-flits write 1685 { 1686 if ( p_vci_tgt_int.cmdval.read() ) 1766 case CONFIG_CMD_WAIT: 1767 { 1768 // wait for an empty slot in the translation table. 1769 size_t tab_index; 1770 if (m_iox_transaction_tab.full(tab_index)) 1771 { 1772 #ifdef INSTRUMENTATION 1773 m_cpt_trt_config_full_cost++; 1774 #endif 1775 break; 1776 } 1777 1778 // create new entry in IOX transaction table 1779 m_iox_transaction_tab.set( tab_index, 1780 r_config_cmd_srcid.read(), 1781 r_config_cmd_trdid.read()); 1782 1783 // TRDID in IOX interconnect is the translation table index 1784 r_config_cmd_trdid = tab_index; 1785 if (r_config_cmd_eop.read()) r_config_cmd_fsm = CONFIG_CMD_PUT; 1786 else r_config_cmd_fsm = CONFIG_CMD_HI; 1787 1788 #if DEBUG_CONFIG_CMD 1789 if( m_debug_activated ) 1790 { 1791 std::cout << name() 1792 << " <IOB CONFIG_CMD_WAIT> ### new entry in IOX transaction table" 1793 << std::endl; 1794 m_iox_transaction_tab.printTrace(); 1795 } 1796 #endif 1797 break; 1798 } 1799 ///////////////////// 1800 case CONFIG_CMD_HI: // consume the second flit for a multi-flits write 1801 { 1802 if ( p_vci_tgt_int.cmdval.read() ) 1687 1803 { 1688 1804 vci_addr_t paddr = p_vci_tgt_int.address.read(); 1689 bool high = ( paddr & 0x4== 0x4);1805 bool high = ((paddr & 0x4) == 0x4); 1690 1806 bool eop = p_vci_tgt_int.eop.read(); 1691 1807 … … 1702 1818 break; 1703 1819 } 1820 ///////////////////// 1821 case CONFIG_CMD_LO: // consume the first flit for a multi-flits write 1822 { 1823 if ( p_vci_tgt_int.cmdval.read() ) 1824 { 1825 vci_addr_t paddr = p_vci_tgt_int.address.read(); 1826 bool high = ((paddr & 0x4) == 0x4); 1827 bool eop = p_vci_tgt_int.eop.read(); 1828 1829 assert( (paddr == r_config_cmd_address.read() + 4) and !high and 1830 "ERROR in vci_io_bridge : addresses must be contiguous in write burst" ); 1831 1832 r_config_cmd_address = p_vci_tgt_int.address.read(); 1833 r_config_cmd_wdata = (ext_data_t)p_vci_tgt_int.wdata.read(); 1834 r_config_cmd_be = (ext_be_t)p_vci_tgt_int.be.read(); 1835 r_config_cmd_eop = eop; 1836 1837 if (eop) r_config_cmd_fsm = CONFIG_CMD_PUT; 1838 else r_config_cmd_fsm = CONFIG_CMD_HI; 1839 } 1840 break; 1841 } 1704 1842 //////////////////// 1705 1843 case CONFIG_CMD_PUT: // post a command to CONFIG_CMD fifo (to IOX network) … … 1711 1849 1712 1850 #if DEBUG_CONFIG_CMD 1713 if( m_debug_activated ) 1714 std::cout << " <IOB CONFIG_CMD_PUT> Transmit VCI command to IOX network" 1851 if( m_debug_activated ) 1852 std::cout << name() 1853 << " <IOB CONFIG_CMD_PUT> Transmit VCI command to IOX network" 1715 1854 << " : address = " << std::hex << r_config_cmd_address.read() 1716 << " / srcid = " << r_config_cmd_srcid.read() 1855 << " / srcid = " << m_iox_srcid 1856 << " / trdid = " << r_config_cmd_trdid.read() 1717 1857 << " / eop = " << r_config_cmd_eop.read() 1718 1858 << std::endl; 1719 1859 #endif 1720 r_config_cmd_fsm = CONFIG_CMD_IDLE; 1860 if (r_config_cmd_eop.read()) r_config_cmd_fsm = CONFIG_CMD_IDLE; 1861 else r_config_cmd_fsm = CONFIG_CMD_LO; 1721 1862 } 1722 1863 break; 1723 1864 } 1724 1865 //////////////////// 1725 case CONFIG_CMD_RSP: // Post a request to CONFIG_RSP FSM, 1866 case CONFIG_CMD_RSP: // Post a request to CONFIG_RSP FSM, 1726 1867 // if no previous pending request. 1727 1868 // r_config_cmd_to_config_rsp_rerror 1728 // has been set in IDLE state. 1869 // has been set in IDLE state. 1729 1870 { 1730 1871 if ( not r_config_cmd_to_config_rsp_req.read() ) … … 1733 1874 1734 1875 #if DEBUG_CONFIG_CMD 1735 if( m_debug_activated ) 1736 std::cout << " <IOB CONFIG_CMD_RSP> Request a response to CONFIG_RSP FSM" 1876 if( m_debug_activated ) 1877 std::cout << name() 1878 << " <IOB CONFIG_CMD_RSP> Request a response to CONFIG_RSP FSM" 1737 1879 << " / error = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; 1738 1880 #endif … … 1748 1890 // - CONFIG_CMD : response to a local config command. 1749 1891 // - CONFIG_RSP : responses from peripherals on IOX network 1750 // Regarding the responses from IOX network it handles both single flit 1751 // config responses, and multi-flits read responses (ROM), where data must 1752 // be serialised (64 bits -> 32 bits). 1892 // Regarding the responses from IOX network it handles both single flit 1893 // config responses, and multi-flits read responses (ROM), where data must 1894 // be serialised (64 bits -> 32 bits). 1753 1895 // Note: We use the VCI RPKTID field to distinguish between read cached 1754 1896 // (multi-flits response) and others (single flit response). … … 1759 1901 if ( m_config_rsp_rerror_fifo.wok() ) 1760 1902 { 1761 switch( r_config_rsp_fsm.read() ) 1903 switch( r_config_rsp_fsm.read() ) 1762 1904 { 1763 1905 ///////////////////////// 1764 1906 case CONFIG_RSP_IDLE_IOX: // IOX requests have highest priority 1765 1907 // no flit on IOX network is consumed 1766 { 1908 { 1767 1909 if ( p_vci_ini_iox.rspval.read() ) // IOX request 1768 { 1769 if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits 1910 { 1911 // recover srcid and trdid from the IOX transaction table 1912 size_t tab_index = (size_t)p_vci_ini_iox.rtrdid.read(); 1913 r_config_rsp_rsrcid = m_iox_transaction_tab.readSrcid(tab_index); 1914 r_config_rsp_rtrdid = m_iox_transaction_tab.readTrdid(tab_index); 1915 1916 // erase entry 1917 m_iox_transaction_tab.erase(tab_index); 1918 1919 if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits 1770 1920 { 1771 r_config_rsp_fsm = CONFIG_RSP_PUT_LO W;1921 r_config_rsp_fsm = CONFIG_RSP_PUT_LO; 1772 1922 } 1773 else // single flit 1923 else // single flit 1774 1924 { 1775 1925 r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; 1776 1926 } 1777 } 1778 else if ( r_config_cmd_to_config_rsp_req.read() ) // LOC request 1927 #if DEBUG_CONFIG_RSP 1928 if( m_debug_activated ) 1929 { 1930 std::cout << name() 1931 << " <IOB CONFIG_RSP_IDLE_IOX> ### remove entry in transaction table" 1932 << std::endl; 1933 m_iox_transaction_tab.printTrace(); 1934 } 1935 #endif 1936 } 1937 else if ( r_config_cmd_to_config_rsp_req.read() ) // LOCAL request 1779 1938 { 1780 1939 r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; 1781 1940 } 1782 1941 break; 1783 1942 } 1784 1943 ///////////////////////// 1785 case CONFIG_RSP_IDLE_LOC: // LOC requests have highest priority1944 case CONFIG_RSP_IDLE_LOC: // LOCAL requests have highest priority 1786 1945 // no flit on IOX network is consumed 1787 { 1788 if ( r_config_cmd_to_config_rsp_req.read() ) // LOC request1946 { 1947 if ( r_config_cmd_to_config_rsp_req.read() ) // LOCAL request 1789 1948 { 1790 1949 r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; 1791 1950 } 1792 1951 else if ( p_vci_ini_iox.rspval.read() ) // IOX request 1793 { 1794 if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits 1952 { 1953 // recover srcid and trdid from the IOX transaction table 1954 size_t tab_index = (size_t)p_vci_ini_iox.rtrdid.read(); 1955 r_config_rsp_rsrcid = m_iox_transaction_tab.readSrcid(tab_index); 1956 r_config_rsp_rtrdid = m_iox_transaction_tab.readTrdid(tab_index); 1957 1958 // erase entry 1959 m_iox_transaction_tab.erase(tab_index); 1960 1961 if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits 1795 1962 { 1796 r_config_rsp_fsm = CONFIG_RSP_PUT_LO W;1963 r_config_rsp_fsm = CONFIG_RSP_PUT_LO; 1797 1964 } 1798 else // single flit 1965 else // single flit 1799 1966 { 1800 1967 r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; 1801 1968 } 1802 } 1803 break; 1969 #if DEBUG_CONFIG_RSP 1970 if( m_debug_activated ) 1971 { 1972 std::cout << name() 1973 << " <IOB CONFIG_RSP_IDLE_IOX> ### remove entry in transaction table" 1974 << std::endl; 1975 m_iox_transaction_tab.printTrace(); 1976 } 1977 #endif 1978 } 1979 break; 1804 1980 } 1805 1981 //////////////////////// 1806 case CONFIG_RSP_PUT_LO W: // put 32 low bits into CONFIG_RSP fifo1982 case CONFIG_RSP_PUT_LO: // put 32 low bits into CONFIG_RSP fifo 1807 1983 // no flit on IOX network is consumed 1808 1984 { … … 1810 1986 config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); 1811 1987 config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); 1812 config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read();1813 config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read();1988 config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); 1989 config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); 1814 1990 config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); 1815 1991 config_rsp_fifo_reop = false; … … 1818 1994 1819 1995 #if DEBUG_CONFIG_RSP 1820 if( m_debug_activated ) 1821 std::cout << " <IOB CONFIG_RSP_PUT_LOW> Push multi-flit response into CONFIG_RSP FIFO" 1822 << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() 1823 << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() 1996 if( m_debug_activated ) 1997 std::cout << name() 1998 << " <IOB CONFIG_RSP_PUT_LO> Push multi-flit response into CONFIG_RSP FIFO" 1999 << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() 2000 << " / rtrdid = " << r_config_rsp_rtrdid.read() 1824 2001 << " / rpktid = " << p_vci_ini_iox.rpktid.read() 1825 2002 << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() … … 1827 2004 << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; 1828 2005 #endif 1829 2006 break; 1830 2007 } 1831 2008 /////////////////////// 1832 2009 case CONFIG_RSP_PUT_HI: // put 32 high bits into CONFIG_RSP fifo 1833 // flit on IOX network is consumed 2010 // flit on IOX network is consumed 1834 2011 { 1835 2012 config_rsp_fifo_put = true; 1836 2013 config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); 1837 2014 config_rsp_fifo_rdata = (uint32_t)(p_vci_ini_iox.rdata.read() >> 32); 1838 config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read();1839 config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read();2015 config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); 2016 config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); 1840 2017 config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); 1841 2018 config_rsp_fifo_reop = p_vci_ini_iox.reop.read(); 1842 2019 1843 2020 if( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE_LOC; 1844 else r_config_rsp_fsm = CONFIG_RSP_PUT_LO W;2021 else r_config_rsp_fsm = CONFIG_RSP_PUT_LO; 1845 2022 1846 2023 #if DEBUG_CONFIG_RSP 1847 if( m_debug_activated ) 1848 std::cout << " <IOB CONFIG_RSP_PUT_HI> Push multi-flit response into CONFIG_RSP FIFO" 1849 << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() 1850 << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() 2024 if( m_debug_activated ) 2025 std::cout << name() 2026 << " <IOB CONFIG_RSP_PUT_HI> Push multi-flit response into CONFIG_RSP FIFO" 2027 << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() 2028 << " / rtrdid = " << r_config_rsp_rtrdid.read() 1851 2029 << " / rpktid = " << p_vci_ini_iox.rpktid.read() 1852 2030 << " / rdata = " << (uint32_t)(p_vci_ini_iox.rdata.read() >> 32) … … 1854 2032 << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; 1855 2033 #endif 1856 2034 break; 1857 2035 } 1858 2036 //////////////////////// 1859 2037 case CONFIG_RSP_PUT_UNC: // put single flit into CONFIG_RSP fifo 1860 // flit on IOX network is consumed 1861 { 1862 assert( p_vci_ini_iox.reop.read() and 2038 // flit on IOX network is consumed 2039 { 2040 assert( p_vci_ini_iox.reop.read() and 1863 2041 "ERROR in vci_io_bridge : a remote config response should be one flit"); 1864 2042 … … 1866 2044 config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); 1867 2045 config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); 1868 config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read();1869 config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read();2046 config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); 2047 config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); 1870 2048 config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); 1871 2049 config_rsp_fifo_reop = true; … … 1875 2053 1876 2054 #if DEBUG_CONFIG_RSP 1877 if( m_debug_activated ) 1878 std::cout << " <IOB CONFIG_RSP_PUT_UNC> Push single flit response into CONFIG_RSP FIFO" 1879 << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() 1880 << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() 2055 if( m_debug_activated ) 2056 std::cout << name() 2057 << " <IOB CONFIG_RSP_PUT_UNC> Push single flit response into CONFIG_RSP FIFO" 2058 << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() 2059 << " / rtrdid = " << r_config_rsp_rtrdid.read() 1881 2060 << " / rpktid = " << p_vci_ini_iox.rpktid.read() 1882 2061 << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() … … 1884 2063 << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; 1885 2064 #endif 1886 2065 break; 1887 2066 } 1888 2067 //////////////////////// 1889 2068 case CONFIG_RSP_PUT_LOC: // put single flit into CONFIG_RSP fifo 1890 // no flit on IOX network is consumed 2069 // no flit on IOX network is consumed 1891 2070 { 1892 2071 config_rsp_fifo_put = true; 1893 2072 config_rsp_fifo_rerror = r_config_cmd_to_config_rsp_rerror.read(); 1894 2073 config_rsp_fifo_rdata = r_config_cmd_to_config_rsp_rdata.read(); 1895 config_rsp_fifo_rsrcid = r_config_cmd_ srcid.read();1896 config_rsp_fifo_rtrdid = r_config_cmd_t rdid.read();1897 config_rsp_fifo_rpktid = r_config_cmd_ pktid.read();2074 config_rsp_fifo_rsrcid = r_config_cmd_to_config_rsp_rsrcid.read(); 2075 config_rsp_fifo_rtrdid = r_config_cmd_to_config_rsp_rtrdid.read(); 2076 config_rsp_fifo_rpktid = r_config_cmd_to_config_rsp_rpktid.read(); 1898 2077 config_rsp_fifo_reop = true; 1899 2078 1900 // acknowledge request 2079 // acknowledge request 1901 2080 r_config_cmd_to_config_rsp_req = false; 1902 2081 … … 1905 2084 1906 2085 #if DEBUG_CONFIG_RSP 1907 if( m_debug_activated ) 1908 std::cout << " <IOB CONFIG_RSP_PUT_UNC> Push single flit response into CONFIG_RSP FIFO" 1909 << " / rsrcid = " << std::hex << r_config_cmd_srcid.read() 1910 << " / rtrdid = " << r_config_cmd_trdid.read() 1911 << " / rpktid = " << r_config_cmd_pktid.read() 2086 if( m_debug_activated ) 2087 std::cout << name() 2088 << " <IOB CONFIG_RSP_PUT_UNC> Push single flit response into CONFIG_RSP FIFO" 2089 << " / rsrcid = " << std::hex << r_config_cmd_to_config_rsp_rsrcid.read() 2090 << " / rtrdid = " << r_config_cmd_to_config_rsp_rtrdid.read() 2091 << " / rpktid = " << r_config_cmd_to_config_rsp_rpktid.read() 1912 2092 << " / rdata = " << r_config_cmd_to_config_rsp_rdata.read() 1913 2093 << " / reop = " << true 1914 2094 << " / rerror = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; 1915 2095 #endif 1916 2096 break; 1917 2097 } 1918 2098 } // end switch CONFIG_RSP FSM … … 1927 2107 // MISS_WTI_RSP FSM only when the response is received. 1928 2108 // 2. WTI requests from DMA_CMD FSM : 1929 // These requestsare non blocking events, and the r_dma_cmd_to_miss_wti_cmd_req 1930 // flip-flop is reset as soon as the WTI command has been sent. 2109 // These requestsare non blocking events, and the r_dma_cmd_to_miss_wti_cmd_req 2110 // flip-flop is reset as soon as the WTI command has been sent. 1931 2111 // There is two types of WTI requests: 1932 2112 // - external WTI from peripherals on IOX network. 1933 2113 // - internal WTI caused by illegal DMA requests. 1934 2114 //////////////////////////////////////////////////////////////////////////////////// 1935 1936 if ( r_tlb_to_miss_wti_cmd_req.read() and 2115 2116 if ( r_tlb_to_miss_wti_cmd_req.read() and 1937 2117 m_miss_wti_cmd_addr_fifo.wok() ) // put MISS READ 1938 2118 { 1939 2119 miss_wti_cmd_fifo_put = true; 1940 miss_wti_cmd_fifo_address = r_tlb_paddr.read(); 1941 miss_wti_cmd_fifo_wdata = 0; 2120 miss_wti_cmd_fifo_address = r_tlb_paddr.read(); 2121 miss_wti_cmd_fifo_wdata = 0; 1942 2122 miss_wti_cmd_fifo_cmd = vci_param_int::CMD_READ; 1943 2123 miss_wti_cmd_fifo_pktid = PKTID_MISS; … … 1947 2127 #if DEBUG_MISS_WTI_CMD 1948 2128 if( m_debug_activated ) 1949 std::cout << " <IOB MISS_WTI_CMD_WTI> push MISS TLB command into MISS_WTI FIFO" 2129 std::cout << name() 2130 << " <IOB MISS_WTI_CMD_WTI> push MISS TLB command into MISS_WTI FIFO" 1950 2131 << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; 1951 2132 #endif 1952 2133 1953 2134 } 1954 else if ( r_dma_cmd_to_miss_wti_cmd_req.read() and 2135 else if ( r_dma_cmd_to_miss_wti_cmd_req.read() and 1955 2136 m_miss_wti_cmd_addr_fifo.wok() ) // put WTI READ / WRITE 1956 2137 { … … 1967 2148 #if DEBUG_MISS_WTI_CMD 1968 2149 if( m_debug_activated ) 1969 std::cout << " <IOB MISS_WTI_CMD_WTI> push WTI command into MISS_WTI FIFO" 2150 std::cout << name() 2151 << " <IOB MISS_WTI_CMD_WTI> push WTI command into MISS_WTI FIFO" 1970 2152 << " / CMD = " << miss_wti_cmd_fifo_cmd 1971 2153 << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; 1972 2154 #endif 1973 2155 1974 } 2156 } 1975 2157 1976 2158 /////////////////////////////////////////////////////////////////////////////////// 1977 2159 // The MISS_WTI_RSP FSM handles VCI responses from the INT network: 1978 2160 // - for a TLB MISS (multi-flits read transaction), the cache line 1979 // is written in r_tlb_buf_data[], and r_tlb_to_miss_wti_cmd_req flip-flop is reset. 2161 // is written in r_tlb_buf_data[], and r_tlb_to_miss_wti_cmd_req flip-flop is reset. 1980 2162 // - for a WTI_IOX (single flit write transaction), the response must be 1981 2163 // forwarded to the source peripheral on the INT network 1982 2164 // - for a WTI_MMU (single flit write transaction), there is nothing to do. 1983 2165 // 1984 // TODO VCI addressing errors for TLB MISS or for WTI_MMU (i.e. kernel errors...) 2166 // TODO VCI addressing errors for TLB MISS or for WTI_MMU (i.e. kernel errors...) 1985 2167 // are registered in the r_miss_wti_rsp_error_miss & r_miss_wti_rsp_error_wti 1986 2168 // flip-flops, and simulation stops... They could be signaled to OS by a WTI. 1987 2169 //////////////////////////////////////////////////////////////////////////////////// 1988 1989 switch ( r_miss_wti_rsp_fsm.read() ) 2170 2171 switch ( r_miss_wti_rsp_fsm.read() ) 1990 2172 { 1991 2173 /////////////////////// … … 1993 2175 // no VCI flit is consumed 1994 2176 { 1995 if ( p_vci_ini_int.rspval.read() ) 1996 { 1997 if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_IOX ) 2177 if ( p_vci_ini_int.rspval.read() ) 2178 { 2179 if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_IOX ) 1998 2180 { 1999 2181 r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_IOX; 2000 2182 } 2001 else if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_MMU ) 2183 else if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_MMU ) 2002 2184 { 2003 2185 r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_MMU; … … 2022 2204 // if no pending previous request. 2023 2205 { 2024 assert( p_vci_ini_int.reop.read() and 2025 "VCI_IO_BRIDGE ERROR: WTI_IOX response should have one single flit" ); 2026 2206 assert( p_vci_ini_int.reop.read() and 2207 "VCI_IO_BRIDGE ERROR: WTI_IOX response should have one single flit" ); 2208 2027 2209 if ( not r_miss_wti_rsp_to_dma_rsp_req.read() ) // no previous pending request 2028 2210 { … … 2037 2219 #if DEBUG_MISS_WTI_RSP 2038 2220 if( m_debug_activated ) 2039 std::cout << " <IOB MISS_WTI_RSP_WTI_IOX> Transfer response to a WTI_IOX" << std::endl; 2221 std::cout << name() 2222 << " <IOB MISS_WTI_RSP_WTI_IOX> Transfer response to a WTI_IOX" << std::endl; 2040 2223 #endif 2041 2224 } 2042 2225 break; 2043 2226 } 2044 ////////////////////////// 2227 ////////////////////////// 2045 2228 case MISS_WTI_RSP_WTI_MMU: // Handling response to an iommu WTI 2046 2229 // consume VCI flit and test VCI error. 2047 2230 { 2048 assert( p_vci_ini_int.reop.read() and 2049 "VCI_IO_BRIDGE ERROR: WTI_MMU response should have one single flit" ); 2050 2231 assert( p_vci_ini_int.reop.read() and 2232 "VCI_IO_BRIDGE ERROR: WTI_MMU response should have one single flit" ); 2233 2051 2234 if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported 2052 2235 { 2053 2236 // set the specific error flip-flop 2054 2237 r_miss_wti_rsp_error_wti = true; 2055 assert( false and 2238 assert( false and 2056 2239 "VCI_IO_BRIDGE ERROR: VCI error response for a WTI_MMU transaction"); 2057 2240 } 2058 2241 2059 2242 #if DEBUG_MISS_WTI_RSP 2060 if( m_debug_activated ) 2061 std::cout << " <IOB MISS_WTI_RSP_WTI_MMU> Receive response to a WTI_MMU" << std::endl; 2243 if( m_debug_activated ) 2244 std::cout << name() 2245 << " <IOB MISS_WTI_RSP_WTI_MMU> Receive response to a WTI_MMU" << std::endl; 2062 2246 #endif 2063 2247 break; 2064 2248 } 2065 2249 /////////////////////// 2066 case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS 2250 case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS 2067 2251 // write cache line in r_tlb_buf buffer 2068 2252 // and analyse possible VCI error 2069 2253 // VCI flit is consumed. 2070 2254 { 2071 if ( p_vci_ini_int.rspval.read() ) 2255 if ( p_vci_ini_int.rspval.read() ) 2072 2256 { 2073 2257 if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported … … 2075 2259 // set the specific error flip-flop 2076 2260 r_miss_wti_rsp_error_miss = true; 2077 assert( false and 2261 assert( false and 2078 2262 "VCI_IO_BRIDGE ERROR: VCI error response for a TLB MISS transaction"); 2079 2263 … … 2082 2266 { 2083 2267 2084 #if DEBUG_MISS_WTI_CMD 2085 if( m_debug_activated ) 2086 std::cout << " <IOB MISS_WTI_RSP_MISS> Receive response to a TLB MISS" 2268 #if DEBUG_MISS_WTI_CMD 2269 if( m_debug_activated ) 2270 std::cout << name() 2271 << " <IOB MISS_WTI_RSP_MISS> Receive response to a TLB MISS" 2087 2272 << " / Count = " << r_miss_wti_rsp_count.read() 2088 << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; 2273 << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; 2089 2274 #endif 2090 2275 r_tlb_buf_data[r_miss_wti_rsp_count.read()] = p_vci_ini_int.rdata.read(); 2091 2276 } 2092 2277 2093 2278 if ( p_vci_ini_int.reop.read() ) // last flit 2094 { 2279 { 2095 2280 bool eop = p_vci_ini_int.eop.read(); 2096 assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and 2281 assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and 2097 2282 "VCI_IO_BRIDGE ERROR: invalid length for a TLB MISS response"); 2098 2283 2099 2284 r_miss_wti_rsp_count = 0; 2100 2285 r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; 2101 r_tlb_to_miss_wti_cmd_req = false; 2102 } 2103 else // not the last flit 2286 r_tlb_to_miss_wti_cmd_req = false; 2287 } 2288 else // not the last flit 2104 2289 { 2105 2290 r_miss_wti_rsp_count = r_miss_wti_rsp_count.read() + 1; … … 2142 2327 m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get, 2143 2328 dma_cmd_fifo_put, 2144 p_vci_tgt_iox.srcid.read());2329 dma_cmd_fifo_srcid ); 2145 2330 m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get, 2146 2331 dma_cmd_fifo_put, … … 2151 2336 m_dma_cmd_data_fifo.update( dma_cmd_fifo_get, 2152 2337 dma_cmd_fifo_put, 2153 p_vci_tgt_iox.wdata.read() ); 2338 p_vci_tgt_iox.wdata.read() ); 2154 2339 m_dma_cmd_be_fifo.update( dma_cmd_fifo_get, 2155 2340 dma_cmd_fifo_put, 2156 p_vci_tgt_iox.be.read() ); 2341 p_vci_tgt_iox.be.read() ); 2157 2342 m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get, 2158 2343 dma_cmd_fifo_put, … … 2169 2354 m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, 2170 2355 dma_rsp_fifo_put, 2171 dma_rsp_fifo_rsrcid ); 2356 dma_rsp_fifo_rsrcid ); 2172 2357 m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, 2173 2358 dma_rsp_fifo_put, 2174 dma_rsp_fifo_rtrdid ); 2359 dma_rsp_fifo_rtrdid ); 2175 2360 m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, 2176 2361 dma_rsp_fifo_put, 2177 dma_rsp_fifo_rpktid ); 2362 dma_rsp_fifo_rpktid ); 2178 2363 m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, 2179 2364 dma_rsp_fifo_put, 2180 dma_rsp_fifo_reop ); 2365 dma_rsp_fifo_reop ); 2181 2366 m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, 2182 2367 dma_rsp_fifo_put, … … 2190 2375 m_config_cmd_addr_fifo.update( config_cmd_fifo_get, 2191 2376 config_cmd_fifo_put, 2192 r_config_cmd_address.read() ); 2377 r_config_cmd_address.read() ); 2193 2378 m_config_cmd_cmd_fifo.update( config_cmd_fifo_get, 2194 2379 config_cmd_fifo_put, 2195 r_config_cmd_cmd.read() ); 2380 r_config_cmd_cmd.read() ); 2196 2381 m_config_cmd_contig_fifo.update( config_cmd_fifo_get, 2197 2382 config_cmd_fifo_put, 2198 r_config_cmd_contig.read() ); 2383 r_config_cmd_contig.read() ); 2199 2384 m_config_cmd_cons_fifo.update( config_cmd_fifo_get, 2200 2385 config_cmd_fifo_put, 2201 r_config_cmd_cons.read() ); 2386 r_config_cmd_cons.read() ); 2202 2387 m_config_cmd_plen_fifo.update( config_cmd_fifo_get, 2203 2388 config_cmd_fifo_put, 2204 r_config_cmd_plen.read() ); 2389 r_config_cmd_plen.read() ); 2205 2390 m_config_cmd_wrap_fifo.update( config_cmd_fifo_get, 2206 2391 config_cmd_fifo_put, 2207 r_config_cmd_wrap.read() ); 2392 r_config_cmd_wrap.read() ); 2208 2393 m_config_cmd_cfixed_fifo.update( config_cmd_fifo_get, 2209 2394 config_cmd_fifo_put, 2210 r_config_cmd_cfixed.read() ); 2395 r_config_cmd_cfixed.read() ); 2211 2396 m_config_cmd_clen_fifo.update( config_cmd_fifo_get, 2212 2397 config_cmd_fifo_put, 2213 r_config_cmd_clen.read() ); 2214 m_config_cmd_srcid_fifo.update( config_cmd_fifo_get, 2215 config_cmd_fifo_put, 2216 r_config_cmd_srcid.read() ); 2398 r_config_cmd_clen.read() ); 2217 2399 m_config_cmd_trdid_fifo.update( config_cmd_fifo_get, 2218 2400 config_cmd_fifo_put, … … 2230 2412 config_cmd_fifo_put, 2231 2413 r_config_cmd_eop.read() ); 2232 2414 2233 2415 ////////////////////////////////////////////////////////////////////////// 2234 2416 // CONFIG_RSP fifo update … … 2238 2420 m_config_rsp_data_fifo.update( config_rsp_fifo_get, 2239 2421 config_rsp_fifo_put, 2240 config_rsp_fifo_rdata ); 2422 config_rsp_fifo_rdata ); 2241 2423 m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, 2242 2424 config_rsp_fifo_put, … … 2254 2436 config_rsp_fifo_put, 2255 2437 config_rsp_fifo_rerror ); 2256 2438 2257 2439 //////////////////////////////////////////////////////////////// 2258 2440 // MISS_WTI_CMD fifo update … … 2262 2444 m_miss_wti_cmd_addr_fifo.update( miss_wti_cmd_fifo_get, 2263 2445 miss_wti_cmd_fifo_put, 2264 miss_wti_cmd_fifo_address ); 2446 miss_wti_cmd_fifo_address ); 2265 2447 m_miss_wti_cmd_cmd_fifo.update( miss_wti_cmd_fifo_get, 2266 2448 miss_wti_cmd_fifo_put, 2267 miss_wti_cmd_fifo_cmd ); 2449 miss_wti_cmd_fifo_cmd ); 2268 2450 m_miss_wti_cmd_contig_fifo.update( config_cmd_fifo_get, 2269 2451 miss_wti_cmd_fifo_put, … … 2302 2484 miss_wti_cmd_fifo_put, 2303 2485 true ); 2304 2486 2305 2487 } // end transition() 2306 2488 … … 2313 2495 // VCI initiator command on RAM network 2314 2496 // directly the content of the dma_cmd FIFO 2315 p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); 2497 p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); 2316 2498 p_vci_ini_ram.address = m_dma_cmd_addr_fifo.read(); 2317 2499 p_vci_ini_ram.be = m_dma_cmd_be_fifo.read(); 2318 2500 p_vci_ini_ram.cmd = m_dma_cmd_cmd_fifo.read(); 2319 2501 p_vci_ini_ram.contig = m_dma_cmd_contig_fifo.read(); 2320 p_vci_ini_ram.wdata = m_dma_cmd_data_fifo.read(); 2502 p_vci_ini_ram.wdata = m_dma_cmd_data_fifo.read(); 2321 2503 p_vci_ini_ram.eop = m_dma_cmd_eop_fifo.read(); 2322 2504 p_vci_ini_ram.cons = m_dma_cmd_cons_fifo.read(); … … 2328 2510 p_vci_ini_ram.pktid = m_dma_cmd_pktid_fifo.read(); 2329 2511 p_vci_ini_ram.srcid = m_dma_cmd_srcid_fifo.read(); 2330 2512 2331 2513 // VCI initiator response on the RAM Network 2332 2514 // depends on the DMA_RSP FSM state 2333 2334 (r_dma_rsp_fsm.read() == DMA_RSP_PUT_DMA); 2515 p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and 2516 (r_dma_rsp_fsm.read() == DMA_RSP_PUT_DMA); 2335 2517 2336 2518 ///////////////// p_vci_tgt_iox ///////////////////////////// … … 2342 2524 p_vci_tgt_iox.rtrdid = m_dma_rsp_rtrdid_fifo.read(); 2343 2525 p_vci_tgt_iox.rpktid = m_dma_rsp_rpktid_fifo.read(); 2344 p_vci_tgt_iox.rdata = m_dma_rsp_data_fifo.read(); 2526 p_vci_tgt_iox.rdata = m_dma_rsp_data_fifo.read(); 2345 2527 p_vci_tgt_iox.rerror = m_dma_rsp_rerror_fifo.read(); 2346 2528 p_vci_tgt_iox.reop = m_dma_rsp_reop_fifo.read(); … … 2348 2530 // VCI target command ack on IOX network 2349 2531 // depends on the DMA_CMD FSM state 2350 switch ( r_dma_cmd_fsm.read() ) 2351 { 2352 case DMA_CMD_IDLE: 2353 p_vci_tgt_iox.cmdack = false; 2532 switch ( r_dma_cmd_fsm.read() ) 2533 { 2534 case DMA_CMD_IDLE: 2535 p_vci_tgt_iox.cmdack = false; 2354 2536 break; 2355 2537 case DMA_CMD_DMA_REQ: 2356 p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); 2538 p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); 2357 2539 break; 2358 2540 case DMA_CMD_WTI_IOX_REQ: 2359 p_vci_tgt_iox.cmdack = not r_dma_cmd_to_miss_wti_cmd_req.read(); 2541 p_vci_tgt_iox.cmdack = not r_dma_cmd_to_miss_wti_cmd_req.read(); 2360 2542 break; 2361 2543 case DMA_CMD_ERR_WTI_REQ: 2362 p_vci_tgt_iox.cmdack = false; 2544 p_vci_tgt_iox.cmdack = false; 2363 2545 break; 2364 case DMA_CMD_ERR_WAIT_EOP: 2365 p_vci_tgt_iox.cmdack = true; 2546 case DMA_CMD_ERR_WAIT_EOP: 2547 p_vci_tgt_iox.cmdack = true; 2366 2548 break; 2367 case DMA_CMD_ERR_RSP_REQ: 2368 p_vci_tgt_iox.cmdack = false; 2549 case DMA_CMD_ERR_RSP_REQ: 2550 p_vci_tgt_iox.cmdack = false; 2369 2551 break; 2370 case DMA_CMD_TLB_MISS_WAIT: 2371 p_vci_tgt_iox.cmdack = false; 2552 case DMA_CMD_TLB_MISS_WAIT: 2553 p_vci_tgt_iox.cmdack = false; 2372 2554 break; 2373 2555 } … … 2382 2564 p_vci_ini_iox.cmd = m_config_cmd_cmd_fifo.read(); 2383 2565 p_vci_ini_iox.contig = m_config_cmd_contig_fifo.read(); 2384 p_vci_ini_iox.wdata = m_config_cmd_data_fifo.read(); 2566 p_vci_ini_iox.wdata = m_config_cmd_data_fifo.read(); 2385 2567 p_vci_ini_iox.eop = m_config_cmd_eop_fifo.read(); 2386 2568 p_vci_ini_iox.cons = m_config_cmd_cons_fifo.read(); … … 2391 2573 p_vci_ini_iox.trdid = m_config_cmd_trdid_fifo.read(); 2392 2574 p_vci_ini_iox.pktid = m_config_cmd_pktid_fifo.read(); 2393 p_vci_ini_iox.srcid = m_ config_cmd_srcid_fifo.read();2394 2575 p_vci_ini_iox.srcid = m_iox_srcid; 2576 2395 2577 // VCI initiator response on IOX Network 2396 2578 // it depends on the CONFIG_RSP FSM state 2397 p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and2579 p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and 2398 2580 ( (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC) or 2399 2581 (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI) ); … … 2404 2586 // directly the content of the CONFIG_RSP FIFO 2405 2587 p_vci_tgt_int.rspval = m_config_rsp_data_fifo.rok(); 2406 2588 p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); 2407 2589 p_vci_tgt_int.rtrdid = m_config_rsp_rtrdid_fifo.read(); 2408 2590 p_vci_tgt_int.rpktid = m_config_rsp_rpktid_fifo.read(); … … 2410 2592 p_vci_tgt_int.rerror = m_config_rsp_rerror_fifo.read(); 2411 2593 p_vci_tgt_int.reop = m_config_rsp_reop_fifo.read(); 2412 2594 2413 2595 // VCI target command ack on INT network 2414 2596 // it depends on the CONFIG_CMD FSM state 2415 switch ( r_config_cmd_fsm.read() ) 2597 switch ( r_config_cmd_fsm.read() ) 2416 2598 { 2417 2599 case CONFIG_CMD_IDLE: 2418 p_vci_tgt_int.cmdack = true; 2419 break; 2420 case CONFIG_CMD_NEXT: 2421 p_vci_tgt_int.cmdack = true; 2422 break; 2423 case CONFIG_CMD_PUT: 2424 p_vci_tgt_int.cmdack = false; 2425 break; 2426 case CONFIG_CMD_RSP: 2427 p_vci_tgt_int.cmdack = false; 2600 p_vci_tgt_int.cmdack = true; 2601 break; 2602 case CONFIG_CMD_WAIT: 2603 p_vci_tgt_int.cmdack = false; 2604 break; 2605 case CONFIG_CMD_HI: 2606 p_vci_tgt_int.cmdack = true; 2607 break; 2608 case CONFIG_CMD_LO: 2609 p_vci_tgt_int.cmdack = true; 2610 break; 2611 case CONFIG_CMD_PUT: 2612 p_vci_tgt_int.cmdack = false; 2613 break; 2614 case CONFIG_CMD_RSP: 2615 p_vci_tgt_int.cmdack = false; 2428 2616 break; 2429 2617 } … … 2431 2619 ///////////////// p_vci_ini_int //////////////////////////////// 2432 2620 2433 // VCI initiator command on INT network 2434 // directly the content of the MISS_WTI_CMD FIFO 2621 // VCI initiator command on INT network 2622 // directly the content of the MISS_WTI_CMD FIFO 2435 2623 p_vci_ini_int.cmdval = m_miss_wti_cmd_addr_fifo.rok(); 2436 2624 p_vci_ini_int.address = m_miss_wti_cmd_addr_fifo.read(); … … 2438 2626 p_vci_ini_int.cmd = m_miss_wti_cmd_cmd_fifo.read(); 2439 2627 p_vci_ini_int.contig = m_miss_wti_cmd_contig_fifo.read(); 2440 p_vci_ini_int.wdata = m_miss_wti_cmd_data_fifo.read(); 2628 p_vci_ini_int.wdata = m_miss_wti_cmd_data_fifo.read(); 2441 2629 p_vci_ini_int.eop = m_miss_wti_cmd_eop_fifo.read(); 2442 2630 p_vci_ini_int.cons = m_miss_wti_cmd_cons_fifo.read();
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