Index: /trunk/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd =================================================================== --- /trunk/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd (revision 714) +++ /trunk/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd (revision 715) @@ -5,48 +5,48 @@ Module('caba:vci_io_bridge', - classname = 'soclib::caba::VciIoBridge', + classname = 'soclib::caba::VciIoBridge', - tmpl_parameters = [ + tmpl_parameters = [ parameter.Module('vci_param_int', default = 'caba:vci_param', cell_size = parameter.Reference('iob_cell_size_int')), - parameter.Module('vci_param_ext', + parameter.Module('vci_param_ext', default = 'caba:vci_param', cell_size = parameter.Reference('iob_cell_size_ext')), ], - header_files = [ + header_files = [ '../source/include/vci_io_bridge.h', - '../source/include/transaction_tab_io.h' + '../source/include/transaction_tab_io.h' ], - implementation_files = [ '../source/src/vci_io_bridge.cpp' ], + implementation_files = [ '../source/src/vci_io_bridge.cpp' ], - uses = [ Uses('caba:base_module'), - Uses('common:mapping_table'), - Uses('caba:generic_fifo'), - Uses('caba:generic_tlb', - addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', + uses = [ Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('caba:generic_fifo'), + Uses('caba:generic_tlb', + addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))), - Uses('common:address_decoding_table', + Uses('common:address_decoding_table', input_t = 'unsigned long', output_t = 'bool'), - Uses('common:address_decoding_table', + Uses('common:address_decoding_table', input_t = 'unsigned long', output_t = 'int'), ], - ports = [ - Port('caba:vci_initiator', 'p_vci_ini_ram'), - Port('caba:vci_target', 'p_vci_tgt_iox'), - Port('caba:vci_initiator', 'p_vci_ini_iox'), - Port('caba:vci_target', 'p_vci_tgt_int'), - Port('caba:vci_initiator', 'p_vci_ini_int'), - Port('caba:bit_in','p_irq', 32), - Port('caba:bit_in', 'p_resetn', auto = 'resetn'), - Port('caba:clock_in', 'p_clk', auto = 'clock'), + ports = [ + Port('caba:vci_initiator', 'p_vci_ini_ram'), + Port('caba:vci_target', 'p_vci_tgt_iox'), + Port('caba:vci_initiator', 'p_vci_ini_iox'), + Port('caba:vci_target', 'p_vci_tgt_int'), + Port('caba:vci_initiator', 'p_vci_ini_int'), + Port('caba:bit_in','p_irq', 32), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), ], - instance_parameters = [ + instance_parameters = [ parameter.Module('mt_ext', 'common:mapping_table'), parameter.Module('mt_int', 'common:mapping_table'), Index: /trunk/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h =================================================================== --- /trunk/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h (revision 714) +++ /trunk/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h (revision 715) @@ -9,6 +9,4 @@ #define DEBUG_IOB_TRANSACTION 0 -// The index of Transaction Tab Entry corresponds to the trdid of the VCI packet on XRAM network - //////////////////////////////////////////////////////////////////////// // A transaction tab entry @@ -16,10 +14,10 @@ class TransactionTabIOEntry { - typedef uint32_t size_t; + typedef uint32_t size_t; public: - bool valid; // entry valid - size_t srcid; // processor requesting the transaction - size_t trdid; // processor requesting the transaction + bool valid; // valid entry + size_t srcid; // initiator requesting the transaction + size_t trdid; // thread ID of transaction ///////////////////////////////////////////////////////////////////// @@ -28,5 +26,5 @@ void init() { - valid = false; + valid = false; } @@ -38,7 +36,7 @@ void copy(const TransactionTabIOEntry &source) { - valid = source.valid; - srcid = source.srcid; - trdid = source.trdid; + valid = source.valid; + srcid = source.srcid; + trdid = source.trdid; } @@ -47,74 +45,67 @@ //////////////////////////////////////////////////////////////////// void print(){ - std::cout << "valid = " << valid << std::endl; - std::cout << "srcid = " << srcid << std::endl; - std::cout << "trdid = " << trdid << std::endl; - } - - ///////////////////////////////////////////////////////////////////// - // Constructors + std::cout << " valid = " << valid << std::hex + << " / srcid = " << srcid + << " / trdid = " << trdid << std::dec + << std::endl; + } + + ///////////////////////////////////////////////////////////////////// + // Constructors ///////////////////////////////////////////////////////////////////// TransactionTabIOEntry() + { + valid = false; + } + + TransactionTabIOEntry(const TransactionTabIOEntry &source){ + valid = source.valid; + srcid = source.srcid; + trdid = source.trdid; + } + +}; // end class TransactionTabIOEntry + +//////////////////////////////////////////////////////////////////////// +// The transaction tab +//////////////////////////////////////////////////////////////////////// +class TransactionTabIO{ + private: + const size_t size_tab; // The size of the tab + + public: + TransactionTabIOEntry *tab; // The transaction tab + + //////////////////////////////////////////////////////////////////// + // Constructors + //////////////////////////////////////////////////////////////////// + TransactionTabIO(size_t n_entries) : size_tab(n_entries) + { + tab = new TransactionTabIOEntry[size_tab]; + } + + ~TransactionTabIO() + { + delete [] tab; + } + + ///////////////////////////////////////////////////////////////////// + // The size() function returns the size of the tab + ///////////////////////////////////////////////////////////////////// + const size_t& size() + { + return size_tab; + } + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the transaction tab entries + ///////////////////////////////////////////////////////////////////// + void init() + { + for ( size_t index = 0; index < size_tab; index++) { - valid=false; + tab[index].init(); } - - TransactionTabIOEntry(const TransactionTabIOEntry &source){ - valid = source.valid; - srcid = source.srcid; - trdid = source.trdid; - } - -}; // end class TransactionTabIOEntry - -//////////////////////////////////////////////////////////////////////// -// The transaction tab -//////////////////////////////////////////////////////////////////////// -class TransactionTabIO{ -// typedef uint32_t size_t; - - private: - size_t size_tab; // The size of the tab - - public: - TransactionTabIOEntry *tab; // The transaction tab - - //////////////////////////////////////////////////////////////////// - // Constructors - //////////////////////////////////////////////////////////////////// - TransactionTabIO() - { - size_tab=0; - tab=NULL; - } - - TransactionTabIO(size_t n_entries) - { - size_tab = n_entries; - tab = new TransactionTabIOEntry[size_tab]; - } - - ~TransactionTabIO() - { - delete [] tab; - } - - ///////////////////////////////////////////////////////////////////// - // The size() function returns the size of the tab - ///////////////////////////////////////////////////////////////////// - size_t size() - { - return size_tab; - } - - ///////////////////////////////////////////////////////////////////// - // The init() function initializes the transaction tab entries - ///////////////////////////////////////////////////////////////////// - void init() - { - for ( size_t i=0; i p_clk; sc_in p_resetn; - - soclib::caba::VciInitiator p_vci_ini_ram; + + soclib::caba::VciInitiator p_vci_ini_ram; soclib::caba::VciTarget p_vci_tgt_iox; @@ -224,16 +228,21 @@ private: - const size_t m_words; + const size_t m_words; // INT & IOX Networks std::list m_int_seglist; - const vci_srcid_t m_int_srcid; // SRCID on INT network + const vci_srcid_t m_int_srcid; // SRCID on INT network std::list m_iox_seglist; + const vci_srcid_t m_iox_srcid; // SRCID on IOX network + + // INT & RAM srcid masking table + const AddressMaskingTable m_srcid_gid_mask; + const AddressMaskingTable m_srcid_lid_mask; // TLB parameters - const size_t m_iotlb_ways; - const size_t m_iotlb_sets; - - // debug variables + const size_t m_iotlb_ways; + const size_t m_iotlb_sets; + + // debug variables uint32_t m_debug_start_cycle; bool m_debug_ok; @@ -247,16 +256,13 @@ sc_signal r_iommu_bvar; // bad vaddr sc_signal r_iommu_etr; // error type - sc_signal r_iommu_bad_id; // faulty srcid - sc_signal r_iommu_wti_enable; // enable IOB WTI + sc_signal r_iommu_bad_id; // faulty srcid + sc_signal r_iommu_wti_enable; // enable IOB WTI sc_signal r_iommu_wti_addr_lo; // IOMMU WTI paddr (32 lsb) sc_signal r_iommu_wti_addr_hi; // IOMMU WTI paddr (32 msb) - sc_signal r_xicu_base; // XICU paddr base (cluster 0) - sc_signal r_xicu_size; // XIXU paddr size (cluster 0) - - /////////////////////////////////// + /////////////////////////////////// // DMA_CMD FSM REGISTERS /////////////////////////////////// - sc_signal r_dma_cmd_fsm; + sc_signal r_dma_cmd_fsm; sc_signal r_dma_cmd_paddr; // output paddr @@ -275,7 +281,7 @@ sc_signal r_dma_cmd_to_dma_rsp_rerror; sc_signal r_dma_cmd_to_dma_rsp_rdata; - + sc_signal r_dma_cmd_to_tlb_req; - sc_signal r_dma_cmd_to_tlb_vaddr; // input vaddr + sc_signal r_dma_cmd_to_tlb_vaddr; // input vaddr /////////////////////////////////// @@ -283,5 +289,5 @@ /////////////////////////////////// sc_signal r_dma_rsp_fsm; - + /////////////////////////////////// // CONFIG_CMD FSM REGISTERS @@ -294,5 +300,8 @@ sc_signal r_config_cmd_to_config_rsp_req; sc_signal r_config_cmd_to_config_rsp_rerror; - sc_signal r_config_cmd_to_config_rsp_rdata; + sc_signal r_config_cmd_to_config_rsp_rdata; + sc_signal r_config_cmd_to_config_rsp_rsrcid; + sc_signal r_config_cmd_to_config_rsp_rtrdid; + sc_signal r_config_cmd_to_config_rsp_rpktid; sc_signal r_config_cmd_wdata; @@ -301,6 +310,6 @@ sc_signal r_config_cmd_address; sc_signal r_config_cmd_srcid; + sc_signal r_config_cmd_trdid; sc_signal r_config_cmd_pktid; - sc_signal r_config_cmd_trdid; sc_signal r_config_cmd_plen; sc_signal r_config_cmd_clen; @@ -311,27 +320,31 @@ sc_signal r_config_cmd_eop; + TransactionTabIO m_iox_transaction_tab; + /////////////////////////////////// // CONFIG_RSP FSM REGISTERS /////////////////////////////////// sc_signal r_config_rsp_fsm; + sc_signal r_config_rsp_rsrcid; + sc_signal r_config_rsp_rtrdid; /////////////////////////////////// // TLB FSM REGISTERS /////////////////////////////////// - sc_signal r_tlb_fsm; // state register + sc_signal r_tlb_fsm; // state register sc_signal r_waiting_transaction; // Flag for returning from sc_signal r_tlb_miss_type; - sc_signal r_tlb_miss_error; - - sc_signal r_tlb_paddr; // physical address of pte - sc_signal r_tlb_pte_flags; // pte1 or first word of pte2 - sc_signal r_tlb_pte_ppn; // second word of pte2 - sc_signal r_tlb_way; // selected way in tlb - sc_signal r_tlb_set; // selected set in tlb + sc_signal r_tlb_miss_error; + + sc_signal r_tlb_paddr; // physical address of pte + sc_signal r_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_tlb_pte_ppn; // second word of pte2 + sc_signal r_tlb_way; // selected way in tlb + sc_signal r_tlb_set; // selected set in tlb uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs sc_signal r_tlb_buf_valid; // one valit flag for all PTEs - sc_signal r_tlb_buf_tag; // cache line number - sc_signal r_tlb_buf_vaddr; // vaddr for first PTE + sc_signal r_tlb_buf_tag; // cache line number + sc_signal r_tlb_buf_vaddr; // vaddr for first PTE sc_signal r_tlb_buf_big_page; // ??? @@ -352,17 +365,17 @@ sc_signal r_miss_wti_rsp_to_dma_rsp_rpktid; - + ///////////////////////////////////////////////////// // ALLOCATORS for CONFIG_RSP fifo & DMA_RSP fifo ///////////////////////////////////////////////////// - sc_signal r_alloc_fifo_config_rsp_local; - - + sc_signal r_alloc_fifo_config_rsp_local; + + ////////////////////////////////////////////////////////////////// - // IOTLB + // IOTLB ////////////////////////////////////////////////////////////////// GenericTlb r_iotlb; - - + + ///////////////////////// // FIFOs @@ -392,5 +405,5 @@ GenericFifo m_dma_rsp_reop_fifo; GenericFifo m_dma_rsp_rerror_fifo; - + // output FIFO to VCI INI port on IOX network (VCI command) GenericFifo m_config_cmd_addr_fifo; @@ -408,6 +421,6 @@ GenericFifo m_config_cmd_cfixed_fifo; GenericFifo m_config_cmd_clen_fifo; - - // output FIFO to VCI TGT port on INT network (VCI response) + + // output FIFO to VCI TGT port on INT network (VCI response) GenericFifo m_config_rsp_data_fifo; GenericFifo m_config_rsp_rsrcid_fifo; @@ -416,5 +429,5 @@ GenericFifo m_config_rsp_reop_fifo; GenericFifo m_config_rsp_rerror_fifo; - + // output FIFO to VCI_INI port on INT network (VCI command) GenericFifo m_miss_wti_cmd_addr_fifo; @@ -432,16 +445,16 @@ GenericFifo m_miss_wti_cmd_cfixed_fifo; GenericFifo m_miss_wti_cmd_clen_fifo; - + //////////////////////////////// // Activity counters //////////////////////////////// - + uint32_t m_cpt_total_cycles; // total number of cycles - + // TLB activity counters uint32_t m_cpt_iotlb_read; // number of iotlb read uint32_t m_cpt_iotlb_miss; // number of iotlb miss uint32_t m_cost_iotlb_miss; // number of wait cycles (not treatment itself) - uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions + uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions uint32_t m_cost_iotlbmiss_transaction; // cumulated duration tlb miss transactions @@ -454,11 +467,11 @@ // FSM activity counters // unused on print_stats - uint32_t m_cpt_fsm_dma_cmd [32]; - uint32_t m_cpt_fsm_dma_rsp [32]; - uint32_t m_cpt_fsm_tlb [32]; - uint32_t m_cpt_fsm_config_cmd [32]; - uint32_t m_cpt_fsm_config_rsp [32]; + uint32_t m_cpt_fsm_dma_cmd [32]; + uint32_t m_cpt_fsm_dma_rsp [32]; + uint32_t m_cpt_fsm_tlb [32]; + uint32_t m_cpt_fsm_config_cmd [32]; + uint32_t m_cpt_fsm_config_rsp [32]; uint32_t m_cpt_fsm_miss_wti_rsp [32]; - + protected: @@ -468,16 +481,17 @@ VciIoBridge( - sc_module_name insname, - const soclib::common::MappingTable &mt_ext, // external network - const soclib::common::MappingTable &mt_int, // internal network - const soclib::common::MappingTable &mt_iox, // iox network - const soclib::common::IntTab &int_tgtid, // INT network TGTID - const soclib::common::IntTab &int_srcid, // INT network SRCID - const soclib::common::IntTab &iox_tgtid, // IOX network TGTID - const size_t dcache_words, - const size_t iotlb_ways, - const size_t iotlb_sets, - const uint32_t debug_start_cycle, - const bool debug_ok ); + sc_module_name insname, + const soclib::common::MappingTable &mt_ext, // external network + const soclib::common::MappingTable &mt_int, // internal network + const soclib::common::MappingTable &mt_iox, // iox network + const soclib::common::IntTab &int_tgtid, // INT network TGTID + const soclib::common::IntTab &int_srcid, // INT network SRCID + const soclib::common::IntTab &iox_tgtid, // IOX network TGTID + const soclib::common::IntTab &iox_srcid, // IOX network SRCID + const size_t dcache_words, + const size_t iotlb_ways, + const size_t iotlb_sets, + const uint32_t debug_start_cycle, + const bool debug_ok ); ~VciIoBridge(); @@ -486,5 +500,5 @@ void clear_stats(); void print_trace(size_t mode = 0); - + private: Index: /trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp =================================================================== --- /trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 714) +++ /trunk/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 715) @@ -5,21 +5,21 @@ * * SOCLIB_LGPL_HEADER_BEGIN - * + * * This file is part of SoCLib, GNU LGPLv2.1. - * + * * SoCLib is free software; you can redistribute it and/or modify it * under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation; version 2.1 of the License. - * + * * SoCLib is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with SoCLib; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA * 02110-1301 USA - * + * * SOCLIB_LGPL_HEADER_END */ @@ -38,17 +38,17 @@ ///////////////////////////////////////////////////////////////////////////////// -#define DEBUG_DMA_CMD 1 -#define DEBUG_DMA_RSP 1 -#define DEBUG_TLB_MISS 1 -#define DEBUG_CONFIG_CMD 1 -#define DEBUG_CONFIG_RSP 1 -#define DEBUG_MISS_WTI_CMD 1 - -namespace soclib { +#define DEBUG_DMA_CMD 1 +#define DEBUG_DMA_RSP 1 +#define DEBUG_TLB_MISS 1 +#define DEBUG_CONFIG_CMD 1 +#define DEBUG_CONFIG_RSP 1 +#define DEBUG_MISS_WTI_CMD 1 + +namespace soclib { namespace caba { namespace { -const char *dma_cmd_fsm_state_str[] = +const char *dma_cmd_fsm_state_str[] = { "DMA_CMD_IDLE", @@ -61,5 +61,5 @@ }; -const char *dma_rsp_fsm_state_str[] = +const char *dma_rsp_fsm_state_str[] = { "DMA_RSP_IDLE_DMA", @@ -71,5 +71,5 @@ }; -const char *tlb_fsm_state_str[] = +const char *tlb_fsm_state_str[] = { "TLB_IDLE", @@ -78,5 +78,5 @@ "TLB_PTE1_SELECT", "TLB_PTE1_UPDT", - "TLB_PTE2_GET", + "TLB_PTE2_GET", "TLB_PTE2_SELECT", "TLB_PTE2_UPDT", @@ -86,24 +86,25 @@ }; -const char *config_cmd_fsm_state_str[] = +const char *config_cmd_fsm_state_str[] = { "CONFIG_CMD_IDLE", - "CONFIG_CMD_NEXT", + "CONFIG_CMD_HI", + "CONFIG_CMD_LO", "CONFIG_CMD_PUT", "CONFIG_CMD_RSP", }; -const char *config_rsp_fsm_state_str[] = +const char *config_rsp_fsm_state_str[] = { "CONFIG_RSP_IDLE_IOX", "CONFIG_RSP_IDLE_LOC", - "CONFIG_RSP_PUT_LOW", - "CONFIG_RSP_PUT_HI", - "CONFIG_RSP_PUT_UNC", - "CONFIG_RSP_PUT_LOC", + "CONFIG_RSP_PUT_LO", + "CONFIG_RSP_PUT_HI", + "CONFIG_RSP_PUT_UNC", + "CONFIG_RSP_PUT_LOC", }; -const char *miss_wti_rsp_state_str[] = - { +const char *miss_wti_rsp_state_str[] = + { "MISS_WTI_RSP_IDLE", "MISS_WTI_RSP_WTI_IOX", @@ -117,16 +118,17 @@ //////////////////////// tmpl(/**/)::VciIoBridge( - sc_module_name name, - const soclib::common::MappingTable &mt_ext, - const soclib::common::MappingTable &mt_int, - const soclib::common::MappingTable &mt_iox, - const soclib::common::IntTab &int_tgtid, // INT network TGTID - const soclib::common::IntTab &int_srcid, // INT network SRCID - const soclib::common::IntTab &iox_tgtid, // IOX network TGTID + sc_module_name name, + const soclib::common::MappingTable &mt_ext, + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_iox, + const soclib::common::IntTab &int_tgtid, // INT network TGTID + const soclib::common::IntTab &int_srcid, // INT network SRCID + const soclib::common::IntTab &iox_tgtid, // IOX network TGTID + const soclib::common::IntTab &iox_srcid, // IOX network SRCID const size_t dcache_words, - const size_t iotlb_ways, - const size_t iotlb_sets, - const uint32_t debug_start_cycle, - const bool debug_ok) + const size_t iotlb_ways, + const size_t iotlb_sets, + const uint32_t debug_start_cycle, + const bool debug_ok) : soclib::caba::BaseModule(name), @@ -143,6 +145,12 @@ // INT & IOX Network m_int_seglist( mt_int.getSegmentList( int_tgtid )), - m_int_srcid( mt_int.indexForId( int_srcid )), + m_int_srcid( mt_int.indexForId( int_srcid )), m_iox_seglist( mt_iox.getSegmentList( iox_tgtid )), + m_iox_srcid( mt_iox.indexForId( iox_srcid )), + + m_srcid_gid_mask( mt_int.getSrcidLevelBits()[0], // use global bits + mt_int.getSrcidLevelBits()[1]), // drop local bits + m_srcid_lid_mask( mt_int.getSrcidLevelBits()[1], // use local bits + 0), m_iotlb_ways(iotlb_ways), @@ -176,12 +184,12 @@ r_dma_cmd_to_dma_rsp_rtrdid("r_dma_cmd_to_dma_rsp_rtrdid"), r_dma_cmd_to_dma_rsp_rpktid("r_dma_cmd_to_dma_rsp_rpktid"), - + r_dma_cmd_to_tlb_req("r_dma_cmd_to_tlb_req"), r_dma_cmd_to_tlb_vaddr("r_dma_cmd_to_tlb_vaddr"), - + //DMA_RSP FSM registers r_dma_rsp_fsm("r_dma_rsp_fsm"), - // CONFIG_CMD FSM registers + // CONFIG_CMD FSM registers r_config_cmd_fsm("r_config_cmd_fsm"), @@ -192,4 +200,7 @@ r_config_cmd_to_config_rsp_rerror("r_config_cmd_to_config_rsp_rerror"), r_config_cmd_to_config_rsp_rdata("r_config_cmd_to_config_rsp_rdata"), + r_config_cmd_to_config_rsp_rsrcid("r_config_cmd_to_config_rsp_rsrcid"), + r_config_cmd_to_config_rsp_rtrdid("r_config_cmd_to_config_rsp_rtrdid"), + r_config_cmd_to_config_rsp_rpktid("r_config_cmd_to_config_rsp_rpktid"), r_config_cmd_wdata("r_config_cmd_wdata"), @@ -198,6 +209,6 @@ r_config_cmd_address("r_config_cmd_address"), r_config_cmd_srcid("r_config_cmd_srcid"), + r_config_cmd_trdid("r_config_cmd_trdid"), r_config_cmd_pktid("r_config_cmd_pktid"), - r_config_cmd_trdid("r_config_cmd_trdid"), r_config_cmd_plen("r_config_cmd_plen"), r_config_cmd_clen("r_config_cmd_clen"), @@ -208,6 +219,11 @@ r_config_cmd_eop("r_config_cmd_eop"), - // CONFIG_RSP FSM registers + // ID translation table used by CONFIG_CMD and CONFIG_RSP FSMs + m_iox_transaction_tab(1), + + // CONFIG_RSP FSM registers r_config_rsp_fsm("r_config_rsp_fsm"), + r_config_rsp_rsrcid("r_config_rsp_rsrcid"), + r_config_rsp_rtrdid("r_config_rsp_rtrdid"), // TLB FSM registers @@ -217,10 +233,10 @@ r_tlb_miss_error("r_tlb_miss_error"), - r_tlb_paddr("r_tlb_paddr"), + r_tlb_paddr("r_tlb_paddr"), r_tlb_pte_flags("r_tlb_pte_flags"), r_tlb_pte_ppn("r_tlb_pte_ppn"), r_tlb_way("r_tlb_way"), - r_tlb_set("r_tlb_set"), - + r_tlb_set("r_tlb_set"), + r_tlb_buf_valid("r_tlb_buf_valid"), r_tlb_buf_tag("r_tlb_buf_tag"), @@ -231,5 +247,5 @@ // MISS_WTI_RSP FSM registers - r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), + r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), r_miss_wti_rsp_error_wti("r_miss_wti_rsp_error_wti"), r_miss_wti_rsp_error_miss("r_miss_wti_rsp_error_miss"), @@ -244,20 +260,20 @@ // TLB for IOMMU r_iotlb("iotlb", 0, iotlb_ways, iotlb_sets, vci_param_int::N), - + // DMA_CMD FIFOs m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",2), - m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",2), - m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",2), - m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",2), - m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",2), - m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",2), - m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",2), - m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",2), + m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",2), + m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",2), + m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",2), + m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",2), + m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",2), + m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",2), + m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",2), m_dma_cmd_eop_fifo("m_dma_cmd_eop_fifo",2), - m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",2), - m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",2), - m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",2), + m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",2), + m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",2), + m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",2), m_dma_cmd_cfixed_fifo("m_dma_cmd_cfixed_fifo",2), - m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",2), + m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",2), // DMA_RSP FIFOs @@ -268,5 +284,5 @@ m_dma_rsp_reop_fifo("m_dma_rsp_reop_fifo",2), m_dma_rsp_rerror_fifo("m_dma_rsp_rerror_fifo",2), - + // CONFIG_CMD FIFOs m_config_cmd_addr_fifo("m_config_cmd_addr_fifo",2), @@ -286,5 +302,5 @@ // CONFIG_RSP FIFOs - m_config_rsp_data_fifo("m_config_rsp_data_fifo",2), + m_config_rsp_data_fifo("m_config_rsp_data_fifo",2), m_config_rsp_rsrcid_fifo("m_config_rsp_rsrcid_fifo",2), m_config_rsp_rtrdid_fifo("m_config_rsp_rtrdid_fifo",2), @@ -311,5 +327,5 @@ std::cout << " - Building VciIoBridge : " << name << std::endl; - // checking segments on INT network + // checking segments on INT network assert ( ( not m_int_seglist.empty() ) and "VCI_IO_BRIDGE ERROR : no segment allocated on INT network"); @@ -320,9 +336,9 @@ std::cout << " => segment " << int_seg->name() << " / base = " << std::hex << int_seg->baseAddress() - << " / size = " << int_seg->size() - << " / special = " << int_seg->special() << std::endl; - } - - // checking segments on IOX network + << " / size = " << int_seg->size() + << " / special = " << int_seg->special() << std::endl; + } + + // checking segments on IOX network assert ( ( not m_iox_seglist.empty() ) and "VCI_IO_BRIDGE ERROR : no segment allocated on IOX network"); @@ -333,8 +349,8 @@ std::cout << " => segment " << iox_seg->name() << " / base = " << std::hex << iox_seg->baseAddress() - << " / size = " << iox_seg->size() << std::endl; - } - - assert( (vci_param_int::N == vci_param_ext::N) and + << " / size = " << iox_seg->size() << std::endl; + } + + assert( (vci_param_int::N == vci_param_ext::N) and "VCI_IO_BRIDGE ERROR: VCI ADDRESS widths must be equal on the 3 networks"); @@ -343,8 +359,8 @@ assert( (vci_param_int::B == 4) and - "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 bits on internal network"); + "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 bits on internal network"); assert( (vci_param_ext::B == 8) and - "VCI_IO_BRIDGE ERROR: VCI DATA width must be 64 bits on external network"); + "VCI_IO_BRIDGE ERROR: VCI DATA width must be 64 bits on external network"); assert( (vci_param_int::S == vci_param_ext::S) and @@ -357,5 +373,5 @@ dont_initialize(); sensitive << p_clk.pos(); - + SC_METHOD(genMoore); dont_initialize(); @@ -392,4 +408,10 @@ r_iotlb.printTrace(); } + + if(mode & 0x02) + { + std::cout << " IOX TRANSACTION TAB" << std::endl; + m_iox_transaction_tab.printTrace(); + } } @@ -398,9 +420,14 @@ //////////////////////// { - std::cout << name() << std::endl - << "- IOTLB MISS RATE = " << (float)m_cpt_iotlb_miss/m_cpt_iotlb_read << std::endl - << "- IOTLB MISS COST = " << (float)m_cost_iotlb_miss/m_cpt_iotlb_miss << std::endl - << "- IOTLB MISS TRANSACTION COST = " << (float)m_cost_iotlbmiss_transaction/m_cpt_iotlbmiss_transaction << std::endl - << "- IOTLB MISS TRANSACTION RATE (OVER ALL MISSES) = " << (float)m_cpt_iotlbmiss_transaction/m_cpt_iotlb_miss << std::endl; + std::cout << name() + << "\n- IOTLB MISS RATE = " + << (float)m_cpt_iotlb_miss/m_cpt_iotlb_read + << "\n- IOTLB MISS COST = " + << (float)m_cost_iotlb_miss/m_cpt_iotlb_miss + << "\n- IOTLB MISS TRANSACTION COST = " + << (float)m_cost_iotlbmiss_transaction/m_cpt_iotlbmiss_transaction + << "\n- IOTLB MISS TRANSACTION RATE (OVER ALL MISSES) = " + << (float)m_cpt_iotlbmiss_transaction/m_cpt_iotlb_miss + << std::endl; } @@ -409,9 +436,9 @@ //////////////////////// { - m_cpt_iotlb_read = 0; - m_cpt_iotlb_miss = 0; + m_cpt_iotlb_read = 0; + m_cpt_iotlb_miss = 0; m_cost_iotlb_miss = 0; - m_cpt_iotlbmiss_transaction = 0; - m_cost_iotlbmiss_transaction = 0; + m_cpt_iotlbmiss_transaction = 0; + m_cost_iotlbmiss_transaction = 0; } @@ -420,8 +447,12 @@ //////////////////////////////////// { - uint32_t addr32 = (uint32_t)paddr; - uint32_t base = r_xicu_base.read(); - uint32_t size = r_xicu_size.read(); - return ( (addr32 >= base) and (addr32 < (base + size)) ); + std::list::iterator seg; + for ( seg = m_iox_seglist.begin() ; + seg != m_iox_seglist.end() ; + seg++ ) + { + if ( seg->contains(paddr) ) return seg->special(); + } + return false; } @@ -430,19 +461,19 @@ ///////////////////////// { - if ( not p_resetn.read() ) - { - r_dma_cmd_fsm = DMA_CMD_IDLE; - r_dma_rsp_fsm = DMA_RSP_IDLE_DMA; - r_tlb_fsm = TLB_IDLE; + if ( not p_resetn.read() ) + { + r_dma_cmd_fsm = DMA_CMD_IDLE; + r_dma_rsp_fsm = DMA_RSP_IDLE_DMA; + r_tlb_fsm = TLB_IDLE; r_config_cmd_fsm = CONFIG_CMD_IDLE; r_config_rsp_fsm = CONFIG_RSP_IDLE_IOX; r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; - r_tlb_buf_valid = false; - r_iommu_active = false; - r_iommu_wti_enable = false; - - r_xicu_size = 0; - r_xicu_base = 0; + r_tlb_buf_valid = false; + r_iommu_active = false; + r_iommu_wti_enable = false; + + // initializing translation table + m_iox_transaction_tab.init(); // initializing FIFOs @@ -461,5 +492,5 @@ m_dma_cmd_cfixed_fifo.init(); m_dma_cmd_clen_fifo.init(); - + m_dma_rsp_rsrcid_fifo.init(); m_dma_rsp_rtrdid_fifo.init(); @@ -468,5 +499,5 @@ m_dma_rsp_rerror_fifo.init(); m_dma_rsp_reop_fifo.init(); - + m_config_cmd_addr_fifo.init(); m_config_cmd_srcid_fifo.init(); @@ -483,5 +514,5 @@ m_config_cmd_cfixed_fifo.init(); m_config_cmd_clen_fifo.init(); - + m_miss_wti_cmd_addr_fifo.init(); m_miss_wti_cmd_srcid_fifo.init(); @@ -498,5 +529,5 @@ m_miss_wti_cmd_cfixed_fifo.init(); m_miss_wti_cmd_clen_fifo.init(); - + m_config_rsp_rsrcid_fifo.init(); m_config_rsp_rtrdid_fifo.init(); @@ -505,10 +536,10 @@ m_config_rsp_rerror_fifo.init(); m_config_rsp_reop_fifo.init(); - - // SET/RESET Communication flip-flops + + // SET/RESET Communication flip-flops r_dma_cmd_to_miss_wti_cmd_req = false; r_dma_cmd_to_dma_rsp_req = false; - r_dma_cmd_to_tlb_req = false; - r_config_cmd_to_tlb_req = false; + r_dma_cmd_to_tlb_req = false; + r_config_cmd_to_tlb_req = false; r_config_cmd_to_config_rsp_req = false; r_tlb_to_miss_wti_cmd_req = false; @@ -520,13 +551,13 @@ // Debug variable - m_debug_activated = false; - - // activity counters - m_cpt_total_cycles = 0; - m_cpt_iotlb_read = 0; - m_cpt_iotlb_miss = 0; - m_cpt_iotlbmiss_transaction = 0; - m_cost_iotlbmiss_transaction = 0; - + m_debug_activated = false; + + // activity counters + m_cpt_total_cycles = 0; + m_cpt_iotlb_read = 0; + m_cpt_iotlb_miss = 0; + m_cpt_iotlbmiss_transaction = 0; + m_cost_iotlbmiss_transaction = 0; + m_cpt_trt_dma_full = 0; m_cpt_trt_dma_full_cost = 0; @@ -547,6 +578,7 @@ bool dma_cmd_fifo_put = false; bool dma_cmd_fifo_get = p_vci_ini_ram.cmdack.read(); - - bool dma_rsp_fifo_put = false; + vci_srcid_t dma_cmd_fifo_srcid = 0; + + bool dma_rsp_fifo_put = false; bool dma_rsp_fifo_get = p_vci_tgt_iox.rspack.read(); vci_rerror_t dma_rsp_fifo_rerror = 0; @@ -579,9 +611,9 @@ #ifdef INSTRUMENTATION - m_cpt_fsm_dma_cmd [r_dma_cmd_fsm.read()] ++; - m_cpt_fsm_dma_rsp [r_dma_rsp_fsm.read() ] ++; - m_cpt_fsm_tlb [r_tlb_fsm.read() ] ++; - m_cpt_fsm_config_cmd [r_config_cmd_fsm.read() ] ++; - m_cpt_fsm_config_rsp [r_config_rsp_fsm.read() ] ++; + m_cpt_fsm_dma_cmd [r_dma_cmd_fsm.read()] ++; + m_cpt_fsm_dma_rsp [r_dma_rsp_fsm.read() ] ++; + m_cpt_fsm_tlb [r_tlb_fsm.read() ] ++; + m_cpt_fsm_config_cmd [r_config_cmd_fsm.read() ] ++; + m_cpt_fsm_config_rsp [r_config_rsp_fsm.read() ] ++; m_cpt_fsm_miss_wti_rsp [r_miss_wti_rsp_fsm.read() ] ++; #endif @@ -607,5 +639,5 @@ /////////////////////////////////////////////////////////////////////////////// - switch( r_dma_cmd_fsm.read() ) + switch( r_dma_cmd_fsm.read() ) { ////////////////// @@ -614,7 +646,7 @@ // no VCI flit is consumed in this state { - if ( p_vci_tgt_iox.cmdval.read() ) - { - if ( not r_iommu_active.read() ) // tlb not activated + if ( p_vci_tgt_iox.cmdval.read() ) + { + if ( not r_iommu_active.read() ) // tlb not activated { // save paddr address @@ -625,5 +657,5 @@ if ( is_wti( p_vci_tgt_iox.address.read() ) ) { - assert( p_vci_tgt_iox.eop.read() and + assert( p_vci_tgt_iox.eop.read() and "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); @@ -637,5 +669,6 @@ #if DEBUG_DMA_CMD if( m_debug_activated ) -std::cout << " DMA command" +std::cout << name() + << " DMA command" << " : address = " << std::hex << p_vci_tgt_iox.address.read() << " / srcid = " << p_vci_tgt_iox.srcid.read() @@ -646,12 +679,12 @@ } else if (r_tlb_fsm.read() == TLB_IDLE || - r_tlb_fsm.read() == TLB_WAIT ) // tlb access possible - { - vci_addr_t iotlb_paddr; - pte_info_t iotlb_flags; - size_t iotlb_way; + r_tlb_fsm.read() == TLB_WAIT ) // tlb access possible + { + vci_addr_t iotlb_paddr; + pte_info_t iotlb_flags; + size_t iotlb_way; size_t iotlb_set; vci_addr_t iotlb_nline; - bool iotlb_hit; + bool iotlb_hit; #ifdef INSTRUMENTATION @@ -662,17 +695,17 @@ &iotlb_flags, &iotlb_nline, // unused - &iotlb_way, // unused + &iotlb_way, // unused &iotlb_set ); // unused - - if ( iotlb_hit ) // tlb hit - { - if ( not iotlb_flags.w and // access right violation - (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) + + if ( iotlb_hit ) // tlb hit + { + if ( not iotlb_flags.w and // access right violation + (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) { // register error - r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; + r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; r_iommu_bvar = p_vci_tgt_iox.address.read(); r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); - + // prepare response error request to DMA_RSP FSM r_dma_cmd_to_dma_rsp_rsrcid = p_vci_tgt_iox.srcid.read(); @@ -684,5 +717,6 @@ #if DEBUG_DMA_CMD if( m_debug_activated ) -std::cout << " TLB HIT but writable violation" << std::endl; +std::cout << name() + << " TLB HIT but writable violation" << std::endl; #endif } @@ -691,5 +725,6 @@ #if DEBUG_DMA_CMD if( m_debug_activated ) -std::cout << " TLB HIT" << std::endl; +std::cout << name() + << " TLB HIT" << std::endl; #endif // save paddr address @@ -699,9 +734,9 @@ if ( is_wti( iotlb_paddr ) ) { - assert( p_vci_tgt_iox.eop.read() and + assert( p_vci_tgt_iox.eop.read() and (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); - r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ; + r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ; } else @@ -717,13 +752,14 @@ m_cpt_iotlb_miss++; #endif - // register virtual address, and send request to TLB FSM - r_dma_cmd_to_tlb_vaddr = p_vci_tgt_iox.address.read(); + // register virtual address, and send request to TLB FSM + r_dma_cmd_to_tlb_vaddr = p_vci_tgt_iox.address.read(); r_dma_cmd_to_tlb_req = true; r_dma_cmd_fsm = DMA_CMD_TLB_MISS_WAIT; #if DEBUG_DMA_CMD if( m_debug_activated ) -std::cout << " TLB MISS" << std::endl; -#endif - } // end tlb miss +std::cout << name() + << " TLB MISS" << std::endl; +#endif + } // end tlb miss } // end if tlb_activated } // end if cmdval @@ -732,22 +768,35 @@ ///////////////////// case DMA_CMD_DMA_REQ: // put a flit in DMA_CMD FIFO - // if contig, VCI address must be incremented + // if contig, VCI address must be incremented // after initial translation by IOMMU. // flit is consumed if DMA_CMD FIFO not full { - if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) - { - dma_cmd_fifo_put = true; - - if ( p_vci_tgt_iox.contig.read() ) r_dma_cmd_paddr = r_dma_cmd_paddr.read() + - vci_param_ext::B; - - if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_IDLE; - + if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) + { + // SRCID in RAM network is the concatenation of the IO bridge + // cluster id with the DMA peripheral local id + assert((m_srcid_gid_mask[p_vci_tgt_iox.srcid.read()] == 0) && + "error: external DMA peripherals global id must be 0"); + + dma_cmd_fifo_srcid = (m_srcid_gid_mask.mask() & m_int_srcid) | + p_vci_tgt_iox.srcid.read(); + dma_cmd_fifo_put = true; + + if ( p_vci_tgt_iox.contig.read() ) + { + r_dma_cmd_paddr = r_dma_cmd_paddr.read() + vci_param_ext::B; + } + + if ( p_vci_tgt_iox.eop.read() ) + { + r_dma_cmd_fsm = DMA_CMD_IDLE; + } + #if DEBUG_DMA_CMD -if( m_debug_activated ) -std::cout << " Push into DMA_CMD fifo:" +if( m_debug_activated ) +std::cout << name() + << " Push into DMA_CMD fifo:" << " address = " << std::hex << r_dma_cmd_paddr.read() - << " srcid = " << p_vci_tgt_iox.srcid.read() + << " srcid = " << dma_cmd_fifo_srcid << " wdata = " << p_vci_tgt_iox.wdata.read() << " plen = " << std::dec << p_vci_tgt_iox.plen.read() @@ -758,26 +807,35 @@ } ///////////////////////// - case DMA_CMD_WTI_IOX_REQ: // post a WTI_IOX request to MISS_WTI FSM + case DMA_CMD_WTI_IOX_REQ: // post a WTI_IOX request to MISS_WTI FSM // if no prending previous request - // command arguments are stored in dedicated registers + // command arguments are stored in dedicated registers // VCI flit is consumed if no previous request { if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no previous pending request { + // SRCID in INT network for WTI transactions is the concatenation + // of the IO bridge cluster id with the DMA peripheral local id + assert((m_srcid_gid_mask[p_vci_tgt_iox.srcid.read()] == 0) && + "error: external DMA peripherals global id must be 0"); + + vci_srcid_t wti_srcid = (m_srcid_gid_mask.mask() & m_int_srcid) | + p_vci_tgt_iox.srcid.read(); + r_dma_cmd_to_miss_wti_cmd_req = true; r_dma_cmd_to_miss_wti_cmd_addr = p_vci_tgt_iox.address.read(); r_dma_cmd_to_miss_wti_cmd_cmd = p_vci_tgt_iox.cmd.read(); r_dma_cmd_to_miss_wti_cmd_wdata = (uint32_t)p_vci_tgt_iox.wdata.read(); - r_dma_cmd_to_miss_wti_cmd_srcid = p_vci_tgt_iox.srcid.read(); + r_dma_cmd_to_miss_wti_cmd_srcid = wti_srcid; r_dma_cmd_to_miss_wti_cmd_trdid = p_vci_tgt_iox.trdid.read(); r_dma_cmd_to_miss_wti_cmd_pktid = PKTID_WTI_IOX; r_dma_cmd_fsm = DMA_CMD_IDLE; - + #if DEBUG_DMA_CMD -if( m_debug_activated ) -std::cout << " request WTI transaction from ext peripheral" +if( m_debug_activated ) +std::cout << name() + << " request WTI transaction from ext peripheral" << " : address = " << std::hex << r_dma_cmd_paddr.read() - << " / srcid = " << p_vci_tgt_iox.srcid.read() + << " / srcid = " << wti_srcid << " / wdata = " << p_vci_tgt_iox.wdata.read() << std::endl; #endif @@ -786,5 +844,5 @@ } ////////////////////////// - case DMA_CMD_ERR_WAIT_EOP: // wait EOP before requesting WTI & error response + case DMA_CMD_ERR_WAIT_EOP: // wait EOP before requesting WTI & error response // VCI flit is always consumed { @@ -792,15 +850,16 @@ #if DEBUG_DMA_CMD -if( m_debug_activated ) -std::cout << " wait EOP for faulty DMA command" << std::endl; -#endif - break; - } - +if( m_debug_activated ) +std::cout << name() + << " wait EOP for faulty DMA command" << std::endl; +#endif + break; + } + ///////////////////////// - case DMA_CMD_ERR_WTI_REQ: // post a WTI_MMU request to MISS_WTI_CMD FSM + case DMA_CMD_ERR_WTI_REQ: // post a WTI_MMU request to MISS_WTI_CMD FSM // if no prending previous request // response arguments are stored in dedicated registers - // no VCI flit is consumed + // no VCI flit is consumed { if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no pending previous request @@ -817,6 +876,7 @@ #if DEBUG_DMA_CMD -if( m_debug_activated ) -std::cout << " request an IOMMU WTI" << std::endl; +if( m_debug_activated ) +std::cout << name() + << " request an IOMMU WTI" << std::endl; #endif } @@ -827,5 +887,5 @@ // if no prending previous request // response arguments are stored in dedicated registers - // no VCI flit is consumed + // no VCI flit is consumed { if ( not r_dma_cmd_to_dma_rsp_req.read() ) // no pending previous request @@ -839,5 +899,5 @@ /////////////////////////// case DMA_CMD_TLB_MISS_WAIT: // waiting completion of a TLB miss - // we must test a possible page fault error... + // we must test a possible page fault error... { if ( not r_dma_cmd_to_tlb_req.read() ) // TLB miss completed @@ -845,5 +905,5 @@ if ( r_tlb_miss_error.read() ) // Error reported by TLB FSM { - r_iommu_etr = MMU_READ_PT2_UNMAPPED; + r_iommu_etr = MMU_READ_PT2_UNMAPPED; r_iommu_bvar = r_dma_cmd_to_tlb_vaddr.read(); r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); @@ -872,9 +932,9 @@ if ( m_dma_rsp_rerror_fifo.wok() ) { - switch( r_dma_rsp_fsm.read() ) + switch( r_dma_rsp_fsm.read() ) { ////////////////////// case DMA_RSP_IDLE_DMA: // normal DMA response has highest priority - { + { if (p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; @@ -884,6 +944,6 @@ ////////////////////// case DMA_RSP_IDLE_WTI: // normal WTI response has highest priority - { - if (r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + { + if (r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; else if(r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; @@ -892,17 +952,17 @@ ////////////////////// case DMA_RSP_IDLE_ERR: // error response has highest priority - { + { if (r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; - else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; break; } /////////////////////// case DMA_RSP_PUT_DMA: // put one flit of the DMA response into FIFO - { + { dma_rsp_fifo_put = true; dma_rsp_fifo_rerror = p_vci_ini_ram.rerror.read(); dma_rsp_fifo_rdata = p_vci_ini_ram.rdata.read(); - dma_rsp_fifo_rsrcid = p_vci_ini_ram.rsrcid.read(); + dma_rsp_fifo_rsrcid = m_srcid_lid_mask[p_vci_ini_ram.rsrcid.read()]; dma_rsp_fifo_rtrdid = p_vci_ini_ram.rtrdid.read(); dma_rsp_fifo_rpktid = p_vci_ini_ram.rpktid.read(); @@ -913,7 +973,9 @@ #if DEBUG_DMA_RSP -if( m_debug_activated ) -std::cout << " Push DMA response into DMA_RSP FIFO" - << " : rsrcid = " << std::hex << p_vci_ini_ram.rsrcid.read() +if( m_debug_activated ) +std::cout << name() + << " Push DMA response into DMA_RSP FIFO" + << std::hex + << " : rsrcid = " << m_srcid_lid_mask[p_vci_ini_ram.rsrcid.read()] << " / rtrdid = " << p_vci_ini_ram.rtrdid.read() << " / rpktid = " << p_vci_ini_ram.rpktid.read() @@ -923,12 +985,13 @@ #endif break; - } + } /////////////////////// case DMA_RSP_PUT_WTI: // put single flit WTI response into FIFO - { + { dma_rsp_fifo_put = true; dma_rsp_fifo_rerror = r_miss_wti_rsp_to_dma_rsp_rerror.read(); dma_rsp_fifo_rdata = 0; - dma_rsp_fifo_rsrcid = r_miss_wti_rsp_to_dma_rsp_rsrcid.read(); + dma_rsp_fifo_rsrcid = + m_srcid_lid_mask[r_miss_wti_rsp_to_dma_rsp_rsrcid.read()]; dma_rsp_fifo_rtrdid = r_miss_wti_rsp_to_dma_rsp_rtrdid.read(); dma_rsp_fifo_rpktid = r_miss_wti_rsp_to_dma_rsp_rpktid.read(); @@ -937,12 +1000,14 @@ // acknowledge request r_miss_wti_rsp_to_dma_rsp_req = false; - + // update priority r_dma_rsp_fsm = DMA_RSP_IDLE_ERR; #if DEBUG_DMA_RSP -if( m_debug_activated ) -std::cout << " Push WTI response into DMA_RSP FIFO" - << " : rsrcid = " << std::hex << r_miss_wti_rsp_to_dma_rsp_rsrcid.read() +if( m_debug_activated ) +std::cout << name() + << " Push WTI response into DMA_RSP FIFO" + << std::hex + << " : rsrcid = " << m_srcid_lid_mask[r_miss_wti_rsp_to_dma_rsp_rsrcid.read()] << " / rtrdid = " << r_miss_wti_rsp_to_dma_rsp_rtrdid.read() << " / rpktid = " << r_miss_wti_rsp_to_dma_rsp_rpktid.read() @@ -966,11 +1031,12 @@ // acknowledge request r_dma_cmd_to_dma_rsp_req = false; - + // update priority r_dma_rsp_fsm = DMA_RSP_PUT_DMA; #if DEBUG_DMA_RSP -if( m_debug_activated ) -std::cout << " Push IOMMU ERROR response into DMA_RSP FIFO" +if( m_debug_activated ) +std::cout << name() + << " Push IOMMU ERROR response into DMA_RSP FIFO" << " : rsrcid = " << std::hex << r_dma_cmd_to_dma_rsp_rsrcid.read() << " / rtrdid = " << r_dma_cmd_to_dma_rsp_rtrdid.read() @@ -982,5 +1048,5 @@ break; } - } // end switch DMA_RSP FSM + } // end switch DMA_RSP FSM } // end if FIFO full @@ -989,5 +1055,5 @@ // The TLB FSM handles the TLB miss requests from DMA_CMD FSM, // and the PTE inval request (from CONFIG_CMD FSM). - // PTE inval request have highest priority. In case of TLB miss, + // PTE inval request have highest priority. In case of TLB miss, // this fsm searchs the requested PTE on the prefetch buffer. // In case of buffer miss, it request the MISS_WTI FSM to access the memory. @@ -1003,5 +1069,5 @@ // PTE inval request are handled as unmaskable interrupts { - if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation + if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation { r_config_cmd_to_tlb_req = false; @@ -1010,5 +1076,5 @@ } - else if ( r_dma_cmd_to_tlb_req.read() ) // request for a TLB Miss + else if ( r_dma_cmd_to_tlb_req.read() ) // request for a TLB Miss { // Checking prefetch buffer @@ -1016,40 +1082,42 @@ { if( r_tlb_buf_valid && // Hit on prefetch buffer - (r_tlb_buf_vaddr.read() == + (r_tlb_buf_vaddr.read() == (r_dma_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) { - size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; + size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; uint32_t pte_flags = r_tlb_buf_data[2*pte_offset]; - uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; - + uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; + // Bit valid checking - if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped { - std::cout << "VCI_IO_BRIDGE ERROR : " << name() + std::cout << "VCI_IO_BRIDGE ERROR : " << name() << " Page Table entry unmapped" << std::endl; - + r_tlb_miss_error = true; r_dma_cmd_to_tlb_req = false; #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " PTE2 Unmapped" << std::hex +std::cout << name() + << " PTE2 Unmapped" << std::hex << " / paddr = " << r_tlb_paddr.read() << " / PTE_FLAGS = " << pte_flags << " / PTE_PPN = " << pte_ppn << std::endl; #endif - break; + break; } // valid PTE2 : we must update the TLB - r_tlb_pte_flags = pte_flags; + r_tlb_pte_flags = pte_flags; r_tlb_pte_ppn = pte_ppn; r_tlb_fsm = TLB_PTE2_SELECT; #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Hit on prefetch buffer: PTE2" << std::hex - << " / PTE_FLAGS = " << pte_flags +std::cout << name() + << " Hit on prefetch buffer: PTE2" << std::hex + << " / PTE_FLAGS = " << pte_flags << " / PTE_PPN = " << pte_ppn << std::endl; #endif - break; + break; } } @@ -1057,25 +1125,26 @@ { if( r_tlb_buf_valid && // Hit on prefetch buffer - (r_tlb_buf_vaddr.read() == - (r_dma_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) - { - size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; + (r_tlb_buf_vaddr.read() == + (r_dma_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) + { + size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; uint32_t pte_flags = r_tlb_buf_data[pte_offset]; - + // Bit valid checking - if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped { - std::cout << "VCI_IO_BRIDGE ERROR : " << name() + std::cout << "VCI_IO_BRIDGE ERROR : " << name() << " Page Table entry unmapped" << std::endl; - + r_tlb_miss_error = true; r_dma_cmd_to_tlb_req = false; #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " PTE1 Unmapped" << std::hex +std::cout << name() + << " PTE1 Unmapped" << std::hex << " / paddr = " << r_tlb_paddr.read() << " / PTE = " << pte_flags << std::endl; #endif - break; + break; } @@ -1085,5 +1154,6 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Hit on prefetch buffer: PTE1" << std::hex +std::cout << name() + << " Hit on prefetch buffer: PTE1" << std::hex << " / paddr = " << r_tlb_paddr.read() << std::hex << " / PTE1 = " << pte_flags << std::endl; @@ -1092,11 +1162,12 @@ } } - + // prefetch buffer miss - r_tlb_fsm = TLB_MISS; + r_tlb_fsm = TLB_MISS; #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Miss on prefetch buffer" +std::cout << name() + << " Miss on prefetch buffer" << std::hex << " / vaddr = " << r_dma_cmd_to_tlb_vaddr.read() << std::endl; #endif @@ -1107,7 +1178,7 @@ case TLB_MISS: // handling tlb miss { - uint32_t ptba = 0; - bool bypass; - vci_addr_t pte_paddr; + uint32_t ptba = 0; + bool bypass; + vci_addr_t pte_paddr; #ifdef INSTRUMENTATION @@ -1116,6 +1187,6 @@ // evaluate bypass in order to skip first level page table access bypass = r_iotlb.get_bypass(r_dma_cmd_to_tlb_vaddr.read(), &ptba); - - // Request MISS_WTI_FSM a transaction on INT Network + + // Request MISS_WTI_FSM a transaction on INT Network if ( not bypass ) // Read PTE1/PTD1 in XRAM { @@ -1123,10 +1194,11 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Read PTE1/PTD1 in memory" << std::endl; +std::cout << name() + << " Read PTE1/PTD1 in memory" << std::endl; #endif pte_paddr = (vci_addr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) | (vci_addr_t)((r_dma_cmd_to_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); r_tlb_paddr = pte_paddr; - + r_tlb_to_miss_wti_cmd_req = true; r_tlb_miss_type = PTE1_MISS; @@ -1138,12 +1210,13 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Read PTE2 in memory" << std::endl; +std::cout << name() + << " Read PTE2 in memory" << std::endl; #endif //&PTE2 = PTBA + IX2 * 8 pte_paddr = (vci_addr_t)ptba << PAGE_K_NBITS | (vci_addr_t)(r_dma_cmd_to_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); - + r_tlb_paddr = pte_paddr; - + r_tlb_to_miss_wti_cmd_req = true; r_tlb_miss_type = PTE2_MISS; @@ -1153,48 +1226,49 @@ break; } - ////////////////// - case TLB_PTE1_GET: // Try to read a PT1 entry in the miss buffer - { - + ////////////////// + case TLB_PTE1_GET: // Try to read a PT1 entry in the miss buffer + { + uint32_t entry; - + vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); - // Hit test. Just to verify. + // Hit test. Just to verify. // Hit must happen, since we've just finished its' miss transaction - bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); - assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); - + bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); + assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); + entry = r_tlb_buf_data[word_position]; - + // Bit valid checking - if ( not ( entry & PTE_V_MASK) ) // unmapped + if ( not ( entry & PTE_V_MASK) ) // unmapped { //must not occur! std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl << "The Page Table entry ins't valid (unmapped)" << std::endl; - + r_tlb_miss_error = true; r_dma_cmd_to_tlb_req = false; - r_tlb_fsm = TLB_IDLE; + r_tlb_fsm = TLB_IDLE; #if DEBUG_TLB_MISS if ( m_debug_activated ) { - std::cout << " First level entry Unmapped" + std::cout << name() + << " First level entry Unmapped" << std::hex << " / paddr = " << r_tlb_paddr.read() << std::hex << " / PTE = " << entry << std::endl; } #endif - break; + break; } - - if( entry & PTE_T_MASK ) // PTD : me must access PT2 + + if( entry & PTE_T_MASK ) // PTD : me must access PT2 { // register bypass r_iotlb.set_bypass( r_dma_cmd_to_tlb_vaddr.read(), - entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), - 0); //nline, unused + entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), + 0); //nline, unused // &PTE2 = PTBA + IX2 * 8 @@ -1213,10 +1287,11 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Success. Search PTE2" << std::hex +std::cout << name() + << " Success. Search PTE2" << std::hex << " / PADDR = " << r_tlb_paddr.read() << " / PTD = " << entry << std::endl; #endif } - else // PTE1 : we must update the IOTLB + else // PTE1 : we must update the IOTLB // Should not occur if working only with small pages { @@ -1226,5 +1301,6 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Success. Big page" +std::cout << name() + << " Success. Big page" << std::hex << " / paddr = " << r_tlb_paddr.read() << std::hex << " / PTE1 = " << entry << std::endl; @@ -1234,11 +1310,11 @@ } ///////////////////// - case TLB_PTE1_SELECT: // select a slot for PTE1 - { - size_t way; - size_t set; - + case TLB_PTE1_SELECT: // select a slot for PTE1 + { + size_t way; + size_t set; + r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), - true, // PTE1 + true, // PTE1 &way, &set ); @@ -1249,5 +1325,6 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Select a slot in TLB" +std::cout << name() + << " Select a slot in TLB" << " / way = " << std::dec << way << " / set = " << set << std::endl; @@ -1263,14 +1340,14 @@ { uint32_t pte = r_tlb_pte_flags.read(); - + r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_flags.read() & PPN1_MASK) << 21) | (r_dma_cmd_to_tlb_vaddr.read()& M_PAGE_OFFSET_MASK) ); - + // update TLB - r_iotlb.write( true, // 2M page + r_iotlb.write( true, // 2M page pte, - 0, // argument unused for a PTE1 - r_dma_cmd_to_tlb_vaddr.read(), - r_tlb_way.read(), + 0, // argument unused for a PTE1 + r_dma_cmd_to_tlb_vaddr.read(), + r_tlb_way.read(), r_tlb_set.read(), 0 ); //we set nline = 0 @@ -1283,5 +1360,6 @@ if ( m_debug_activated ) { -std::cout << " write PTE1 in TLB" +std::cout << name() + << " write PTE1 in TLB" << " / set = " << std::dec << r_tlb_set.read() << " / way = " << r_tlb_way.read() << std::endl; @@ -1290,50 +1368,52 @@ #endif // next state - r_tlb_fsm = TLB_RETURN; // exit sub-fsm + r_tlb_fsm = TLB_RETURN; // exit sub-fsm break; } ////////////////// - case TLB_PTE2_GET: // Try to read a PTE2 (64 bits) in the miss buffer - { - uint32_t pte_flags; - uint32_t pte_ppn; - + case TLB_PTE2_GET: // Try to read a PTE2 (64 bits) in the miss buffer + { + uint32_t pte_flags; + uint32_t pte_ppn; + vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); - - + + // Hit test. Just to verify. - bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); - assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); + bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); + assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); pte_flags= r_tlb_buf_data[word_position]; pte_ppn= r_tlb_buf_data[word_position+1]; //because PTE2 is 2 words long // Bit valid checking - if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped { //must not occur! std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl << "The Page Table entry ins't valid (unmapped)" << std::endl; - + r_tlb_miss_error = true; r_dma_cmd_to_tlb_req = false; - r_tlb_fsm = TLB_IDLE; + r_tlb_fsm = TLB_IDLE; #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " PTE2 Unmapped" << std::hex +std::cout << name() + << " PTE2 Unmapped" << std::hex << " / PADDR = " << r_tlb_paddr.read() << " / PTE = " << pte_flags << std::endl; #endif - break; + break; } - - r_tlb_pte_flags = pte_flags; + + r_tlb_pte_flags = pte_flags; r_tlb_pte_ppn = pte_ppn; r_tlb_fsm = TLB_PTE2_SELECT; - + #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Mapped" << std::hex - << " / PTE_FLAGS = " << pte_flags +std::cout << name() + << " Mapped" << std::hex + << " / PTE_FLAGS = " << pte_flags << " / PTE_PPN = " << pte_ppn << std::endl; #endif @@ -1347,5 +1427,5 @@ r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), - false, // PTE2 + false, // PTE2 &way, &set ); @@ -1356,5 +1436,6 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " Select a slot in IOTLB:" +std::cout << name() + << " Select a slot in IOTLB:" << " way = " << std::dec << way << " / set = " << set << std::endl; @@ -1366,19 +1447,19 @@ } /////////////////// - case TLB_PTE2_UPDT: // write a new PTE2 in tlb + case TLB_PTE2_UPDT: // write a new PTE2 in tlb // not necessary to treat the L/R bit { uint32_t pte_flags = r_tlb_pte_flags.read(); uint32_t pte_ppn = r_tlb_pte_ppn.read(); - + r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_ppn.read() & PPN2_MASK) << 12) | (r_dma_cmd_to_tlb_vaddr.read()& K_PAGE_OFFSET_MASK) ); - + // update TLB for a PTE2 - r_iotlb.write( false, // 4K page + r_iotlb.write( false, // 4K page pte_flags, pte_ppn, - r_dma_cmd_to_tlb_vaddr.read(), - r_tlb_way.read(), + r_dma_cmd_to_tlb_vaddr.read(), + r_tlb_way.read(), r_tlb_set.read(), 0 ); // nline = 0 @@ -1390,5 +1471,6 @@ if ( m_debug_activated ) { -std::cout << " write PTE2 in IOTLB" +std::cout << name() + << " write PTE2 in IOTLB" << " / set = " << std::dec << r_tlb_set.read() << " / way = " << r_tlb_way.read() << std::endl; @@ -1397,5 +1479,5 @@ #endif // next state - r_tlb_fsm = TLB_RETURN; + r_tlb_fsm = TLB_RETURN; break; } @@ -1404,5 +1486,5 @@ // PTE inval request are handled as unmaskable interrupts { - if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation + if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation { r_config_cmd_to_tlb_req = false; @@ -1414,8 +1496,8 @@ m_cost_iotlbmiss_transaction++; #endif - if ( not r_tlb_to_miss_wti_cmd_req.read() ) // Miss transaction completed - { - if ( r_miss_wti_rsp_error_miss.read() ) // bus error reported - { + if ( not r_tlb_to_miss_wti_cmd_req.read() ) // Miss transaction completed + { + if ( r_miss_wti_rsp_error_miss.read() ) // bus error reported + { r_miss_wti_rsp_error_miss = false; r_tlb_miss_error = true; @@ -1425,5 +1507,5 @@ else if(r_tlb_miss_type == PTE1_MISS) { - r_tlb_fsm = TLB_PTE1_GET; + r_tlb_fsm = TLB_PTE1_GET; } else @@ -1440,5 +1522,6 @@ #if DEBUG_TLB_MISS if ( m_debug_activated ) -std::cout << " IOTLB MISS completed" << std::endl; +std::cout << name() + << " IOTLB MISS completed" << std::endl; #endif r_dma_cmd_to_tlb_req = false; @@ -1457,6 +1540,6 @@ if(!r_tlb_buf_big_page) { - if( r_tlb_buf_vaddr.read() == - (r_config_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET) ) + if( r_tlb_buf_vaddr.read() == + (r_config_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET) ) // The virtual address corresponds to one entry on the buffer line { @@ -1466,6 +1549,6 @@ else // First level entries on buffer. Unused if only small pages { - if( r_tlb_buf_vaddr.read() == - (r_config_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET) ) + if( r_tlb_buf_vaddr.read() == + (r_config_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET) ) // The virtual address corresponds to one entry on the buffer line { @@ -1474,15 +1557,14 @@ } } - + // Invalidation on IOTLB - bool ok; - ok = r_iotlb.inval(r_config_cmd_to_tlb_vaddr.read()); - - if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; + r_iotlb.inval(r_config_cmd_to_tlb_vaddr.read()); + + if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; else r_tlb_fsm = TLB_IDLE; - break; + break; } } //end switch r_tlb_fsm - + //////////////////////////////////////////////////////////////////////////////// // The CONFIG_CMD_FSM handles the VCI commands from the INT network. @@ -1501,18 +1583,20 @@ /////////////////////////////////////////////////////////////////////////////// - switch( r_config_cmd_fsm.read() ) + switch( r_config_cmd_fsm.read() ) { ///////////////////// case CONFIG_CMD_IDLE: // A VCI INT command is always consumed in this state { - if ( p_vci_tgt_int.cmdval.read() ) + if ( p_vci_tgt_int.cmdval.read() ) { #if DEBUG_CONFIG_CMD if( m_debug_activated ) -std::cout << " ### Config Command received" << std::endl +std::cout << name() + << " ### Config Command received" << std::endl << " address = " << std::hex << p_vci_tgt_int.address.read() << " / srcid = " << p_vci_tgt_int.srcid.read() << " / trdid = " << p_vci_tgt_int.trdid.read() + << " / pktid = " << p_vci_tgt_int.pktid.read() << " / wdata = " << std::hex << p_vci_tgt_int.wdata.read() << " / be = " << p_vci_tgt_int.be.read() @@ -1522,7 +1606,9 @@ vci_addr_t paddr = p_vci_tgt_int.address.read(); bool read = (p_vci_tgt_int.cmd.read() == vci_param_int::CMD_READ); - uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); + uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); bool eop = p_vci_tgt_int.eop.read(); bool high = (paddr & 0x4); + ext_data_t wdata = (ext_data_t)p_vci_tgt_int.wdata.read(); + ext_be_t be = (ext_be_t)p_vci_tgt_int.be.read(); // chek segments @@ -1530,8 +1616,8 @@ bool found = false; bool special = false; - for ( seg = m_int_seglist.begin() ; + for ( seg = m_int_seglist.begin() ; seg != m_int_seglist.end() and not found ; seg++ ) { - if ( seg->contains(paddr) ) + if ( seg->contains(paddr) ) { found = true; @@ -1539,10 +1625,11 @@ } } - + if ( found and special ) // IO_BRIDGE itself { bool rerror = false; - - assert( (p_vci_tgt_int.be.read() == 0xF) and + int_data_t rdata; + + assert( (be == 0xF) and "ERROR in vci_io_bridge : BE must be 0xF for a config access"); @@ -1552,66 +1639,50 @@ if ( not read && (cell == IOB_IOMMU_PTPR) ) // WRITE PTPR { - r_iommu_ptpr = (uint32_t)p_vci_tgt_int.wdata.read(); - } - else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR - { - r_config_cmd_to_config_rsp_rdata = r_iommu_ptpr.read(); + r_iommu_ptpr = (uint32_t)wdata; + } + else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR + { + rdata = r_iommu_ptpr.read(); } else if( not read && (cell == IOB_WTI_ENABLE)) // WRITE WTI_ENABLE { - r_iommu_wti_enable = p_vci_tgt_int.wdata.read(); + r_iommu_wti_enable = wdata; } else if( read && (cell == IOB_WTI_ENABLE)) // READ WTI ENABLE { - r_config_cmd_to_config_rsp_rdata = r_iommu_wti_enable.read(); + rdata = r_iommu_wti_enable.read(); } else if( read && (cell == IOB_IOMMU_BVAR)) // READ BVAR { - r_config_cmd_to_config_rsp_rdata = r_iommu_bvar.read(); + rdata = r_iommu_bvar.read(); } else if( read && (cell == IOB_IOMMU_ETR)) // READ ETR { - r_config_cmd_to_config_rsp_rdata = r_iommu_etr.read(); + rdata = r_iommu_etr.read(); } else if( read && (cell == IOB_IOMMU_BAD_ID)) // READ BAD_ID { - r_config_cmd_to_config_rsp_rdata = r_iommu_bad_id.read(); + rdata = r_iommu_bad_id.read(); } else if( not read && (cell == IOB_INVAL_PTE)) // WRITE INVAL_PTE { r_config_cmd_to_tlb_req = true; - r_config_cmd_to_tlb_vaddr = (uint32_t)p_vci_tgt_int.wdata.read(); + r_config_cmd_to_tlb_vaddr = (uint32_t)wdata; } else if( not read && (cell == IOB_WTI_ADDR_LO)) // WRITE WTI_PADDR_LO { - r_iommu_wti_addr_lo = (vci_addr_t)p_vci_tgt_int.wdata.read(); + r_iommu_wti_addr_lo = (vci_addr_t)wdata; } else if( read && (cell == IOB_WTI_ADDR_LO)) // READ WTI_PADDR_LO { - r_config_cmd_to_config_rsp_rdata = r_iommu_wti_addr_lo.read(); + rdata = r_iommu_wti_addr_lo.read(); } else if( not read && (cell == IOB_WTI_ADDR_HI)) // WRITE WTI_PADDR_HI { - r_iommu_wti_addr_hi = (vci_addr_t)p_vci_tgt_int.wdata.read(); + r_iommu_wti_addr_hi = (vci_addr_t)wdata; } else if( read && (cell == IOB_WTI_ADDR_HI)) // READ WTI_PADDR_HI { - r_config_cmd_to_config_rsp_rdata = r_iommu_wti_addr_hi.read(); - } - else if( not read && (cell == IOB_XICU_BASE)) // WRITE XICU_BASE - { - r_xicu_base = (vci_addr_t)p_vci_tgt_int.wdata.read(); - } - else if( read && (cell == IOB_XICU_BASE)) // READ XICU_BASE - { - r_config_cmd_to_config_rsp_rdata = r_xicu_base.read(); - } - else if( not read && (cell == IOB_XICU_SIZE)) // WRITE XICU_SIZE - { - r_xicu_size = (vci_addr_t)p_vci_tgt_int.wdata.read(); - } - else if( read && (cell == IOB_XICU_SIZE)) // READ XICU_SIZE - { - r_config_cmd_to_config_rsp_rdata = r_xicu_size.read(); + rdata = r_iommu_wti_addr_hi.read(); } else // Error: Wrong address, or invalid operation. @@ -1620,12 +1691,14 @@ } r_config_cmd_to_config_rsp_rerror = rerror; - r_config_cmd_fsm = CONFIG_CMD_RSP; + r_config_cmd_to_config_rsp_rdata = rdata; + r_config_cmd_to_config_rsp_rsrcid = p_vci_tgt_int.srcid.read(); + r_config_cmd_to_config_rsp_rtrdid = p_vci_tgt_int.trdid.read(); + r_config_cmd_to_config_rsp_rpktid = p_vci_tgt_int.pktid.read(); + r_config_cmd_fsm = CONFIG_CMD_RSP; } else if ( found ) // remote peripheral { + // buffer VCI command r_config_cmd_address = p_vci_tgt_int.address.read(); - r_config_cmd_srcid = p_vci_tgt_int.srcid.read(); - r_config_cmd_trdid = p_vci_tgt_int.trdid.read(); - r_config_cmd_pktid = p_vci_tgt_int.pktid.read(); r_config_cmd_pktid = p_vci_tgt_int.pktid.read(); r_config_cmd_plen = p_vci_tgt_int.plen.read(); @@ -1636,45 +1709,54 @@ r_config_cmd_contig = p_vci_tgt_int.contig.read(); r_config_cmd_cfixed = p_vci_tgt_int.cfixed.read(); - - if( eop ) // single flit command - { - if ( high ) // HI word - { - r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read())<<32; - r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read())<<4; - r_config_cmd_eop = true; - r_config_cmd_fsm = CONFIG_CMD_PUT; - } - else // LO word - { - r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read()); - r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read()); - r_config_cmd_eop = true; - r_config_cmd_fsm = CONFIG_CMD_PUT; - } - } - else // multi-flits write - { - if ( high ) // MSB word - { - r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read())<<32; - r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read())<<4; - r_config_cmd_eop = false; - r_config_cmd_fsm = CONFIG_CMD_PUT; - } - else // LSB word - { - r_config_cmd_wdata = ((ext_data_t)p_vci_tgt_int.wdata.read()); - r_config_cmd_be = ((ext_be_t)p_vci_tgt_int.be.read()); - r_config_cmd_eop = false; - r_config_cmd_fsm = CONFIG_CMD_NEXT; - } - } - } - else // out of segment address - { + r_config_cmd_eop = eop; + r_config_cmd_wdata = (wdata << (high ? 32 : 0)); + r_config_cmd_be = (be << (high ? 4 : 0)); + + size_t tab_index; + if (m_iox_transaction_tab.full(tab_index)) + { +#ifdef INSTRUMENTATION +m_cpt_trt_config_full++; +#endif + + // wait for an empty slot in the IOX transaction table. + // buffer SRCID and TRDID of VCI command to store them + // later in IOX transaction table. + r_config_cmd_srcid = p_vci_tgt_int.srcid.read(); + r_config_cmd_trdid = p_vci_tgt_int.trdid.read(); + r_config_cmd_fsm = CONFIG_CMD_WAIT; + break; + } + + // TRDID in IOX interconnect is the translation table index + r_config_cmd_trdid = tab_index; + + // create new entry in IOX transaction table + m_iox_transaction_tab.set( tab_index, + p_vci_tgt_int.srcid.read(), + p_vci_tgt_int.trdid.read()); + + if (eop) r_config_cmd_fsm = CONFIG_CMD_PUT; + else r_config_cmd_fsm = CONFIG_CMD_HI; + +#if DEBUG_CONFIG_CMD +if( m_debug_activated ) +{ +std::cout << name() + << " ### new entry in IOX transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + + } + else if ( eop ) // out of segment address + { + r_config_cmd_to_config_rsp_rerror = true; r_config_cmd_to_config_rsp_rdata = 0; - r_config_cmd_to_config_rsp_rerror = true; - if( eop ) r_config_cmd_fsm = CONFIG_CMD_RSP; + r_config_cmd_to_config_rsp_rsrcid = p_vci_tgt_int.srcid.read(); + r_config_cmd_to_config_rsp_rtrdid = p_vci_tgt_int.trdid.read(); + r_config_cmd_to_config_rsp_rpktid = p_vci_tgt_int.pktid.read(); + r_config_cmd_fsm = CONFIG_CMD_RSP; } } // end if cmdval @@ -1682,10 +1764,44 @@ } ///////////////////// - case CONFIG_CMD_NEXT: // Consume the second flit for a multi-flits write - { - if ( p_vci_tgt_int.cmdval.read() ) + case CONFIG_CMD_WAIT: + { + // wait for an empty slot in the translation table. + size_t tab_index; + if (m_iox_transaction_tab.full(tab_index)) + { +#ifdef INSTRUMENTATION +m_cpt_trt_config_full_cost++; +#endif + break; + } + + // create new entry in IOX transaction table + m_iox_transaction_tab.set( tab_index, + r_config_cmd_srcid.read(), + r_config_cmd_trdid.read()); + + // TRDID in IOX interconnect is the translation table index + r_config_cmd_trdid = tab_index; + if (r_config_cmd_eop.read()) r_config_cmd_fsm = CONFIG_CMD_PUT; + else r_config_cmd_fsm = CONFIG_CMD_HI; + +#if DEBUG_CONFIG_CMD +if( m_debug_activated ) +{ +std::cout << name() + << " ### new entry in IOX transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + break; + } + ///////////////////// + case CONFIG_CMD_HI: // consume the second flit for a multi-flits write + { + if ( p_vci_tgt_int.cmdval.read() ) { vci_addr_t paddr = p_vci_tgt_int.address.read(); - bool high = (paddr & 0x4 == 0x4); + bool high = ((paddr & 0x4) == 0x4); bool eop = p_vci_tgt_int.eop.read(); @@ -1702,4 +1818,26 @@ break; } + ///////////////////// + case CONFIG_CMD_LO: // consume the first flit for a multi-flits write + { + if ( p_vci_tgt_int.cmdval.read() ) + { + vci_addr_t paddr = p_vci_tgt_int.address.read(); + bool high = ((paddr & 0x4) == 0x4); + bool eop = p_vci_tgt_int.eop.read(); + + assert( (paddr == r_config_cmd_address.read() + 4) and !high and + "ERROR in vci_io_bridge : addresses must be contiguous in write burst" ); + + r_config_cmd_address = p_vci_tgt_int.address.read(); + r_config_cmd_wdata = (ext_data_t)p_vci_tgt_int.wdata.read(); + r_config_cmd_be = (ext_be_t)p_vci_tgt_int.be.read(); + r_config_cmd_eop = eop; + + if (eop) r_config_cmd_fsm = CONFIG_CMD_PUT; + else r_config_cmd_fsm = CONFIG_CMD_HI; + } + break; + } //////////////////// case CONFIG_CMD_PUT: // post a command to CONFIG_CMD fifo (to IOX network) @@ -1711,20 +1849,23 @@ #if DEBUG_CONFIG_CMD -if( m_debug_activated ) -std::cout << " Transmit VCI command to IOX network" +if( m_debug_activated ) +std::cout << name() + << " Transmit VCI command to IOX network" << " : address = " << std::hex << r_config_cmd_address.read() - << " / srcid = " << r_config_cmd_srcid.read() + << " / srcid = " << m_iox_srcid + << " / trdid = " << r_config_cmd_trdid.read() << " / eop = " << r_config_cmd_eop.read() << std::endl; #endif - r_config_cmd_fsm = CONFIG_CMD_IDLE; + if (r_config_cmd_eop.read()) r_config_cmd_fsm = CONFIG_CMD_IDLE; + else r_config_cmd_fsm = CONFIG_CMD_LO; } break; } //////////////////// - case CONFIG_CMD_RSP: // Post a request to CONFIG_RSP FSM, + case CONFIG_CMD_RSP: // Post a request to CONFIG_RSP FSM, // if no previous pending request. // r_config_cmd_to_config_rsp_rerror - // has been set in IDLE state. + // has been set in IDLE state. { if ( not r_config_cmd_to_config_rsp_req.read() ) @@ -1733,6 +1874,7 @@ #if DEBUG_CONFIG_CMD -if( m_debug_activated ) -std::cout << " Request a response to CONFIG_RSP FSM" +if( m_debug_activated ) +std::cout << name() + << " Request a response to CONFIG_RSP FSM" << " / error = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; #endif @@ -1748,7 +1890,7 @@ // - CONFIG_CMD : response to a local config command. // - CONFIG_RSP : responses from peripherals on IOX network - // Regarding the responses from IOX network it handles both single flit - // config responses, and multi-flits read responses (ROM), where data must - // be serialised (64 bits -> 32 bits). + // Regarding the responses from IOX network it handles both single flit + // config responses, and multi-flits read responses (ROM), where data must + // be serialised (64 bits -> 32 bits). // Note: We use the VCI RPKTID field to distinguish between read cached // (multi-flits response) and others (single flit response). @@ -1759,50 +1901,84 @@ if ( m_config_rsp_rerror_fifo.wok() ) { - switch( r_config_rsp_fsm.read() ) + switch( r_config_rsp_fsm.read() ) { ///////////////////////// case CONFIG_RSP_IDLE_IOX: // IOX requests have highest priority // no flit on IOX network is consumed - { + { if ( p_vci_ini_iox.rspval.read() ) // IOX request - { - if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits + { + // recover srcid and trdid from the IOX transaction table + size_t tab_index = (size_t)p_vci_ini_iox.rtrdid.read(); + r_config_rsp_rsrcid = m_iox_transaction_tab.readSrcid(tab_index); + r_config_rsp_rtrdid = m_iox_transaction_tab.readTrdid(tab_index); + + // erase entry + m_iox_transaction_tab.erase(tab_index); + + if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits { - r_config_rsp_fsm = CONFIG_RSP_PUT_LOW; + r_config_rsp_fsm = CONFIG_RSP_PUT_LO; } - else // single flit + else // single flit { r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; } - } - else if ( r_config_cmd_to_config_rsp_req.read() ) // LOC request +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +{ +std::cout << name() + << " ### remove entry in transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + } + else if ( r_config_cmd_to_config_rsp_req.read() ) // LOCAL request { r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; } - break; + break; } ///////////////////////// - case CONFIG_RSP_IDLE_LOC: // LOC requests have highest priority + case CONFIG_RSP_IDLE_LOC: // LOCAL requests have highest priority // no flit on IOX network is consumed - { - if ( r_config_cmd_to_config_rsp_req.read() ) // LOC request + { + if ( r_config_cmd_to_config_rsp_req.read() ) // LOCAL request { r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; } else if ( p_vci_ini_iox.rspval.read() ) // IOX request - { - if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits + { + // recover srcid and trdid from the IOX transaction table + size_t tab_index = (size_t)p_vci_ini_iox.rtrdid.read(); + r_config_rsp_rsrcid = m_iox_transaction_tab.readSrcid(tab_index); + r_config_rsp_rtrdid = m_iox_transaction_tab.readTrdid(tab_index); + + // erase entry + m_iox_transaction_tab.erase(tab_index); + + if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits { - r_config_rsp_fsm = CONFIG_RSP_PUT_LOW; + r_config_rsp_fsm = CONFIG_RSP_PUT_LO; } - else // single flit + else // single flit { r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; } - } - break; +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +{ +std::cout << name() + << " ### remove entry in transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + } + break; } //////////////////////// - case CONFIG_RSP_PUT_LOW: // put 32 low bits into CONFIG_RSP fifo + case CONFIG_RSP_PUT_LO: // put 32 low bits into CONFIG_RSP fifo // no flit on IOX network is consumed { @@ -1810,6 +1986,6 @@ config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); - config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read(); - config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read(); + config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); config_rsp_fifo_reop = false; @@ -1818,8 +1994,9 @@ #if DEBUG_CONFIG_RSP -if( m_debug_activated ) -std::cout << " Push multi-flit response into CONFIG_RSP FIFO" - << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() - << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() +if( m_debug_activated ) +std::cout << name() + << " Push multi-flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_rsp_rtrdid.read() << " / rpktid = " << p_vci_ini_iox.rpktid.read() << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() @@ -1827,26 +2004,27 @@ << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; #endif - break; + break; } /////////////////////// case CONFIG_RSP_PUT_HI: // put 32 high bits into CONFIG_RSP fifo - // flit on IOX network is consumed + // flit on IOX network is consumed { config_rsp_fifo_put = true; config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); config_rsp_fifo_rdata = (uint32_t)(p_vci_ini_iox.rdata.read() >> 32); - config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read(); - config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read(); + config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); config_rsp_fifo_reop = p_vci_ini_iox.reop.read(); if( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE_LOC; - else r_config_rsp_fsm = CONFIG_RSP_PUT_LOW; + else r_config_rsp_fsm = CONFIG_RSP_PUT_LO; #if DEBUG_CONFIG_RSP -if( m_debug_activated ) -std::cout << " Push multi-flit response into CONFIG_RSP FIFO" - << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() - << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() +if( m_debug_activated ) +std::cout << name() + << " Push multi-flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_rsp_rtrdid.read() << " / rpktid = " << p_vci_ini_iox.rpktid.read() << " / rdata = " << (uint32_t)(p_vci_ini_iox.rdata.read() >> 32) @@ -1854,11 +2032,11 @@ << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; #endif - break; + break; } //////////////////////// case CONFIG_RSP_PUT_UNC: // put single flit into CONFIG_RSP fifo - // flit on IOX network is consumed - { - assert( p_vci_ini_iox.reop.read() and + // flit on IOX network is consumed + { + assert( p_vci_ini_iox.reop.read() and "ERROR in vci_io_bridge : a remote config response should be one flit"); @@ -1866,6 +2044,6 @@ config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); - config_rsp_fifo_rsrcid = p_vci_ini_iox.rsrcid.read(); - config_rsp_fifo_rtrdid = p_vci_ini_iox.rtrdid.read(); + config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); config_rsp_fifo_reop = true; @@ -1875,8 +2053,9 @@ #if DEBUG_CONFIG_RSP -if( m_debug_activated ) -std::cout << " Push single flit response into CONFIG_RSP FIFO" - << " / rsrcid = " << std::hex << p_vci_ini_iox.rsrcid.read() - << " / rtrdid = " << p_vci_ini_iox.rtrdid.read() +if( m_debug_activated ) +std::cout << name() + << " Push single flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_rsp_rtrdid.read() << " / rpktid = " << p_vci_ini_iox.rpktid.read() << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() @@ -1884,19 +2063,19 @@ << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; #endif - break; + break; } //////////////////////// case CONFIG_RSP_PUT_LOC: // put single flit into CONFIG_RSP fifo - // no flit on IOX network is consumed + // no flit on IOX network is consumed { config_rsp_fifo_put = true; config_rsp_fifo_rerror = r_config_cmd_to_config_rsp_rerror.read(); config_rsp_fifo_rdata = r_config_cmd_to_config_rsp_rdata.read(); - config_rsp_fifo_rsrcid = r_config_cmd_srcid.read(); - config_rsp_fifo_rtrdid = r_config_cmd_trdid.read(); - config_rsp_fifo_rpktid = r_config_cmd_pktid.read(); + config_rsp_fifo_rsrcid = r_config_cmd_to_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_cmd_to_config_rsp_rtrdid.read(); + config_rsp_fifo_rpktid = r_config_cmd_to_config_rsp_rpktid.read(); config_rsp_fifo_reop = true; - // acknowledge request + // acknowledge request r_config_cmd_to_config_rsp_req = false; @@ -1905,14 +2084,15 @@ #if DEBUG_CONFIG_RSP -if( m_debug_activated ) -std::cout << " Push single flit response into CONFIG_RSP FIFO" - << " / rsrcid = " << std::hex << r_config_cmd_srcid.read() - << " / rtrdid = " << r_config_cmd_trdid.read() - << " / rpktid = " << r_config_cmd_pktid.read() +if( m_debug_activated ) +std::cout << name() + << " Push single flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_cmd_to_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_cmd_to_config_rsp_rtrdid.read() + << " / rpktid = " << r_config_cmd_to_config_rsp_rpktid.read() << " / rdata = " << r_config_cmd_to_config_rsp_rdata.read() << " / reop = " << true << " / rerror = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; #endif - break; + break; } } // end switch CONFIG_RSP FSM @@ -1927,17 +2107,17 @@ // MISS_WTI_RSP FSM only when the response is received. // 2. WTI requests from DMA_CMD FSM : - // These requestsare non blocking events, and the r_dma_cmd_to_miss_wti_cmd_req - // flip-flop is reset as soon as the WTI command has been sent. + // These requestsare non blocking events, and the r_dma_cmd_to_miss_wti_cmd_req + // flip-flop is reset as soon as the WTI command has been sent. // There is two types of WTI requests: // - external WTI from peripherals on IOX network. // - internal WTI caused by illegal DMA requests. //////////////////////////////////////////////////////////////////////////////////// - - if ( r_tlb_to_miss_wti_cmd_req.read() and + + if ( r_tlb_to_miss_wti_cmd_req.read() and m_miss_wti_cmd_addr_fifo.wok() ) // put MISS READ { miss_wti_cmd_fifo_put = true; - miss_wti_cmd_fifo_address = r_tlb_paddr.read(); - miss_wti_cmd_fifo_wdata = 0; + miss_wti_cmd_fifo_address = r_tlb_paddr.read(); + miss_wti_cmd_fifo_wdata = 0; miss_wti_cmd_fifo_cmd = vci_param_int::CMD_READ; miss_wti_cmd_fifo_pktid = PKTID_MISS; @@ -1947,10 +2127,11 @@ #if DEBUG_MISS_WTI_CMD if( m_debug_activated ) -std::cout << " push MISS TLB command into MISS_WTI FIFO" +std::cout << name() + << " push MISS TLB command into MISS_WTI FIFO" << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; #endif } - else if ( r_dma_cmd_to_miss_wti_cmd_req.read() and + else if ( r_dma_cmd_to_miss_wti_cmd_req.read() and m_miss_wti_cmd_addr_fifo.wok() ) // put WTI READ / WRITE { @@ -1967,25 +2148,26 @@ #if DEBUG_MISS_WTI_CMD if( m_debug_activated ) -std::cout << " push WTI command into MISS_WTI FIFO" +std::cout << name() + << " push WTI command into MISS_WTI FIFO" << " / CMD = " << miss_wti_cmd_fifo_cmd << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; #endif - } + } /////////////////////////////////////////////////////////////////////////////////// // The MISS_WTI_RSP FSM handles VCI responses from the INT network: // - for a TLB MISS (multi-flits read transaction), the cache line - // is written in r_tlb_buf_data[], and r_tlb_to_miss_wti_cmd_req flip-flop is reset. + // is written in r_tlb_buf_data[], and r_tlb_to_miss_wti_cmd_req flip-flop is reset. // - for a WTI_IOX (single flit write transaction), the response must be // forwarded to the source peripheral on the INT network // - for a WTI_MMU (single flit write transaction), there is nothing to do. // - // TODO VCI addressing errors for TLB MISS or for WTI_MMU (i.e. kernel errors...) + // TODO VCI addressing errors for TLB MISS or for WTI_MMU (i.e. kernel errors...) // are registered in the r_miss_wti_rsp_error_miss & r_miss_wti_rsp_error_wti // flip-flops, and simulation stops... They could be signaled to OS by a WTI. //////////////////////////////////////////////////////////////////////////////////// - - switch ( r_miss_wti_rsp_fsm.read() ) + + switch ( r_miss_wti_rsp_fsm.read() ) { /////////////////////// @@ -1993,11 +2175,11 @@ // no VCI flit is consumed { - if ( p_vci_ini_int.rspval.read() ) - { - if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_IOX ) + if ( p_vci_ini_int.rspval.read() ) + { + if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_IOX ) { r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_IOX; } - else if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_MMU ) + else if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_MMU ) { r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_MMU; @@ -2022,7 +2204,7 @@ // if no pending previous request. { - assert( p_vci_ini_int.reop.read() and - "VCI_IO_BRIDGE ERROR: WTI_IOX response should have one single flit" ); - + assert( p_vci_ini_int.reop.read() and + "VCI_IO_BRIDGE ERROR: WTI_IOX response should have one single flit" ); + if ( not r_miss_wti_rsp_to_dma_rsp_req.read() ) // no previous pending request { @@ -2037,37 +2219,39 @@ #if DEBUG_MISS_WTI_RSP if( m_debug_activated ) -std::cout << " Transfer response to a WTI_IOX" << std::endl; +std::cout << name() + << " Transfer response to a WTI_IOX" << std::endl; #endif } break; } - ////////////////////////// + ////////////////////////// case MISS_WTI_RSP_WTI_MMU: // Handling response to an iommu WTI // consume VCI flit and test VCI error. { - assert( p_vci_ini_int.reop.read() and - "VCI_IO_BRIDGE ERROR: WTI_MMU response should have one single flit" ); - + assert( p_vci_ini_int.reop.read() and + "VCI_IO_BRIDGE ERROR: WTI_MMU response should have one single flit" ); + if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported { // set the specific error flip-flop r_miss_wti_rsp_error_wti = true; - assert( false and + assert( false and "VCI_IO_BRIDGE ERROR: VCI error response for a WTI_MMU transaction"); } #if DEBUG_MISS_WTI_RSP -if( m_debug_activated ) -std::cout << " Receive response to a WTI_MMU" << std::endl; +if( m_debug_activated ) +std::cout << name() + << " Receive response to a WTI_MMU" << std::endl; #endif break; } /////////////////////// - case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS + case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS // write cache line in r_tlb_buf buffer // and analyse possible VCI error // VCI flit is consumed. { - if ( p_vci_ini_int.rspval.read() ) + if ( p_vci_ini_int.rspval.read() ) { if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported @@ -2075,5 +2259,5 @@ // set the specific error flip-flop r_miss_wti_rsp_error_miss = true; - assert( false and + assert( false and "VCI_IO_BRIDGE ERROR: VCI error response for a TLB MISS transaction"); @@ -2082,24 +2266,25 @@ { -#if DEBUG_MISS_WTI_CMD -if( m_debug_activated ) -std::cout << " Receive response to a TLB MISS" +#if DEBUG_MISS_WTI_CMD +if( m_debug_activated ) +std::cout << name() + << " Receive response to a TLB MISS" << " / Count = " << r_miss_wti_rsp_count.read() - << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; + << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; #endif r_tlb_buf_data[r_miss_wti_rsp_count.read()] = p_vci_ini_int.rdata.read(); } - + if ( p_vci_ini_int.reop.read() ) // last flit - { + { bool eop = p_vci_ini_int.eop.read(); - assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and + assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and "VCI_IO_BRIDGE ERROR: invalid length for a TLB MISS response"); r_miss_wti_rsp_count = 0; r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; - r_tlb_to_miss_wti_cmd_req = false; - } - else // not the last flit + r_tlb_to_miss_wti_cmd_req = false; + } + else // not the last flit { r_miss_wti_rsp_count = r_miss_wti_rsp_count.read() + 1; @@ -2142,5 +2327,5 @@ m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get, dma_cmd_fifo_put, - p_vci_tgt_iox.srcid.read() ); + dma_cmd_fifo_srcid ); m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get, dma_cmd_fifo_put, @@ -2151,8 +2336,8 @@ m_dma_cmd_data_fifo.update( dma_cmd_fifo_get, dma_cmd_fifo_put, - p_vci_tgt_iox.wdata.read() ); + p_vci_tgt_iox.wdata.read() ); m_dma_cmd_be_fifo.update( dma_cmd_fifo_get, dma_cmd_fifo_put, - p_vci_tgt_iox.be.read() ); + p_vci_tgt_iox.be.read() ); m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get, dma_cmd_fifo_put, @@ -2169,14 +2354,14 @@ m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, dma_rsp_fifo_put, - dma_rsp_fifo_rsrcid ); + dma_rsp_fifo_rsrcid ); m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, dma_rsp_fifo_put, - dma_rsp_fifo_rtrdid ); + dma_rsp_fifo_rtrdid ); m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, dma_rsp_fifo_put, - dma_rsp_fifo_rpktid ); + dma_rsp_fifo_rpktid ); m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, dma_rsp_fifo_put, - dma_rsp_fifo_reop ); + dma_rsp_fifo_reop ); m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, dma_rsp_fifo_put, @@ -2190,29 +2375,26 @@ m_config_cmd_addr_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_address.read() ); + r_config_cmd_address.read() ); m_config_cmd_cmd_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_cmd.read() ); + r_config_cmd_cmd.read() ); m_config_cmd_contig_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_contig.read() ); + r_config_cmd_contig.read() ); m_config_cmd_cons_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_cons.read() ); + r_config_cmd_cons.read() ); m_config_cmd_plen_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_plen.read() ); + r_config_cmd_plen.read() ); m_config_cmd_wrap_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_wrap.read() ); + r_config_cmd_wrap.read() ); m_config_cmd_cfixed_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_cfixed.read() ); + r_config_cmd_cfixed.read() ); m_config_cmd_clen_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, - r_config_cmd_clen.read() ); - m_config_cmd_srcid_fifo.update( config_cmd_fifo_get, - config_cmd_fifo_put, - r_config_cmd_srcid.read() ); + r_config_cmd_clen.read() ); m_config_cmd_trdid_fifo.update( config_cmd_fifo_get, config_cmd_fifo_put, @@ -2230,5 +2412,5 @@ config_cmd_fifo_put, r_config_cmd_eop.read() ); - + ////////////////////////////////////////////////////////////////////////// // CONFIG_RSP fifo update @@ -2238,5 +2420,5 @@ m_config_rsp_data_fifo.update( config_rsp_fifo_get, config_rsp_fifo_put, - config_rsp_fifo_rdata ); + config_rsp_fifo_rdata ); m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, config_rsp_fifo_put, @@ -2254,5 +2436,5 @@ config_rsp_fifo_put, config_rsp_fifo_rerror ); - + //////////////////////////////////////////////////////////////// // MISS_WTI_CMD fifo update @@ -2262,8 +2444,8 @@ m_miss_wti_cmd_addr_fifo.update( miss_wti_cmd_fifo_get, miss_wti_cmd_fifo_put, - miss_wti_cmd_fifo_address ); + miss_wti_cmd_fifo_address ); m_miss_wti_cmd_cmd_fifo.update( miss_wti_cmd_fifo_get, miss_wti_cmd_fifo_put, - miss_wti_cmd_fifo_cmd ); + miss_wti_cmd_fifo_cmd ); m_miss_wti_cmd_contig_fifo.update( config_cmd_fifo_get, miss_wti_cmd_fifo_put, @@ -2302,5 +2484,5 @@ miss_wti_cmd_fifo_put, true ); - + } // end transition() @@ -2313,10 +2495,10 @@ // VCI initiator command on RAM network // directly the content of the dma_cmd FIFO - p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); + p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); p_vci_ini_ram.address = m_dma_cmd_addr_fifo.read(); p_vci_ini_ram.be = m_dma_cmd_be_fifo.read(); p_vci_ini_ram.cmd = m_dma_cmd_cmd_fifo.read(); p_vci_ini_ram.contig = m_dma_cmd_contig_fifo.read(); - p_vci_ini_ram.wdata = m_dma_cmd_data_fifo.read(); + p_vci_ini_ram.wdata = m_dma_cmd_data_fifo.read(); p_vci_ini_ram.eop = m_dma_cmd_eop_fifo.read(); p_vci_ini_ram.cons = m_dma_cmd_cons_fifo.read(); @@ -2328,9 +2510,9 @@ p_vci_ini_ram.pktid = m_dma_cmd_pktid_fifo.read(); p_vci_ini_ram.srcid = m_dma_cmd_srcid_fifo.read(); - + // VCI initiator response on the RAM Network // depends on the DMA_RSP FSM state - p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and - (r_dma_rsp_fsm.read() == DMA_RSP_PUT_DMA); + p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and + (r_dma_rsp_fsm.read() == DMA_RSP_PUT_DMA); ///////////////// p_vci_tgt_iox ///////////////////////////// @@ -2342,5 +2524,5 @@ p_vci_tgt_iox.rtrdid = m_dma_rsp_rtrdid_fifo.read(); p_vci_tgt_iox.rpktid = m_dma_rsp_rpktid_fifo.read(); - p_vci_tgt_iox.rdata = m_dma_rsp_data_fifo.read(); + p_vci_tgt_iox.rdata = m_dma_rsp_data_fifo.read(); p_vci_tgt_iox.rerror = m_dma_rsp_rerror_fifo.read(); p_vci_tgt_iox.reop = m_dma_rsp_reop_fifo.read(); @@ -2348,26 +2530,26 @@ // VCI target command ack on IOX network // depends on the DMA_CMD FSM state - switch ( r_dma_cmd_fsm.read() ) - { - case DMA_CMD_IDLE: - p_vci_tgt_iox.cmdack = false; + switch ( r_dma_cmd_fsm.read() ) + { + case DMA_CMD_IDLE: + p_vci_tgt_iox.cmdack = false; break; case DMA_CMD_DMA_REQ: - p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); + p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); break; case DMA_CMD_WTI_IOX_REQ: - p_vci_tgt_iox.cmdack = not r_dma_cmd_to_miss_wti_cmd_req.read(); + p_vci_tgt_iox.cmdack = not r_dma_cmd_to_miss_wti_cmd_req.read(); break; case DMA_CMD_ERR_WTI_REQ: - p_vci_tgt_iox.cmdack = false; + p_vci_tgt_iox.cmdack = false; break; - case DMA_CMD_ERR_WAIT_EOP: - p_vci_tgt_iox.cmdack = true; + case DMA_CMD_ERR_WAIT_EOP: + p_vci_tgt_iox.cmdack = true; break; - case DMA_CMD_ERR_RSP_REQ: - p_vci_tgt_iox.cmdack = false; + case DMA_CMD_ERR_RSP_REQ: + p_vci_tgt_iox.cmdack = false; break; - case DMA_CMD_TLB_MISS_WAIT: - p_vci_tgt_iox.cmdack = false; + case DMA_CMD_TLB_MISS_WAIT: + p_vci_tgt_iox.cmdack = false; break; } @@ -2382,5 +2564,5 @@ p_vci_ini_iox.cmd = m_config_cmd_cmd_fifo.read(); p_vci_ini_iox.contig = m_config_cmd_contig_fifo.read(); - p_vci_ini_iox.wdata = m_config_cmd_data_fifo.read(); + p_vci_ini_iox.wdata = m_config_cmd_data_fifo.read(); p_vci_ini_iox.eop = m_config_cmd_eop_fifo.read(); p_vci_ini_iox.cons = m_config_cmd_cons_fifo.read(); @@ -2391,9 +2573,9 @@ p_vci_ini_iox.trdid = m_config_cmd_trdid_fifo.read(); p_vci_ini_iox.pktid = m_config_cmd_pktid_fifo.read(); - p_vci_ini_iox.srcid = m_config_cmd_srcid_fifo.read(); - + p_vci_ini_iox.srcid = m_iox_srcid; + // VCI initiator response on IOX Network // it depends on the CONFIG_RSP FSM state - p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and + p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and ( (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC) or (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI) ); @@ -2404,5 +2586,5 @@ // directly the content of the CONFIG_RSP FIFO p_vci_tgt_int.rspval = m_config_rsp_data_fifo.rok(); - p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); + p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); p_vci_tgt_int.rtrdid = m_config_rsp_rtrdid_fifo.read(); p_vci_tgt_int.rpktid = m_config_rsp_rpktid_fifo.read(); @@ -2410,20 +2592,26 @@ p_vci_tgt_int.rerror = m_config_rsp_rerror_fifo.read(); p_vci_tgt_int.reop = m_config_rsp_reop_fifo.read(); - + // VCI target command ack on INT network // it depends on the CONFIG_CMD FSM state - switch ( r_config_cmd_fsm.read() ) + switch ( r_config_cmd_fsm.read() ) { case CONFIG_CMD_IDLE: - p_vci_tgt_int.cmdack = true; - break; - case CONFIG_CMD_NEXT: - p_vci_tgt_int.cmdack = true; - break; - case CONFIG_CMD_PUT: - p_vci_tgt_int.cmdack = false; - break; - case CONFIG_CMD_RSP: - p_vci_tgt_int.cmdack = false; + p_vci_tgt_int.cmdack = true; + break; + case CONFIG_CMD_WAIT: + p_vci_tgt_int.cmdack = false; + break; + case CONFIG_CMD_HI: + p_vci_tgt_int.cmdack = true; + break; + case CONFIG_CMD_LO: + p_vci_tgt_int.cmdack = true; + break; + case CONFIG_CMD_PUT: + p_vci_tgt_int.cmdack = false; + break; + case CONFIG_CMD_RSP: + p_vci_tgt_int.cmdack = false; break; } @@ -2431,6 +2619,6 @@ ///////////////// p_vci_ini_int //////////////////////////////// - // VCI initiator command on INT network - // directly the content of the MISS_WTI_CMD FIFO + // VCI initiator command on INT network + // directly the content of the MISS_WTI_CMD FIFO p_vci_ini_int.cmdval = m_miss_wti_cmd_addr_fifo.rok(); p_vci_ini_int.address = m_miss_wti_cmd_addr_fifo.read(); @@ -2438,5 +2626,5 @@ p_vci_ini_int.cmd = m_miss_wti_cmd_cmd_fifo.read(); p_vci_ini_int.contig = m_miss_wti_cmd_contig_fifo.read(); - p_vci_ini_int.wdata = m_miss_wti_cmd_data_fifo.read(); + p_vci_ini_int.wdata = m_miss_wti_cmd_data_fifo.read(); p_vci_ini_int.eop = m_miss_wti_cmd_eop_fifo.read(); p_vci_ini_int.cons = m_miss_wti_cmd_cons_fifo.read(); Index: /trunk/modules/vci_io_bridge/include/soclib/io_bridge.h =================================================================== --- /trunk/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 714) +++ /trunk/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 715) @@ -41,6 +41,4 @@ IOB_WTI_ADDR_LO = 7, // R/W : IOB WTI address (32 LSB bits) IOB_WTI_ADDR_HI = 8, // R/W : IOB WTI address (32 MSB bits) - IOB_XICU_BASE = 9, // R/W : XICU pbase address in cluster 0 - IOB_XICU_SIZE = 10, // R/W : XICU segment size /**/ IOB_SPAN = 16,