Index: branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
===================================================================
--- branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 699)
+++ branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 717)
@@ -66,4 +66,10 @@
               flit_width         = parameter.Reference('dspin_int_rsp_width')),
 
+        Uses('caba:dspin_local_crossbar', 
+              flit_width         = parameter.Reference('dspin_ram_cmd_width')),
+
+        Uses('caba:dspin_local_crossbar', 
+              flit_width         = parameter.Reference('dspin_ram_rsp_width')),
+
         Uses('caba:vci_dspin_initiator_wrapper', 
               cell_size          = parameter.Reference('vci_data_width_int'),
@@ -93,8 +99,8 @@
               dspin_rsp_width    = parameter.Reference('dspin_ram_rsp_width')),
 
-        Uses('caba:dspin_router_tsar', 
+        Uses('caba:dspin_router', 
               flit_width         = parameter.Reference('dspin_ram_cmd_width')),
 
-        Uses('caba:dspin_router_tsar', 
+        Uses('caba:dspin_router', 
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
Index: branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
===================================================================
--- branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h	(revision 699)
+++ branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h	(revision 717)
@@ -27,5 +27,5 @@
 #include "vci_dspin_initiator_wrapper.h"
 #include "vci_dspin_target_wrapper.h"
-#include "dspin_router_tsar.h"
+#include "dspin_router.h"
 #include "virtual_dspin_router.h"
 #include "vci_multi_dma.h"
@@ -89,12 +89,4 @@
       soclib::caba::VciTarget<vci_param_ext>*    p_vci_iob_iox_tgt;
 
-      // These ports are used to connect IOB to RAM network in top cell
-      soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out;
-      soclib::caba::DspinInput<dspin_ram_rsp_width>*  p_dspin_iob_rsp_in;
-
-      // These ports are used to connect hard IRQ from external peripherals to
-      // IOB0
-      sc_in<bool>* p_irq[32];
-
       // These arrays of ports are used to connect the INT & RAM networks in
       // top cell
@@ -111,7 +103,7 @@
       // interrupt signals
       sc_signal<bool> signal_false;
-      sc_signal<bool> signal_proc_it[8];
-      sc_signal<bool> signal_irq_mdma[8];
-      sc_signal<bool> signal_irq_mtty[8];
+      sc_signal<bool> signal_proc_it[NB_PROCS*IRQ_PER_PROCESSOR];
+      sc_signal<bool> signal_irq_mdma[NB_DMA_CHANNELS];
+      sc_signal<bool> signal_irq_mtty[NB_DEBUG_TTY_CHANNELS];
       sc_signal<bool> signal_irq_memc;
 
@@ -130,5 +122,5 @@
 
       // INT network VCI signals between VCI components and VCI local crossbar
-      VciSignals<vci_param_int> signal_int_vci_ini_proc[8];
+      VciSignals<vci_param_int> signal_int_vci_ini_proc[NB_PROCS];
       VciSignals<vci_param_int> signal_int_vci_ini_mdma;
       VciSignals<vci_param_int> signal_int_vci_ini_iobx;
@@ -149,7 +141,7 @@
       DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc;
       DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_memc;
-      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[8];
-      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[8];
-      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[8];
+      DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_proc[NB_PROCS];
+      DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_proc[NB_PROCS];
+      DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_proc[NB_PROCS];
 
       // RAM network VCI signals between VCI components and VCI/DSPIN wrappers
@@ -161,6 +153,17 @@
       DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t;
       DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t;
+
       DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i;
       DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i;
+
+      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i;
+      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i;
+
+      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar;
+      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar;
+
+      DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false;
+      DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false;
+
 
       //////////////////////////////////////
@@ -213,6 +216,9 @@
       VciExtDspinTargetWrapperType* xram_ram_wt;
 
-      DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd;
-      DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp;
+      DspinRouter<dspin_ram_cmd_width>* ram_router_cmd;
+      DspinRouter<dspin_ram_rsp_width>* ram_router_rsp;
+
+      DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd;
+      DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp;
 
       // IO Network Components (not instanciated in all clusters)
@@ -232,4 +238,8 @@
          const soclib::common::MappingTable &mt_ext;
          const soclib::common::MappingTable &mt_iox;
+
+         const bool is_io;
+         const soclib::common::IntTab iox_iob_tgtid;
+         const soclib::common::IntTab iox_iob_srcid;
 
          size_t memc_ways;
@@ -243,4 +253,6 @@
          const Loader& loader;
 
+         bool distboot;
+
          uint32_t frozen_cycles;
          uint32_t debug_start_cycle;
@@ -255,4 +267,9 @@
       };
 
+
+      SC_HAS_PROCESS(TsarIobCluster);
+
+      void init();
+
       // cluster constructor
       TsarIobCluster(struct ClusterParams& params);
Index: branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
===================================================================
--- branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp	(revision 699)
+++ branches/fault_tolerance/platform/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp	(revision 717)
@@ -9,7 +9,7 @@
 // Modified on: mars 2014
 //////////////////////////////////////////////////////////////////////////////
-// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
-// These two clusters contain 6 extra components:
-// - 1 vci_io_bridge (connected to the 3 networks.
+// IO clusters contains the IOB component.
+// These clusters contain 6 extra components:
+// - 1 vci_io_bridge (connected to the 3 networks).
 // - 3 vci_dspin_wrapper for the IOB.
 // - 2 dspin_local_crossbar for commands and responses. 
@@ -39,11 +39,5 @@
    assert((params.x_id < X_MAX) && (params.y_id < Y_MAX));
 
-   size_t cid           = this->clusterId(params.x_id, params.y_id);
-   size_t cluster_iob0  = this->clusterId(0, 0);
-   size_t cluster_iob1  = this->clusterId(X_SIZE - 1, Y_SIZE - 1);
-   size_t is_iob0       = (cid == cluster_iob0);
-   size_t is_iob1       = (cid == cluster_iob1);
-   bool   is_io_cluster = is_iob0 || is_iob1;
-
+   size_t cid     = this->clusterId(params.x_id, params.y_id);
    size_t l_width = vci_param_int::S - X_WIDTH - Y_WIDTH;
 
@@ -67,22 +61,13 @@
       alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
 
-   // ports in cluster_iob0 and cluster_iob1 only
+   // ports in IO clusters only
    p_vci_iob_iox_ini   = NULL;
    p_vci_iob_iox_tgt   = NULL;
-   p_dspin_iob_cmd_out = NULL;
-   p_dspin_iob_rsp_in  = NULL;
-   if ( is_io_cluster ) {
+   if ( params.is_io ) {
+      std::cout << "   Creating signals for IOB" << std::endl;
+
       // VCI ports from IOB to IOX network
       p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
       p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 
-
-      // DSPIN ports from IOB to RAM network
-      p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
-      p_dspin_iob_rsp_in  = new soclib::caba::DspinInput<dspin_ram_rsp_width>;
-   }
-
-   // IRQ ports in cluster_iob0 only
-   for ( size_t n = 0 ; n < 32 ; n++ ) {
-      p_irq[n] = ( is_iob0 ) ? new sc_in<bool> : NULL;
    }
 
@@ -110,6 +95,10 @@
             params.debug_start_cycle, params.proc_debug_ok);
 
-      proc[p]->set_dcache_paddr_ext_reset(cid);
-      proc[p]->set_icache_paddr_ext_reset(cid);
+      // Physical address extention register is initialized with local cluster
+      // ID when distributed boot is activated.
+      if (params.distboot) {
+         proc[p]->set_dcache_paddr_ext_reset(cid);
+         proc[p]->set_icache_paddr_ext_reset(cid);
+      }
    }
 
@@ -149,5 +138,5 @@
 
    // Multi-TTY controller
-   mtty        = NULL;
+   mtty = NULL;
    if (NB_DEBUG_TTY_CHANNELS) {
       assert(NB_DEBUG_TTY_CHANNELS < 8);
@@ -175,6 +164,6 @@
          params.mt_int,
          IntTab(cid, INT_XICU_TGT_ID),
-         32, 32, 32,
-         NB_PROCS);
+         32, 1, 32,
+         NB_PROCS * IRQ_PER_PROCESSOR);
 
    ////////////  MDMA
@@ -195,5 +184,5 @@
       nb_direct_targets++;
    }
-   if ( is_io_cluster ) {
+   if ( params.is_io ) {
       nb_direct_initiators++;
       nb_direct_targets++;
@@ -306,40 +295,23 @@
    std::ostringstream s_ram_router_cmd;
    s_ram_router_cmd << "ram_router_cmd_" << params.x_id << "_" << params.y_id;
-   ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>(
+   ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
          s_ram_router_cmd.str().c_str(),
          params.x_id, params.y_id,
          X_WIDTH, Y_WIDTH,
-         4, 4,
-         is_iob0, is_iob1,
-         false,
-         l_width);
+         4, 4);
 
    std::ostringstream s_ram_router_rsp;
    s_ram_router_rsp << "ram_router_rsp_" << params.x_id << "_" << params.y_id;
-   ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>(
+   ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
          s_ram_router_rsp.str().c_str(),
          params.x_id, params.y_id,
          X_WIDTH, Y_WIDTH,
-         4, 4,
-         is_iob0, is_iob1,
-         true,
-         l_width);
+         4, 4);
 
    ////////////////////// I/O  CLUSTER ONLY ///////////////////////
    iob        = NULL;
    iob_ram_wi = NULL;
-   if ( is_io_cluster ) {
+   if ( params.is_io ) {
       ///////////  IO_BRIDGE
-      size_t iox_local_id;
-      bool   has_irqs;
-      if ( is_iob0 ) {
-         iox_local_id = 0;
-         has_irqs     = true;
-      }
-      else {
-         iox_local_id = 1;
-         has_irqs     = false;
-      }
-
       std::ostringstream s_iob;
       s_iob << "iob_" << params.x_id << "_" << params.y_id;   
@@ -351,6 +323,6 @@
             IntTab(cid, INT_IOBX_TGT_ID),
             IntTab(cid, INT_IOBX_INI_ID),
-            IntTab(cid, iox_local_id ),
-            has_irqs,
+            params.iox_iob_tgtid,
+            params.iox_iob_srcid,
             16,
             8,
@@ -364,4 +336,30 @@
             s_iob_ram_wi.str().c_str(),
             vci_param_int::S);
+
+      std::ostringstream s_ram_xbar_cmd;
+      s_ram_xbar_cmd << "s_ram_xbar_cmd_" << params.x_id << "_" << params.y_id;
+      ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
+            s_ram_xbar_cmd.str().c_str(), // name
+            params.mt_ext,                // mapping table
+            params.x_id, params.y_id,     // x, y
+            X_WIDTH, Y_WIDTH, l_width,    // x_width, y_width, l_width
+            2, 0,                         // local inputs, local outputs
+            2, 2,                         // in fifo, out fifo depths
+            true,                         // is cmd ?
+            false,                        // use routing table ?
+            false);                       // support broadcast ?
+
+      std::ostringstream s_ram_xbar_rsp;
+      s_ram_xbar_rsp << "s_ram_xbar_rsp_" << params.x_id << "_" << params.y_id;
+      ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
+            s_ram_xbar_rsp.str().c_str(), // name
+            params.mt_ext,                // mapping table
+            params.x_id, params.y_id,     // x, y
+            X_WIDTH, Y_WIDTH, l_width,    // x_width, y_width, l_width
+            0, 2,                         // local inputs, local outputs
+            2, 2,                         // in fifo, out fifo depths
+            false,                        // is cmd ?
+            true,                         // use routing table ?
+            false);                       // support broadcast ?
    }
 
@@ -372,7 +370,4 @@
    // on coherence network : local srcid[proc] in [0...NB_PROCS-1]
    //                      : local srcid[memc] = NB_PROCS
-   // In cluster_iob0, 32 HWI interrupts from external peripherals
-   // are connected to the XICU ports p_hwi[0:31] 
-   // In other clusters, no HWI interrupts are connected to XICU
 
    //////////////////////// internal CMD & RSP routers
@@ -425,5 +420,5 @@
    }
 
-   if ( is_io_cluster ) {
+   if ( params.is_io ) {
       int_xbar_d->p_to_target[INT_IOBX_TGT_ID]    (signal_int_vci_tgt_iobx);
       int_xbar_d->p_to_initiator[INT_IOBX_INI_ID] (signal_int_vci_ini_iobx);
@@ -480,7 +475,11 @@
       proc[p]->p_dspin_p2m    (signal_int_dspin_p2m_proc[p]);
       proc[p]->p_dspin_clack  (signal_int_dspin_clack_proc[p]);
-      proc[p]->p_irq[0]       (signal_proc_it[p]);
-      for ( size_t j = 1 ; j < 6 ; j++) {
-         proc[p]->p_irq[j]    (signal_false);
+      for ( size_t j = 0 ; j < 6 ; j++) {
+         if ( j < IRQ_PER_PROCESSOR ) {
+            proc[p]->p_irq[j] (signal_proc_it[IRQ_PER_PROCESSOR * p + j]);
+         }
+         else {
+            proc[p]->p_irq[j] (signal_false);
+         }
       }
    }
@@ -490,13 +489,8 @@
    xicu->p_resetn (this->p_resetn);
    xicu->p_vci    (signal_int_vci_tgt_xicu);
-   for ( size_t p = 0 ; p < NB_PROCS ; p++) {
-      xicu->p_irq[p] (signal_proc_it[p]);
-   }
-   for ( size_t i=0 ; i<32 ; i++) {
-      if ( is_iob0 ) 
-         xicu->p_hwi[i] (*(this->p_irq[i]));
-      else  
-         xicu->p_hwi[i] (signal_false);
-   }                     
+   for ( size_t irq = 0 ; irq < (IRQ_PER_PROCESSOR * NB_PROCS) ; irq++) {
+      xicu->p_irq[irq] (signal_proc_it[irq]);
+   }
+   xicu->p_hwi[0] (signal_irq_memc);
 
    ///////////////////////////////////// MEMC
@@ -564,11 +558,15 @@
       ram_router_rsp->p_in[n]  (this->p_dspin_ram_rsp_in[n]);
    }
-   ram_router_cmd->p_out[4]    (signal_ram_dspin_cmd_xram_t);
-   ram_router_cmd->p_in[4]     (signal_ram_dspin_cmd_memc_i);
-   ram_router_rsp->p_out[4]    (signal_ram_dspin_rsp_memc_i);
-   ram_router_rsp->p_in[4]     (signal_ram_dspin_rsp_xram_t);
-
-   ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 
-   if ( is_io_cluster ) {
+
+   ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
+   if (params.is_io) ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
+   else              ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
+
+   ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
+   if (params.is_io) ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
+   else              ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
+
+   ///////////////////////// IOB exists only in IO clusters. 
+   if ( params.is_io ) {
       // IO bridge
       iob->p_clk         (this->p_clk);
@@ -580,30 +578,41 @@
       iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
 
-      if ( is_iob0 ) {
-         for ( size_t n = 0 ; n < 32 ; n++ ) {
-            (*iob->p_irq[n]) (*(this->p_irq[n]));
-         }
-      }
-
       // initiator wrapper to RAM network
-      iob_ram_wi->p_clk       (this->p_clk);
-      iob_ram_wi->p_resetn    (this->p_resetn);
-      iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out));
-      iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in));
-      iob_ram_wi->p_vci       (signal_ram_vci_ini_iobx);
-   }
+      iob_ram_wi->p_clk            (this->p_clk);
+      iob_ram_wi->p_resetn         (this->p_resetn);
+      iob_ram_wi->p_dspin_cmd      (signal_ram_dspin_cmd_iob_i);
+      iob_ram_wi->p_dspin_rsp      (signal_ram_dspin_rsp_iob_i);
+      iob_ram_wi->p_vci            (signal_ram_vci_ini_iobx);
+
+      ram_xbar_cmd->p_clk          (this->p_clk);
+      ram_xbar_cmd->p_resetn       (this->p_resetn);
+      ram_xbar_cmd->p_global_out   (signal_ram_dspin_cmd_xbar);
+      ram_xbar_cmd->p_global_in    (signal_ram_dspin_cmd_false);
+      ram_xbar_cmd->p_local_in[0]  (signal_ram_dspin_cmd_memc_i);
+      ram_xbar_cmd->p_local_in[1]  (signal_ram_dspin_cmd_iob_i);
+
+      ram_xbar_rsp->p_clk          (this->p_clk);
+      ram_xbar_rsp->p_resetn       (this->p_resetn);
+      ram_xbar_rsp->p_global_out   (signal_ram_dspin_rsp_false);
+      ram_xbar_rsp->p_global_in    (signal_ram_dspin_rsp_xbar);
+      ram_xbar_rsp->p_local_out[0] (signal_ram_dspin_rsp_memc_i);
+      ram_xbar_rsp->p_local_out[1] (signal_ram_dspin_rsp_iob_i);
+   }
+
+   SC_METHOD(init);
 } // end constructor
+
+tmpl(void)::init() {
+   signal_ram_dspin_cmd_false.write = false;
+   signal_ram_dspin_cmd_false.read = true;
+   signal_ram_dspin_rsp_false.write = false;
+   signal_ram_dspin_rsp_false.read = true;
+}
 
 tmpl(/**/)::~TsarIobCluster() {
    if (p_vci_iob_iox_ini)   delete p_vci_iob_iox_ini;
    if (p_vci_iob_iox_tgt)   delete p_vci_iob_iox_tgt;
-   if (p_dspin_iob_cmd_out) delete p_dspin_iob_cmd_out;
-   if (p_dspin_iob_rsp_in)  delete p_dspin_iob_rsp_in;
    if (iob)                 delete iob;
    if (iob_ram_wi)          delete iob_ram_wi;
-
-   for (size_t n = 0 ; n < 32 ; n++) {
-      if (p_irq[n]) delete p_irq[n];
-   }
 
    for (size_t p = 0; p < NB_PROCS; p++) { 
@@ -627,4 +636,6 @@
    delete ram_router_cmd;
    delete ram_router_rsp;
+   delete ram_xbar_cmd;
+   delete ram_xbar_rsp;
 }
 
